Hi,
This series adds support for PWM controller on new
Allwinner's SoCs, such as D1, T113s and R329. The implemented driver
provides basic functionality for control PWM channels.
v2:
- fix dt-bindings
- fix a remark in the driver
v3:
- fix dt-bindings
- fix sunxi-d1s-t113.dtsi
v4:
- fix a remark in the driver
v5:
- dropped unused varibale in the driver
- fix dt-bindings
Aleksandr Shubin (3):
dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM
controller
pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support
riscv: dts: allwinner: d1: Add pwm node
.../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++
.../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sun20i.c | 323 ++++++++++++++++++
5 files changed, 430 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
create mode 100644 drivers/pwm/pwm-sun20i.c
--
2.25.1
Allwinner's D1, T113-S3 and R329 SoCs have a new pwm
controller witch is different from the previous pwm-sun4i.
The D1 and T113 are identical in terms of peripherals,
they differ only in the architecture of the CPU core, and
even share the majority of their DT. Because of that,
using the same compatible makes sense.
The R329 is a different SoC though, and should have
a different compatible string added, especially as there
is a difference in the number of channels.
D1 and T113s SoCs have one PWM controller with 8 channels.
R329 SoC has two PWM controllers in both power domains, one of
them has 9 channels (CPUX one) and the other has 6 (CPUS one).
Add a device tree binding for them.
Signed-off-by: Aleksandr Shubin <[email protected]>
---
.../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
new file mode 100644
index 000000000000..9512d4bed322
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner D1, T113-S3 and R329 PWM
+
+maintainers:
+ - Aleksandr Shubin <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun20i-d1-pwm
+ - items:
+ - const: allwinner,sun20i-r329-pwm
+ - const: allwinner,sun20i-d1-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+ clocks:
+ items:
+ - description: 24 MHz oscillator
+ - description: Bus Clock
+
+ clock-names:
+ items:
+ - const: hosc
+ - const: bus
+
+ resets:
+ maxItems: 1
+
+ allwinner,pwm-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The number of PWM channels configured for this instance
+ enum: [6, 9]
+
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun20i-r329-pwm
+
+ then:
+ required:
+ - allwinner,pwm-channels
+
+ else:
+ properties:
+ allwinner,pwm-channels: false
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+ - clocks
+ - clock-names
+ - resets
+
+examples:
+ - |
+ #include <dt-bindings/clock/sun20i-d1-ccu.h>
+ #include <dt-bindings/reset/sun20i-d1-ccu.h>
+
+ pwm: pwm@2000c00 {
+ compatible = "allwinner,sun20i-d1-pwm";
+ reg = <0x02000c00 0x400>;
+ clocks = <&dcxo>, <&ccu CLK_BUS_PWM>;
+ clock-names = "hosc", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ #pwm-cells = <0x3>;
+ };
+
+...
--
2.25.1
D1 and T113s contain a pwm controller with 8 channels.
This controller is supported by the sun20i-pwm driver.
Add a device tree node for it.
Signed-off-by: Aleksandr Shubin <[email protected]>
---
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 922e8e0e2c09..e24543b6aff7 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -127,6 +127,17 @@ uart3_pb_pins: uart3-pb-pins {
};
};
+ pwm: pwm@2000c00 {
+ compatible = "allwinner,sun20i-d1-pwm";
+ reg = <0x02000c00 0x400>;
+ clocks = <&dcxo>,
+ <&ccu CLK_BUS_PWM>;
+ clock-names = "hosc", "bus";
+ resets = <&ccu RST_BUS_PWM>;
+ status = "disabled";
+ #pwm-cells = <0x3>;
+ };
+
ccu: clock-controller@2001000 {
compatible = "allwinner,sun20i-d1-ccu";
reg = <0x2001000 0x1000>;
--
2.25.1
On Mon, 14 Aug 2023 16:32:16 +0300
Aleksandr Shubin <[email protected]> wrote:
Hi Aleksandr,
> Allwinner's D1, T113-S3 and R329 SoCs have a new pwm
> controller witch is different from the previous pwm-sun4i.
>
> The D1 and T113 are identical in terms of peripherals,
> they differ only in the architecture of the CPU core, and
> even share the majority of their DT. Because of that,
> using the same compatible makes sense.
> The R329 is a different SoC though, and should have
> a different compatible string added, especially as there
> is a difference in the number of channels.
>
> D1 and T113s SoCs have one PWM controller with 8 channels.
> R329 SoC has two PWM controllers in both power domains, one of
> them has 9 channels (CPUX one) and the other has 6 (CPUS one).
>
> Add a device tree binding for them.
>
> Signed-off-by: Aleksandr Shubin <[email protected]>
> ---
> .../bindings/pwm/allwinner,sun20i-pwm.yaml | 85 +++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
> new file mode 100644
> index 000000000000..9512d4bed322
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner D1, T113-S3 and R329 PWM
> +
> +maintainers:
> + - Aleksandr Shubin <[email protected]>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: allwinner,sun20i-d1-pwm
> + - items:
> + - const: allwinner,sun20i-r329-pwm
> + - const: allwinner,sun20i-d1-pwm
> +
> + reg:
> + maxItems: 1
> +
> + "#pwm-cells":
> + const: 3
> +
> + clocks:
> + items:
> + - description: 24 MHz oscillator
> + - description: Bus Clock
The manual tells me that the new PWMs can also use APB0 as the
input clock, which (finally!) allows PWM frequencies above 24 MHz.
So we should have an explicit reference to that clock - even if the bus
clock happens to be gated version of APB0.
Cheers,
Andre
> +
> + clock-names:
> + items:
> + - const: hosc
> + - const: bus
> +
> + resets:
> + maxItems: 1
> +
> + allwinner,pwm-channels:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: The number of PWM channels configured for this instance
> + enum: [6, 9]
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: allwinner,sun20i-r329-pwm
> +
> + then:
> + required:
> + - allwinner,pwm-channels
> +
> + else:
> + properties:
> + allwinner,pwm-channels: false
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - "#pwm-cells"
> + - clocks
> + - clock-names
> + - resets
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/sun20i-d1-ccu.h>
> + #include <dt-bindings/reset/sun20i-d1-ccu.h>
> +
> + pwm: pwm@2000c00 {
> + compatible = "allwinner,sun20i-d1-pwm";
> + reg = <0x02000c00 0x400>;
> + clocks = <&dcxo>, <&ccu CLK_BUS_PWM>;
> + clock-names = "hosc", "bus";
> + resets = <&ccu RST_BUS_PWM>;
> + #pwm-cells = <0x3>;
> + };
> +
> +...