2023-09-21 18:06:36

by Wenhua Lin

[permalink] [raw]
Subject: [PATCH V2 0/4] gpio: sprd: Modification of UNISOC Platform EIC Driver

Recently, some bugs have been discovered during use, and patch1
and patch2 are bug fixes. Also, this patchset add optimization:
patch3 optimization the calculation method of eic number,
and patch4 Support 8 banks EIC controller.

Change in V2:
-Using thread send 4 patches

-The dbnc of the title is changed to debounce in PATCH 1/4.
-Add Fixes tag in PATCH 1/4.

-Change commit message and title in PATCH 2/4.

-Change commit message in PATCH 3/4.
-Remove modifications to SPRD_EIC_MAX_BANK macro in PATCH 3/4.
-Remove modifications to fallthrough in PATCH 3/4.
-Add Fixes tag in PATCH 3/4.

-PATCH 3/4 macro modify split into a separate patch in PATCH 4/4.
-Change related comments in PATCH 4/4.

Wenhua Lin (4):
gpio: sprd: In the sleep state, the eic debounce clk must be forced
open
gpio: sprd: Clear interrupt after set the interrupt type
gpio: sprd: Modify the calculation method of eic number
gpio: sprd: Support 8 banks EIC controller

drivers/gpio/gpio-eic-sprd.c | 63 ++++++++++++++++++++++--------------
1 file changed, 38 insertions(+), 25 deletions(-)

--
2.17.1


2023-09-21 20:15:40

by Wenhua Lin

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Subject: [PATCH V2 2/4] gpio: sprd: Clear interrupt after set the interrupt type

The initialization state of the EIC module is a high level trigger.
If it is currently a high level, the interrupt condition is met at
this time, and the EIC interrupt has a latch capability, which will
cause an interrupt to occur after booting. To avoid this, When setting
the EIC interrupt trigger type, clear the interrupt once.

Signed-off-by: Wenhua Lin <[email protected]>
---
drivers/gpio/gpio-eic-sprd.c | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
index bfa8a4c7515a..96f1c7fd3988 100644
--- a/drivers/gpio/gpio-eic-sprd.c
+++ b/drivers/gpio/gpio-eic-sprd.c
@@ -375,29 +375,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
@@ -410,29 +415,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_BOTH:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
+ sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
irq_set_handler_locked(data, handle_level_irq);
break;
default:
--
2.17.1

2023-09-21 20:36:50

by Wenhua Lin

[permalink] [raw]
Subject: [PATCH V2 4/4] gpio: sprd: Support 8 banks EIC controller

In order to solve the problem of insufficient eic,
it supports 8 banks of eic controller, each bank contains 8 eic.

Signed-off-by: Wenhua Lin <[email protected]>
---
drivers/gpio/gpio-eic-sprd.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
index e85addbdf8aa..6bb002060c3e 100644
--- a/drivers/gpio/gpio-eic-sprd.c
+++ b/drivers/gpio/gpio-eic-sprd.c
@@ -51,10 +51,10 @@
#define SPRD_EIC_SYNC_DATA 0x1c

/*
- * The digital-chip EIC controller can support maximum 3 banks, and each bank
+ * The digital-chip EIC controller can support maximum 8 banks, and each bank
* contains 8 EICs.
*/
-#define SPRD_EIC_MAX_BANK 3
+#define SPRD_EIC_MAX_BANK 8
#define SPRD_EIC_PER_BANK_NR 8
#define SPRD_EIC_DATA_MASK GENMASK(7, 0)
#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
@@ -615,9 +615,9 @@ static int sprd_eic_probe(struct platform_device *pdev)

for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
/*
- * We can have maximum 3 banks EICs, and each EIC has
+ * We can have maximum 8 banks EICs, and each EIC has
* its own base address. But some platform maybe only
- * have one bank EIC, thus base[1] and base[2] can be
+ * have one bank EIC, thus base[1] and base[7] can be
* optional.
*/
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
--
2.17.1

2023-09-27 09:52:38

by Baolin Wang

[permalink] [raw]
Subject: Re: [PATCH V2 4/4] gpio: sprd: Support 8 banks EIC controller



On 9/21/2023 5:00 PM, Wenhua Lin wrote:
> In order to solve the problem of insufficient eic,
> it supports 8 banks of eic controller, each bank contains 8 eic.
>
> Signed-off-by: Wenhua Lin <[email protected]>
> ---
> drivers/gpio/gpio-eic-sprd.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
> index e85addbdf8aa..6bb002060c3e 100644
> --- a/drivers/gpio/gpio-eic-sprd.c
> +++ b/drivers/gpio/gpio-eic-sprd.c
> @@ -51,10 +51,10 @@
> #define SPRD_EIC_SYNC_DATA 0x1c
>
> /*
> - * The digital-chip EIC controller can support maximum 3 banks, and each bank
> + * The digital-chip EIC controller can support maximum 8 banks, and each bank
> * contains 8 EICs.
> */
> -#define SPRD_EIC_MAX_BANK 3
> +#define SPRD_EIC_MAX_BANK 8
> #define SPRD_EIC_PER_BANK_NR 8
> #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
> #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
> @@ -615,9 +615,9 @@ static int sprd_eic_probe(struct platform_device *pdev)
>
> for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
> /*
> - * We can have maximum 3 banks EICs, and each EIC has
> + * We can have maximum 8 banks EICs, and each EIC has
> * its own base address. But some platform maybe only
> - * have one bank EIC, thus base[1] and base[2] can be
> + * have one bank EIC, thus base[1] and base[7] can be

Should be "base[1] to base[7]"

> * optional.
> */
> res = platform_get_resource(pdev, IORESOURCE_MEM, i);

2023-09-27 10:57:21

by Baolin Wang

[permalink] [raw]
Subject: Re: [PATCH V2 2/4] gpio: sprd: Clear interrupt after set the interrupt type



On 9/21/2023 5:00 PM, Wenhua Lin wrote:
> The initialization state of the EIC module is a high level trigger.
> If it is currently a high level, the interrupt condition is met at
> this time, and the EIC interrupt has a latch capability, which will
> cause an interrupt to occur after booting. To avoid this, When setting
> the EIC interrupt trigger type, clear the interrupt once.

With Andy's comments,
Reviewed-by: Baolin Wang <[email protected]>

> Signed-off-by: Wenhua Lin <[email protected]>
> ---
> drivers/gpio/gpio-eic-sprd.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
> index bfa8a4c7515a..96f1c7fd3988 100644
> --- a/drivers/gpio/gpio-eic-sprd.c
> +++ b/drivers/gpio/gpio-eic-sprd.c
> @@ -375,29 +375,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
> + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_edge_irq);
> break;
> case IRQ_TYPE_EDGE_FALLING:
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
> + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_edge_irq);
> break;
> case IRQ_TYPE_EDGE_BOTH:
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
> + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_edge_irq);
> break;
> case IRQ_TYPE_LEVEL_HIGH:
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
> + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_level_irq);
> break;
> case IRQ_TYPE_LEVEL_LOW:
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
> sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
> + sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_level_irq);
> break;
> default:
> @@ -410,29 +415,34 @@ static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
> + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_edge_irq);
> break;
> case IRQ_TYPE_EDGE_FALLING:
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
> + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_edge_irq);
> break;
> case IRQ_TYPE_EDGE_BOTH:
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
> + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_edge_irq);
> break;
> case IRQ_TYPE_LEVEL_HIGH:
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
> + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_level_irq);
> break;
> case IRQ_TYPE_LEVEL_LOW:
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
> sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
> + sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
> irq_set_handler_locked(data, handle_level_irq);
> break;
> default:

2024-01-03 12:04:05

by wenhua lin

[permalink] [raw]
Subject: Re: [PATCH V2 4/4] gpio: sprd: Support 8 banks EIC controller

On Wed, Sep 27, 2023 at 5:28 PM Baolin Wang
<[email protected]> wrote:
>
>
>
> On 9/21/2023 5:00 PM, Wenhua Lin wrote:
> > In order to solve the problem of insufficient eic,
> > it supports 8 banks of eic controller, each bank contains 8 eic.
> >
> > Signed-off-by: Wenhua Lin <[email protected]>
> > ---
> > drivers/gpio/gpio-eic-sprd.c | 8 ++++----
> > 1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-eic-sprd.c b/drivers/gpio/gpio-eic-sprd.c
> > index e85addbdf8aa..6bb002060c3e 100644
> > --- a/drivers/gpio/gpio-eic-sprd.c
> > +++ b/drivers/gpio/gpio-eic-sprd.c
> > @@ -51,10 +51,10 @@
> > #define SPRD_EIC_SYNC_DATA 0x1c
> >
> > /*
> > - * The digital-chip EIC controller can support maximum 3 banks, and each bank
> > + * The digital-chip EIC controller can support maximum 8 banks, and each bank
> > * contains 8 EICs.
> > */
> > -#define SPRD_EIC_MAX_BANK 3
> > +#define SPRD_EIC_MAX_BANK 8
> > #define SPRD_EIC_PER_BANK_NR 8
> > #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
> > #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
> > @@ -615,9 +615,9 @@ static int sprd_eic_probe(struct platform_device *pdev)
> >
> > for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
> > /*
> > - * We can have maximum 3 banks EICs, and each EIC has
> > + * We can have maximum 8 banks EICs, and each EIC has
> > * its own base address. But some platform maybe only
> > - * have one bank EIC, thus base[1] and base[2] can be
> > + * have one bank EIC, thus base[1] and base[7] can be
>
> Should be "base[1] to base[7]"

Thank you very much for your review.
I will fix this issue in patch v3.

>
> > * optional.
> > */
> > res = platform_get_resource(pdev, IORESOURCE_MEM, i);