Current driver is supports up to 16 buses. The following code fixes
to support up to 256 buses.
update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
region to detect 256 buses.
Update ecam size to 256MB in device tree binding example.
Remove unwanted code.
Thippeswamy Havalige (4):
PCI: xilinx-nwl: Remove unnecessary code which updates primary,
secondary and sub-ordinate bus numbers
dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
PCI: xilinx-nwl: Rename ECAM size default macro
PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
.../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++---------------
2 files changed, 4 insertions(+), 16 deletions(-)
--
2.25.1
Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove
redundant code
Signed-off-by: Thippeswamy Havalige <[email protected]>
---
changes in v5:
Remove period at end of subject line.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index d8a3a08be1d5..8fe0e8a325b0 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_VALUE_DEFAULT 12
+#define NWL_ECAM_MAX_SIZE 12
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
@@ -165,7 +165,6 @@ struct nwl_pcie {
u32 ecam_size;
int irq_intx;
int irq_misc;
- u32 ecam_value;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
struct clk *clk;
@@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
- (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
+ (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),
E_ECAM_CONTROL);
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
@@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
pcie = pci_host_bridge_priv(bridge);
pcie->dev = dev;
- pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
err = nwl_pcie_parse_dt(pcie, pdev);
if (err) {
--
2.25.1
The primary,secondary and sub-ordinate bus number registers are updated by
Linux PCI core, so remove code which updates respective fields of type 1
header.
Signed-off-by: Thippeswamy Havalige <[email protected]>
---
changes in v5:
- None
changes in v4:
- None
changes in v3:
- Remove unnecessary period at end of subject line.
- Updated commit message.
changes in v2:
- Code increasing ECAM Size value is added into a seperate patch.
- Modified commit messages.
changes in v1:
- Modified commit messages.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 176686bdb15c..d8a3a08be1d5 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -166,7 +166,6 @@ struct nwl_pcie {
int irq_intx;
int irq_misc;
u32 ecam_value;
- u8 last_busno;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
struct clk *clk;
@@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
{
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
- u32 breg_val, ecam_val, first_busno = 0;
+ u32 breg_val, ecam_val;
int err;
breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
@@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
E_ECAM_BASE_HI);
- /* Get bus range */
- ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
- pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
- /* Write primary, secondary and subordinate bus numbers */
- ecam_val = first_busno;
- ecam_val |= (first_busno + 1) << 8;
- ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
- writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
-
if (nwl_pcie_link_up(pcie))
dev_info(dev, "Link is UP\n");
else
--
2.25.1
Update ECAM size in example to discover up to 256 buses.
Signed-off-by: Thippeswamy Havalige <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
changes in v5:
None
changes in v4:
None
changes in v3:
Remove period at end of subject line
changes in v2:
None.
changes in v1:
None.
---
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 897602559b37..426f90a47f35 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -118,7 +118,7 @@ examples:
compatible = "xlnx,nwl-pcie-2.11";
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
--
2.25.1
Our controller is expecting ECAM size to be programmed by software. By
programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB
ECAM region which is used to detect 16 buses, so by updating
"NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB
ECAM region to detect 256 buses.
Signed-off-by: Thippeswamy Havalige <[email protected]>
---
changes in v5:
None.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 8fe0e8a325b0..e307aceba5c9 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_MAX_SIZE 12
+#define NWL_ECAM_MAX_SIZE 16
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
--
2.25.1
Hi Bjorn,
Can you please provide an update on this patch series.
Regards,
Thippeswamy H
> -----Original Message-----
> From: Thippeswamy Havalige <[email protected]>
> Sent: Monday, October 16, 2023 10:41 AM
> To: [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> Havalige, Thippeswamy <[email protected]>; Simek, Michal
> <[email protected]>; Gogada, Bharat Kumar
> <[email protected]>
> Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
> buses during
>
> Current driver is supports up to 16 buses. The following code fixes to support
> up to 256 buses.
>
> update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
> region to detect 256 buses.
>
> Update ecam size to 256MB in device tree binding example.
>
> Remove unwanted code.
>
> Thippeswamy Havalige (4):
> PCI: xilinx-nwl: Remove unnecessary code which updates primary,
> secondary and sub-ordinate bus numbers
> dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
> PCI: xilinx-nwl: Rename ECAM size default macro
> PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
>
> .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
> drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++---------------
> 2 files changed, 4 insertions(+), 16 deletions(-)
>
> --
> 2.25.1
On Fri, Oct 20, 2023 at 10:35:46AM +0000, Havalige, Thippeswamy wrote:
> Hi Bjorn,
>
> Can you please provide an update on this patch series.
As with your Xilinx XDMA Soft IP series, I hope to get this merged for
v6.7.
Would you take a quick look at patchwork here:
https://patchwork.kernel.org/project/linux-pci/list/?submitter=207519
to make sure that everything you're waiting on is listed there?
I cleaned out things that appeared to be older versions of the
"Increase ECAM size" and the "Add support for Xilinx XDMA Soft IP"
series, but the subject lines didn't always match exactly, so it's
possible I incorrectly marked something as "superseded".
Bjorn
> > -----Original Message-----
> > From: Thippeswamy Havalige <[email protected]>
> > Sent: Monday, October 16, 2023 10:41 AM
> > To: [email protected]; [email protected]; linux-
> > [email protected]; [email protected]
> > Cc: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > Havalige, Thippeswamy <[email protected]>; Simek, Michal
> > <[email protected]>; Gogada, Bharat Kumar
> > <[email protected]>
> > Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
> > buses during
> >
> > Current driver is supports up to 16 buses. The following code fixes to support
> > up to 256 buses.
> >
> > update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
> > region to detect 256 buses.
> >
> > Update ecam size to 256MB in device tree binding example.
> >
> > Remove unwanted code.
> >
> > Thippeswamy Havalige (4):
> > PCI: xilinx-nwl: Remove unnecessary code which updates primary,
> > secondary and sub-ordinate bus numbers
> > dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
> > PCI: xilinx-nwl: Rename ECAM size default macro
> > PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
> >
> > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
> > drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++---------------
> > 2 files changed, 4 insertions(+), 16 deletions(-)
> >
> > --
> > 2.25.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi Bjorn,
Thanks for update, provided list consist of all submitted patches for both the series.
Regards,
Thippeswamy H
> -----Original Message-----
> From: Bjorn Helgaas <[email protected]>
> Sent: Monday, October 23, 2023 10:57 PM
> To: Havalige, Thippeswamy <[email protected]>
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Simek, Michal
> <[email protected]>; Gogada, Bharat Kumar
> <[email protected]>
> Subject: Re: [PATCH v5 RESEND 0/4] increase ecam size value to discover 256
> buses during
>
> On Fri, Oct 20, 2023 at 10:35:46AM +0000, Havalige, Thippeswamy wrote:
> > Hi Bjorn,
> >
> > Can you please provide an update on this patch series.
>
> As with your Xilinx XDMA Soft IP series, I hope to get this merged for v6.7.
>
> Would you take a quick look at patchwork here:
> https://patchwork.kernel.org/project/linux-pci/list/?submitter=207519
> to make sure that everything you're waiting on is listed there?
>
> I cleaned out things that appeared to be older versions of the "Increase ECAM
> size" and the "Add support for Xilinx XDMA Soft IP"
> series, but the subject lines didn't always match exactly, so it's possible I
> incorrectly marked something as "superseded".
>
> Bjorn
>
> > > -----Original Message-----
> > > From: Thippeswamy Havalige <[email protected]>
> > > Sent: Monday, October 16, 2023 10:41 AM
> > > To: [email protected]; [email protected]; linux-
> > > [email protected]; [email protected]
> > > Cc: [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; Havalige, Thippeswamy
> > > <[email protected]>; Simek, Michal
> > > <[email protected]>; Gogada, Bharat Kumar
> > > <[email protected]>
> > > Subject: [PATCH v5 RESEND 0/4] increase ecam size value to discover
> > > 256 buses during
> > >
> > > Current driver is supports up to 16 buses. The following code fixes
> > > to support up to 256 buses.
> > >
> > > update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB
> ECAM
> > > region to detect 256 buses.
> > >
> > > Update ecam size to 256MB in device tree binding example.
> > >
> > > Remove unwanted code.
> > >
> > > Thippeswamy Havalige (4):
> > > PCI: xilinx-nwl: Remove unnecessary code which updates primary,
> > > secondary and sub-ordinate bus numbers
> > > dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
> > > PCI: xilinx-nwl: Rename ECAM size default macro
> > > PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses
> > >
> > > .../devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
> > > drivers/pci/controller/pcie-xilinx-nwl.c | 18 +++---------------
> > > 2 files changed, 4 insertions(+), 16 deletions(-)
> > >
> > > --
> > > 2.25.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hello,
> Current driver is supports up to 16 buses. The following code fixes
> to support up to 256 buses.
>
> update "NWL_ECAM_VALUE_DEFAULT " to 16 can access up to 256MB ECAM
> region to detect 256 buses.
>
> Update ecam size to 256MB in device tree binding example.
>
> Remove unwanted code.
Applied to controller/xilinx-ecam, thank you!
[01/04] PCI: xilinx-nwl: Remove redundant code that sets Type 1 header fields
https://git.kernel.org/pci/pci/c/a2492ff1fcb9
[02/04] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in the DT example
https://git.kernel.org/pci/pci/c/22f38a244273
[03/04] PCI: xilinx-nwl: Rename the NWL_ECAM_VALUE_DEFAULT macro
https://git.kernel.org/pci/pci/c/177692115f6f
[04/04] PCI: xilinx-nwl: Modify ECAM size to enable support for 256 buses
https://git.kernel.org/pci/pci/c/2fccd11518f1
Krzysztof