Add device tree documentation for the AXI TDD Core.
The generic TDD controller is in essence a waveform generator
capable of addressing RF applications which require Time Division
Duplexing, as well as controlling other modules of general
applications through its dedicated 32 channel outputs.
Signed-off-by: Eliza Balas <[email protected]>
---
.../devicetree/bindings/misc/adi,axi-tdd.yaml | 65 +++++++++++++++++++
MAINTAINERS | 7 ++
2 files changed, 72 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
diff --git a/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml b/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
new file mode 100644
index 000000000000..4449d9abf46e
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2023 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/adi,axi-tdd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AXI TDD Core
+
+maintainers:
+ - Eliza Balas <[email protected]>
+
+description: |
+ The TDD controller is a waveform generator capable of addressing RF
+ applications which require Time Division Duplexing, as well as controlling
+ other modules of general applications through its dedicated 32 channel
+ outputs. It solves the synchronization issue when transmitting and receiving
+ multiple frames of data through multiple buffers.
+ The TDD IP core is part of the Analog Devices hdl reference designs and has
+ the following features:
+ * Up to 32 independent output channels
+ * Start/stop time values per channel
+ * Enable and polarity bit values per channel
+ * 32 bit-max internal reference counter
+ * Initial startup delay before waveform generation
+ * Configurable frame length and number of frames per burst
+ * 3 sources of synchronization: external, internal and software generated
+ For more information see the wiki:
+ https://wiki.analog.com/resources/fpga/docs/axi_tdd
+
+properties:
+ compatible:
+ enum:
+ - adi,axi-tdd
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: System clock
+ - description: TDD Core clock
+
+ clock-names:
+ items:
+ - const: s_axi_aclk
+ - const: intf_clk
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ tdd@84a00000 {
+ compatible = "adi,axi-tdd";
+ reg = <0x84a00000 0x10000>;
+ clocks = <&zynqmp_clk_PL0_REF>, <&zynqmp_clk_PL1_REF>;
+ clock-names = "s_axi_aclk", "intf_clk";
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 59831c69a275..13a1e1990c19 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1344,6 +1344,13 @@ S: Supported
W: https://ez.analog.com/linux-software-drivers
F: drivers/dma/dma-axi-dmac.c
+ANALOG DEVICES INC GENERIC TDD ENGINE DRIVER
+M: Eliza Balas <[email protected]>
+S: Supported
+W: http://wiki.analog.com/resources/fpga/docs/axi_tdd
+W: http://ez.analog.com/linux-software-drivers/
+F: Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
+
ANALOG DEVICES INC IIO DRIVERS
M: Lars-Peter Clausen <[email protected]>
M: Michael Hennerich <[email protected]>
--
2.25.1
On Thu, Oct 19, 2023 at 03:56:45PM +0300, Eliza Balas wrote:
> Add device tree documentation for the AXI TDD Core.
> The generic TDD controller is in essence a waveform generator
> capable of addressing RF applications which require Time Division
> Duplexing, as well as controlling other modules of general
> applications through its dedicated 32 channel outputs.
>
> Signed-off-by: Eliza Balas <[email protected]>
> ---
> .../devicetree/bindings/misc/adi,axi-tdd.yaml | 65 +++++++++++++++++++
> MAINTAINERS | 7 ++
> 2 files changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
>
> diff --git a/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml b/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
> new file mode 100644
> index 000000000000..4449d9abf46e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright 2023 Analog Devices Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/misc/adi,axi-tdd.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AXI TDD Core
> +
> +maintainers:
> + - Eliza Balas <[email protected]>
> +
> +description: |
> + The TDD controller is a waveform generator capable of addressing RF
> + applications which require Time Division Duplexing, as well as controlling
> + other modules of general applications through its dedicated 32 channel
> + outputs. It solves the synchronization issue when transmitting and receiving
> + multiple frames of data through multiple buffers.
> + The TDD IP core is part of the Analog Devices hdl reference designs and has
> + the following features:
> + * Up to 32 independent output channels
> + * Start/stop time values per channel
> + * Enable and polarity bit values per channel
> + * 32 bit-max internal reference counter
> + * Initial startup delay before waveform generation
> + * Configurable frame length and number of frames per burst
> + * 3 sources of synchronization: external, internal and software generated
> + For more information see the wiki:
> + https://wiki.analog.com/resources/fpga/docs/axi_tdd
> +
> +properties:
> + compatible:
> + enum:
> + - adi,axi-tdd
I don't understand where the version number went. Now my question is is
there only one version of this (ever). It's not specific enough unless
there's a version register that can be relied on.
This patch needs to answer any questions raised in previous versions.
Assume the reviewers don't remember your patch and will ask the same
questions again otherwise.
Rob
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Tuesday, October 24, 2023 22:10
> To: Balas, Eliza <[email protected]>
> Cc: [email protected]; [email protected]; Krzysztof Kozlowski <[email protected]>; Conor
> Dooley <[email protected]>; Derek Kiernan <[email protected]>; Dragan Cvetic <[email protected]>; Arnd
> Bergmann <[email protected]>; Greg Kroah-Hartman <[email protected]>
> Subject: Re: [PATCH v3 1/2] dt-bindings: misc: adi,axi-tdd: Add device-tree binding for TDD engine
>
> [External]
>
> On Thu, Oct 19, 2023 at 03:56:45PM +0300, Eliza Balas wrote:
> > Add device tree documentation for the AXI TDD Core.
> > The generic TDD controller is in essence a waveform generator
> > capable of addressing RF applications which require Time Division
> > Duplexing, as well as controlling other modules of general
> > applications through its dedicated 32 channel outputs.
> >
> > Signed-off-by: Eliza Balas <[email protected]>
> > ---
> > .../devicetree/bindings/misc/adi,axi-tdd.yaml | 65 +++++++++++++++++++
> > MAINTAINERS | 7 ++
> > 2 files changed, 72 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml b/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
> > new file mode 100644
> > index 000000000000..4449d9abf46e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/misc/adi,axi-tdd.yaml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright 2023 Analog Devices Inc.
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/misc/adi,axi-
> tdd.yaml*__;Iw!!A3Ni8CS0y2Y!4FubpNBZ9iITDA4tWD49qCUp7AqEs72W2OQmpSkLyK2lCiWNWSbXGS6MGhJSdKMVza7CV5IRsVxNlA$
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-
> schemas/core.yaml*__;Iw!!A3Ni8CS0y2Y!4FubpNBZ9iITDA4tWD49qCUp7AqEs72W2OQmpSkLyK2lCiWNWSbXGS6MGhJSdKMVza7CV5
> J20y6r-A$
> > +
> > +title: Analog Devices AXI TDD Core
> > +
> > +maintainers:
> > + - Eliza Balas <[email protected]>
> > +
> > +description: |
> > + The TDD controller is a waveform generator capable of addressing RF
> > + applications which require Time Division Duplexing, as well as controlling
> > + other modules of general applications through its dedicated 32 channel
> > + outputs. It solves the synchronization issue when transmitting and receiving
> > + multiple frames of data through multiple buffers.
> > + The TDD IP core is part of the Analog Devices hdl reference designs and has
> > + the following features:
> > + * Up to 32 independent output channels
> > + * Start/stop time values per channel
> > + * Enable and polarity bit values per channel
> > + * 32 bit-max internal reference counter
> > + * Initial startup delay before waveform generation
> > + * Configurable frame length and number of frames per burst
> > + * 3 sources of synchronization: external, internal and software generated
> > + For more information see the wiki:
> > + https://wiki.analog.com/resources/fpga/docs/axi_tdd
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - adi,axi-tdd
>
> I don't understand where the version number went. Now my question is is
> there only one version of this (ever). It's not specific enough unless
> there's a version register that can be relied on.
>
> This patch needs to answer any questions raised in previous versions.
> Assume the reviewers don't remember your patch and will ask the same
> questions again otherwise.
>
> Rob
This is the only TDD driver and I use the information from
the version register to determine the version.
That is why I had to remove the version number from
the compatible string.
Thank you,
Eliza