This series add base description of UART, TLMM, RPMHCC, GCC and RPMh PD
nodes which helps SM4450 boot to shell with console on boards with this
SoC.
Signed-off-by: Tengfei Fan <[email protected]>
---
"[PATCH v4 0/2] pinctl: qcom: Add SM4450 pinctrl driver"
https://lore.kernel.org/linux-arm-msm/[email protected]/
"[PATCH 0/2] pinctrl: qcom: fix some sm4450 pinctrl issue"
https://lore.kernel.org/linux-arm-msm/[email protected]/
v6 -> v7:
- drop reserve gpio 136, pinctrl driver issue cause gpio 136
accessed issue
v5 -> v6:
- remove link that depend on clock patch from cover letter
- remove patch which already mainline
v4 -> v5:
- separate reserved gpios setting from enable UART console patch
v3 -> v4:
- adjustment the sequence of property and property-names
- update 0 to 0x0 for reg params
- remove unrelated change
- separate SoC change and board change
v2 -> v3:
- fix dtbs_check warning
- remove interconnect, iommu, scm and tcsr related code
- rearrangement dt node
- remove smmu, scm and tcsr related documentation update
- enable CONFIG_SM_GCC_4450 in defconfig related patch
v1 -> v2:
- setting "qcom,rpmh-rsc" compatible to the first property
- keep order by unit address
- move tlmm node into soc node
- update arm,smmu.yaml
- add enable pinctrl and interconnect defconfig patches
- remove blank line
- redo dtbs_check check
previous discussion here:
[1] v6: https://lore.kernel.org/linux-arm-msm/[email protected]
[1] v5: https://lore.kernel.org/linux-arm-msm/[email protected]
[2] v4: https://lore.kernel.org/linux-arm-msm/[email protected]
[3] v3: https://lore.kernel.org/linux-arm-msm/[email protected]
[4] v2: https://lore.kernel.org/linux-arm-msm/[email protected]
[4] v1: https://lore.kernel.org/linux-arm-msm/[email protected]
Ajit Pandey (1):
arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node
Tengfei Fan (5):
arm64: dts: qcom: sm4450: Add RPMH and Global clock
arm64: dts: qcom: add uart console support for SM4450
arm64: dts: qcom: sm4450-qrd: add QRD4450 uart support
arm64: dts: qcom: sm4450-qrd: mark QRD4450 reserved gpios
arm64: defconfig: enable clock controller and pinctrl
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 18 +++-
arch/arm64/boot/dts/qcom/sm4450.dtsi | 107 ++++++++++++++++++++++++
arch/arm64/configs/defconfig | 2 +
3 files changed, 125 insertions(+), 2 deletions(-)
base-commit: 1f5c003694fab4b1ba6cbdcc417488b975c088d0
--
2.17.1
From: Ajit Pandey <[email protected]>
Add apps_rsc node and cmd_db memory region for sm4450.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Ajit Pandey <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 35 ++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index c4e5b33f5169..5e09880f4218 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
@@ -328,6 +329,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: cmd-db@80860000 {
+ compatible = "qcom,cmd-db";
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ no-map;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -419,6 +432,28 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@17a00000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ label = "apps_rsc";
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 0>;
+ power-domains = <&CLUSTER_PD>;
+
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+ };
+
};
timer {
--
2.17.1
Add base description of UART and TLMM nodes which helps SM4450
boot to shell with console on boards with this SoC.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 5a8a54b0f6c1..3e7ae3bebbe0 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -364,6 +364,29 @@
<0>;
};
+ qupv3_id_0: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x00ac0000 0x0 0x2000>;
+ ranges;
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ uart7: serial@a88000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x00a88000 0x0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -380,6 +403,32 @@
interrupt-controller;
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm4450-tlmm";
+ reg = <0x0 0x0f100000 0x0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 137>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_rx: qup-uart7-rx-state {
+ pins = "gpio23";
+ function = "qup1_se2_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart7_tx: qup-uart7-tx-state {
+ pins = "gpio22";
+ function = "qup1_se2_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
intc: interrupt-controller@17200000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
--
2.17.1
Add device node for RPMH and Global clock controller on Qualcomm
SM4450 platform.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Ajit Pandey <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 5e09880f4218..5a8a54b0f6c1 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm4450-gcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -348,6 +350,20 @@
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
+ gcc: clock-controller@100000 {
+ compatible = "qcom,sm4450-gcc";
+ reg = <0x0 0x00100000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>,
+ <0>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -452,6 +468,13 @@
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm4450-rpmh-clk";
+ #clock-cells = <1>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ };
};
};
--
2.17.1
Add uart support for QRD4450 for enable uart console.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
index 00a1c81ca397..bb8c58fb4267 100644
--- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
@@ -10,9 +10,19 @@
model = "Qualcomm Technologies, Inc. SM4450 QRD";
compatible = "qcom,sm4450-qrd", "qcom,sm4450";
- aliases { };
+ aliases {
+ serial0 = &uart7;
+ };
chosen {
- bootargs = "console=hvc0";
+ stdout-path = "serial0:115200n8";
};
};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
--
2.17.1
Some gpios are reserved for other subsystems, so mark these reserved
gpios.
Suggested-by: Can Guo <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/boot/dts/qcom/sm4450-qrd.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
index bb8c58fb4267..866e93783590 100644
--- a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts
@@ -23,6 +23,10 @@
status = "okay";
};
+&tlmm {
+ gpio-reserved-ranges = <0 4>; /* NFC eSE SPI */
+};
+
&uart7 {
status = "okay";
};
--
2.17.1
Enable global clock controller and pinctrl for support the Qualcomm
SM4450 platform to boot to UART console.
The serial engine depends on some global clock controller and pinctrl, but
as the serial console driver is only available as built-in, so the global
clock controller and pinctrl also needs be built-in for the UART device to
probe and register the console.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Tengfei Fan <[email protected]>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5ad2b841aafc..a8cf31b62e19 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -599,6 +599,7 @@ CONFIG_PINCTRL_SC8280XP=y
CONFIG_PINCTRL_SDM660=y
CONFIG_PINCTRL_SDM670=y
CONFIG_PINCTRL_SDM845=y
+CONFIG_PINCTRL_SM4450=y
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6115_LPASS_LPI=m
CONFIG_PINCTRL_SM6125=y
@@ -1258,6 +1259,7 @@ CONFIG_SM_DISPCC_6115=m
CONFIG_SM_DISPCC_8250=y
CONFIG_SM_DISPCC_8450=m
CONFIG_SM_DISPCC_8550=m
+CONFIG_SM_GCC_4450=y
CONFIG_SM_GCC_6115=y
CONFIG_SM_GCC_8350=y
CONFIG_SM_GCC_8450=y
--
2.17.1
On Wed, 29 Nov 2023 18:33:19 +0800, Tengfei Fan wrote:
> This series add base description of UART, TLMM, RPMHCC, GCC and RPMh PD
> nodes which helps SM4450 boot to shell with console on boards with this
> SoC.
>
>
Applied, thanks!
[1/6] arm64: dts: qcom: sm4450: Add apps_rsc and cmd_db node
commit: 924645058d31bde9788d6b493adefc6f113b3272
[2/6] arm64: dts: qcom: sm4450: Add RPMH and Global clock
commit: 483fa5552d352f3bfe835a3156e6cf037c4cf77f
[3/6] arm64: dts: qcom: add uart console support for SM4450
commit: 980679261b061da92fc441fa4e2fdb7ef8baadb2
[4/6] arm64: dts: qcom: sm4450-qrd: add QRD4450 uart support
commit: b6fbe1112e40109b8a0013d19b2d97f01438482d
[5/6] arm64: dts: qcom: sm4450-qrd: mark QRD4450 reserved gpios
commit: 6e28e70f00756275151ffb02534c6d2318229416
Best regards,
--
Bjorn Andersson <[email protected]>
On Wed, 29 Nov 2023 18:33:19 +0800, Tengfei Fan wrote:
> This series add base description of UART, TLMM, RPMHCC, GCC and RPMh PD
> nodes which helps SM4450 boot to shell with console on boards with this
> SoC.
>
>
Applied, thanks!
[6/6] arm64: defconfig: enable clock controller and pinctrl
commit: cdd97e07e5fa6babc8f620951efa517a1e29d6e2
Best regards,
--
Bjorn Andersson <[email protected]>