The device tree clock structure for the mipi_dsi is
unnecessarily redundant.
The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
already IMX8MM_CLK_24M, so there is no need to set the
parent-child relationship between them. The default clock
rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
already defined to be 266MHz and 24MHz respectively,
so there is no need to define those clock rates.
On i.MX8M[MNP] the samsung,pll-clock-frequency is not
necessary, because the driver will read it from sclk_mipi
which is also already set to 24MHz making it also
redundant.
Signed-off-by: Adam Ford <[email protected]>
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 738024baaa57..8d872568231d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1151,12 +1151,8 @@ mipi_dsi: dsi@32e10000 {
clocks = <&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>;
clock-names = "bus_clk", "sclk_mipi";
- assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
- <&clk IMX8MM_CLK_DSI_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
- <&clk IMX8MM_CLK_24M>;
- assigned-clock-rates = <266000000>, <24000000>;
- samsung,pll-clock-frequency = <24000000>;
+ assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
status = "disabled";
--
2.40.1
There are two clock-rate assignments for video_pll1, and the
only one it should really have belongs inside the lcdif node,
since it's the only consumer of this clock. Remove it from
the clk node.
Signed-off-by: Adam Ford <[email protected]>
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 8d872568231d..a3dae114c20e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -647,7 +647,6 @@ clk: clock-controller@30380000 {
<&clk IMX8MM_CLK_AUDIO_AHB>,
<&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MM_SYS_PLL3>,
- <&clk IMX8MM_VIDEO_PLL1>,
<&clk IMX8MM_AUDIO_PLL1>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
<&clk IMX8MM_ARM_PLL_OUT>,
@@ -657,7 +656,6 @@ clk: clock-controller@30380000 {
<400000000>,
<400000000>,
<750000000>,
- <594000000>,
<393216000>;
};
--
2.40.1
Since commit 8208181fe536 ("clk: imx: composite-8m:
Add imx8m_divider_determine_rate") the lcdif controller has
had the ability to set the lcdif_pixel rate which propagates
up the tree and sets the video_pll1 rate automatically.
By setting this value low, it will force the recalculation of
video_pll1 to the lowest rate needed by lcdif instead of
dividing a larger clock down to the desired clock speed. This
has the advantage of being able to lower the video_pll1 rate
from 594MHz to 148.5MHz when operating at 1080p. It can go even
lower when operating at lower resolutions and refresh rates.
Signed-off-by: Adam Ford <[email protected]>
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index a3dae114c20e..669fdd2c54e4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 {
assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
<&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
- assigned-clock-rates = <594000000>, <500000000>, <200000000>;
+ assigned-clock-rates = <24000000>, <500000000>, <200000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
status = "disabled";
--
2.40.1
On 28.11.23 05:54, Adam Ford wrote:
> The device tree clock structure for the mipi_dsi is
> unnecessarily redundant.
>
> The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
> already IMX8MM_CLK_24M, so there is no need to set the
> parent-child relationship between them. The default clock
> rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
> already defined to be 266MHz and 24MHz respectively,
> so there is no need to define those clock rates.
>
> On i.MX8M[MNP] the samsung,pll-clock-frequency is not
> necessary, because the driver will read it from sclk_mipi
> which is also already set to 24MHz making it also
> redundant.
>
> Signed-off-by: Adam Ford <[email protected]>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 738024baaa57..8d872568231d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1151,12 +1151,8 @@ mipi_dsi: dsi@32e10000 {
> clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> <&clk IMX8MM_CLK_DSI_PHY_REF>;
> clock-names = "bus_clk", "sclk_mipi";
> - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
> - <&clk IMX8MM_CLK_DSI_PHY_REF>;
> - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
> - <&clk IMX8MM_CLK_24M>;
> - assigned-clock-rates = <266000000>, <24000000>;
> - samsung,pll-clock-frequency = <24000000>;
> + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
> + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
> status = "disabled";
Thanks for the cleanup!
Reviewed-by: Frieder Schrempf <[email protected]>
Tested-by: Frieder Schrempf <[email protected]> # Kontron BL
i.MX8MM
On 28.11.23 05:54, Adam Ford wrote:
> There are two clock-rate assignments for video_pll1, and the
> only one it should really have belongs inside the lcdif node,
> since it's the only consumer of this clock. Remove it from
> the clk node.
>
> Signed-off-by: Adam Ford <[email protected]>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 8d872568231d..a3dae114c20e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -647,7 +647,6 @@ clk: clock-controller@30380000 {
> <&clk IMX8MM_CLK_AUDIO_AHB>,
> <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
> <&clk IMX8MM_SYS_PLL3>,
> - <&clk IMX8MM_VIDEO_PLL1>,
> <&clk IMX8MM_AUDIO_PLL1>;
> assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
> <&clk IMX8MM_ARM_PLL_OUT>,
> @@ -657,7 +656,6 @@ clk: clock-controller@30380000 {
> <400000000>,
> <400000000>,
> <750000000>,
> - <594000000>,
> <393216000>;
> };
>
Thanks for the cleanup!
Reviewed-by: Frieder Schrempf <[email protected]>
Tested-by: Frieder Schrempf <[email protected]> # Kontron BL
i.MX8MM
On 28.11.23 05:54, Adam Ford wrote:
> Since commit 8208181fe536 ("clk: imx: composite-8m:
> Add imx8m_divider_determine_rate") the lcdif controller has
> had the ability to set the lcdif_pixel rate which propagates
> up the tree and sets the video_pll1 rate automatically.
>
> By setting this value low, it will force the recalculation of
> video_pll1 to the lowest rate needed by lcdif instead of
> dividing a larger clock down to the desired clock speed. This
> has the advantage of being able to lower the video_pll1 rate
> from 594MHz to 148.5MHz when operating at 1080p. It can go even
> lower when operating at lower resolutions and refresh rates.
>
> Signed-off-by: Adam Ford <[email protected]>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index a3dae114c20e..669fdd2c54e4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1131,7 +1131,7 @@ lcdif: lcdif@32e00000 {
> assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
> <&clk IMX8MM_SYS_PLL2_1000M>,
> <&clk IMX8MM_SYS_PLL1_800M>;
> - assigned-clock-rates = <594000000>, <500000000>, <200000000>;
> + assigned-clock-rates = <24000000>, <500000000>, <200000000>;
> interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
> status = "disabled";
Thanks for the cleanup!
Reviewed-by: Frieder Schrempf <[email protected]>
Tested-by: Frieder Schrempf <[email protected]> # Kontron BL
i.MX8MM
On Mon, Nov 27, 2023 at 10:54:13PM -0600, Adam Ford wrote:
> The device tree clock structure for the mipi_dsi is
> unnecessarily redundant.
>
> The default clock parent of IMX8MM_CLK_DSI_PHY_REF is
> already IMX8MM_CLK_24M, so there is no need to set the
> parent-child relationship between them. The default clock
> rates for IMX8MM_SYS_PLL1_266M and IMX8MM_CLK_24M are
> already defined to be 266MHz and 24MHz respectively,
> so there is no need to define those clock rates.
>
> On i.MX8M[MNP] the samsung,pll-clock-frequency is not
> necessary, because the driver will read it from sclk_mipi
> which is also already set to 24MHz making it also
> redundant.
>
> Signed-off-by: Adam Ford <[email protected]>
Applied all, thanks!