As IOMMUs are supported, dma-ranges is not mentioned but
additionalProperties=false, thus we have an error when adding dma-ranges.
Add dma-ranges as a possible property because this may be present.
Signed-off-by: Eugen Hristev <[email protected]>
---
.../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
index a2051b31fa29..403530de5624 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
@@ -38,6 +38,8 @@ properties:
minItems: 1
maxItems: 5
+ dma-ranges: true
+
assigned-clocks: true
assigned-clock-parents: true
--
2.34.1
The larb clock is in fact a subsys clock, so it must be prefixed by
'subsys-' to be correctly identified in the driver.
Fixes: d9e43c1e7a38 ("arm64: dts: mt8186: Add power domains controller")
Signed-off-by: Eugen Hristev <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index df0c04f2ba1d..66ead3f23336 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1061,7 +1061,7 @@ power-domain@MT8186_POWER_DOMAIN_VENC {
reg = <MT8186_POWER_DOMAIN_VENC>;
clocks = <&topckgen CLK_TOP_VENC>,
<&vencsys CLK_VENC_CKE1_VENC>;
- clock-names = "venc0", "larb";
+ clock-names = "venc0", "subsys-larb";
mediatek,infracfg = <&infracfg_ao>;
#power-domain-cells = <0>;
};
--
2.34.1
From: Kyrie Wu <[email protected]>
Add video encoder node.
Signed-off-by: Kyrie Wu <[email protected]>
Signed-off-by: Allen-KH Cheng <[email protected]>
Reviewed-by: Hsin-Yi Wang <[email protected]>
[[email protected]: minor cleanup]
Signed-off-by: Eugen Hristev <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 66ead3f23336..8535ff2b44e9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -1993,6 +1993,30 @@ larb7: smi@17010000 {
power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
};
+ venc: venc@17020000 {
+ compatible = "mediatek,mt8183-vcodec-enc";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0 0x17020000 0 0x2000>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
+ <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
+ dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
+ mediatek,scp = <&scp>;
+ clocks = <&vencsys CLK_VENC_CKE1_VENC>;
+ clock-names = "MT_CG_VENC";
+ assigned-clocks = <&topckgen CLK_TOP_VENC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
+ power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8186-camsys";
reg = <0 0x1a000000 0 0x1000>;
--
2.34.1
It is possible that mtk_vcodec_enc_pw_on fails, and in that scenario
the PM counter is not incremented, and subsequent call to
mtk_vcodec_enc_pw_off decrements the counter, leading to a PM imbalance.
Fix by bailing out of venc_if_encode in the case when mtk_vcodec_enc_pw_on
fails.
Fixes: 4e855a6efa54 ("[media] vcodec: mediatek: Add Mediatek V4L2 Video Encoder Driver")
Signed-off-by: Eugen Hristev <[email protected]>
---
.../platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.c | 4 +++-
.../platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.h | 2 +-
drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c | 5 ++++-
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.c b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.c
index a22b7dfc656e..1a2b14a3e219 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.c
@@ -58,13 +58,15 @@ int mtk_vcodec_init_enc_clk(struct mtk_vcodec_enc_dev *mtkdev)
return 0;
}
-void mtk_vcodec_enc_pw_on(struct mtk_vcodec_pm *pm)
+int mtk_vcodec_enc_pw_on(struct mtk_vcodec_pm *pm)
{
int ret;
ret = pm_runtime_resume_and_get(pm->dev);
if (ret)
dev_err(pm->dev, "pm_runtime_resume_and_get fail: %d", ret);
+
+ return ret;
}
void mtk_vcodec_enc_pw_off(struct mtk_vcodec_pm *pm)
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.h b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.h
index 157ea08ba9e3..2e28f25e36cc 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.h
+++ b/drivers/media/platform/mediatek/vcodec/encoder/mtk_vcodec_enc_pm.h
@@ -10,7 +10,7 @@
#include "mtk_vcodec_enc_drv.h"
int mtk_vcodec_init_enc_clk(struct mtk_vcodec_enc_dev *dev);
-void mtk_vcodec_enc_pw_on(struct mtk_vcodec_pm *pm);
+int mtk_vcodec_enc_pw_on(struct mtk_vcodec_pm *pm);
void mtk_vcodec_enc_pw_off(struct mtk_vcodec_pm *pm);
void mtk_vcodec_enc_clock_on(struct mtk_vcodec_pm *pm);
void mtk_vcodec_enc_clock_off(struct mtk_vcodec_pm *pm);
diff --git a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c
index c402a686f3cb..e83747b8d69a 100644
--- a/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c
+++ b/drivers/media/platform/mediatek/vcodec/encoder/venc_drv_if.c
@@ -64,7 +64,9 @@ int venc_if_encode(struct mtk_vcodec_enc_ctx *ctx,
ctx->dev->curr_ctx = ctx;
spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
- mtk_vcodec_enc_pw_on(&ctx->dev->pm);
+ ret = mtk_vcodec_enc_pw_on(&ctx->dev->pm);
+ if (ret)
+ goto venc_if_encode_pw_on_err;
mtk_vcodec_enc_clock_on(&ctx->dev->pm);
ret = ctx->enc_if->encode(ctx->drv_handle, opt, frm_buf,
bs_buf, result);
@@ -75,6 +77,7 @@ int venc_if_encode(struct mtk_vcodec_enc_ctx *ctx,
ctx->dev->curr_ctx = NULL;
spin_unlock_irqrestore(&ctx->dev->irqlock, flags);
+venc_if_encode_pw_on_err:
mtk_venc_unlock(ctx);
return ret;
}
--
2.34.1
Il 13/12/23 13:20, Eugen Hristev ha scritto:
> From: Kyrie Wu <[email protected]>
>
> Add video encoder node.
>
> Signed-off-by: Kyrie Wu <[email protected]>
> Signed-off-by: Allen-KH Cheng <[email protected]>
> Reviewed-by: Hsin-Yi Wang <[email protected]>
> [[email protected]: minor cleanup]
> Signed-off-by: Eugen Hristev <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index 66ead3f23336..8535ff2b44e9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -1993,6 +1993,30 @@ larb7: smi@17010000 {
> power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
> };
>
> + venc: venc@17020000 {
> + compatible = "mediatek,mt8183-vcodec-enc";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0 0x17020000 0 0x2000>;
> + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
> + dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
> + mediatek,scp = <&scp>;
> + clocks = <&vencsys CLK_VENC_CKE1_VENC>;
> + clock-names = "MT_CG_VENC";
clock-names = "venc"; (please no underscores and please lower case)
> + assigned-clocks = <&topckgen CLK_TOP_VENC>;
> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
> + };
....also:
The following order of properties in device nodes is preferred:
1. "compatible"
2. "reg"
3. "ranges"
4. Standard/common properties (defined by common bindings, e.g. without
vendor-prefixes)
5. Vendor-specific properties
6. "status" (if applicable)
7. Child nodes, where each node is preceded with a blank line
Documentation/devicetree/bindings/dts-coding-style.rst
Please reorder as per the DTS coding style document, and also please rename the
venc node to use a generic name, such as "video-encoder@xxxx"
Cheers,
Angelo
Il 13/12/23 13:20, Eugen Hristev ha scritto:
> It is possible that mtk_vcodec_enc_pw_on fails, and in that scenario
> the PM counter is not incremented, and subsequent call to
> mtk_vcodec_enc_pw_off decrements the counter, leading to a PM imbalance.
> Fix by bailing out of venc_if_encode in the case when mtk_vcodec_enc_pw_on
> fails.
>
> Fixes: 4e855a6efa54 ("[media] vcodec: mediatek: Add Mediatek V4L2 Video Encoder Driver")
> Signed-off-by: Eugen Hristev <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregnoòcollabora.com>
Il 14/12/23 11:44, AngeloGioacchino Del Regno ha scritto:
> Il 13/12/23 13:20, Eugen Hristev ha scritto:
>> From: Kyrie Wu <[email protected]>
>>
>> Add video encoder node.
>>
>> Signed-off-by: Kyrie Wu <[email protected]>
>> Signed-off-by: Allen-KH Cheng <[email protected]>
>> Reviewed-by: Hsin-Yi Wang <[email protected]>
>> [[email protected]: minor cleanup]
>> Signed-off-by: Eugen Hristev <[email protected]>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 24 ++++++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> index 66ead3f23336..8535ff2b44e9 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> @@ -1993,6 +1993,30 @@ larb7: smi@17010000 {
>> power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
>> };
>> + venc: venc@17020000 {
>> + compatible = "mediatek,mt8183-vcodec-enc";
Sorry for the double email;
I've just noticed: where's mediatek,mt8186-vcodec-enc? :-)
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + reg = <0 0x17020000 0 0x2000>;
>> + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
>> + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
>> + dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
>> + mediatek,scp = <&scp>;
>> + clocks = <&vencsys CLK_VENC_CKE1_VENC>;
>> + clock-names = "MT_CG_VENC";
>
> clock-names = "venc"; (please no underscores and please lower case)
>
>> + assigned-clocks = <&topckgen CLK_TOP_VENC>;
>> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
>> + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
>> + };
>
>
> ....also:
>
> The following order of properties in device nodes is preferred:
>
> 1. "compatible"
> 2. "reg"
> 3. "ranges"
> 4. Standard/common properties (defined by common bindings, e.g. without
> vendor-prefixes)
> 5. Vendor-specific properties
> 6. "status" (if applicable)
> 7. Child nodes, where each node is preceded with a blank line
>
> Documentation/devicetree/bindings/dts-coding-style.rst
>
> Please reorder as per the DTS coding style document, and also please rename the
> venc node to use a generic name, such as "video-encoder@xxxx"
>
> Cheers,
> Angelo
On 12/14/23 12:50, AngeloGioacchino Del Regno wrote:
> Il 14/12/23 11:44, AngeloGioacchino Del Regno ha scritto:
>> Il 13/12/23 13:20, Eugen Hristev ha scritto:
>>> From: Kyrie Wu <[email protected]>
>>>
>>> Add video encoder node.
>>>
>>> Signed-off-by: Kyrie Wu <[email protected]>
>>> Signed-off-by: Allen-KH Cheng <[email protected]>
>>> Reviewed-by: Hsin-Yi Wang <[email protected]>
>>> [[email protected]: minor cleanup]
>>> Signed-off-by: Eugen Hristev <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 24 ++++++++++++++++++++++++
>>> 1 file changed, 24 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> index 66ead3f23336..8535ff2b44e9 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>>> @@ -1993,6 +1993,30 @@ larb7: smi@17010000 {
>>> power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
>>> };
>>> + venc: venc@17020000 {
>>> + compatible = "mediatek,mt8183-vcodec-enc";
>
> Sorry for the double email;
>
> I've just noticed: where's mediatek,mt8186-vcodec-enc? :-)
Hi,
There is none.
This just works exactly as mt8183, thus reusing the same compatible.
Do you want a new dedicated mt8186 compatible as well for the situation *just in
case* some specific difference showing up later ?
Eugen
>
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + reg = <0 0x17020000 0 0x2000>;
>>> + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
>>> + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
>>> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
>>> + dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
>>> + mediatek,scp = <&scp>;
>>> + clocks = <&vencsys CLK_VENC_CKE1_VENC>;
>>> + clock-names = "MT_CG_VENC";
>>
>> clock-names = "venc"; (please no underscores and please lower case)
>>
>>> + assigned-clocks = <&topckgen CLK_TOP_VENC>;
>>> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
>>> + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
>>> + };
>>
>>
>> ....also:
>>
>> The following order of properties in device nodes is preferred:
>>
>> 1. "compatible"
>> 2. "reg"
>> 3. "ranges"
>> 4. Standard/common properties (defined by common bindings, e.g. without
>> vendor-prefixes)
>> 5. Vendor-specific properties
>> 6. "status" (if applicable)
>> 7. Child nodes, where each node is preceded with a blank line
>>
>> Documentation/devicetree/bindings/dts-coding-style.rst
>>
>> Please reorder as per the DTS coding style document, and also please rename the
>> venc node to use a generic name, such as "video-encoder@xxxx"
>>
>> Cheers,
>> Angelo
>
>
> _______________________________________________
> Kernel mailing list -- [email protected]
> To unsubscribe send an email to [email protected]
On 12/14/23 12:44, AngeloGioacchino Del Regno wrote:
> Il 13/12/23 13:20, Eugen Hristev ha scritto:
>> From: Kyrie Wu <[email protected]>
>>
>> Add video encoder node.
>>
>> Signed-off-by: Kyrie Wu <[email protected]>
>> Signed-off-by: Allen-KH Cheng <[email protected]>
>> Reviewed-by: Hsin-Yi Wang <[email protected]>
>> [[email protected]: minor cleanup]
>> Signed-off-by: Eugen Hristev <[email protected]>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 24 ++++++++++++++++++++++++
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> index 66ead3f23336..8535ff2b44e9 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
>> @@ -1993,6 +1993,30 @@ larb7: smi@17010000 {
>> power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
>> };
>>
>> + venc: venc@17020000 {
>> + compatible = "mediatek,mt8183-vcodec-enc";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + reg = <0 0x17020000 0 0x2000>;
>> + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
>> + iommus = <&iommu_mm IOMMU_PORT_L7_VENC_RCPU>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_REC>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_BSDMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_SV_COMV>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_RD_COMV>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_LUMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_CUR_CHROMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_LUMA>,
>> + <&iommu_mm IOMMU_PORT_L7_VENC_REF_CHROMA>;
>> + dma-ranges = <0x1 0x0 0x1 0x0 0x1 0x0>;
>> + mediatek,scp = <&scp>;
>> + clocks = <&vencsys CLK_VENC_CKE1_VENC>;
>> + clock-names = "MT_CG_VENC";
>
> clock-names = "venc"; (please no underscores and please lower case)
The clock name must be `venc_sel` (*with* underscores) and it's ABI as defined in
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
so I will it change to that.
>
>> + assigned-clocks = <&topckgen CLK_TOP_VENC>;
>> + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3>;
>> + power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
>> + };
>
>
> ....also:
>
> The following order of properties in device nodes is preferred:
>
> 1. "compatible"
> 2. "reg"
> 3. "ranges"
> 4. Standard/common properties (defined by common bindings, e.g. without
> vendor-prefixes)
> 5. Vendor-specific properties
> 6. "status" (if applicable)
> 7. Child nodes, where each node is preceded with a blank line
>
> Documentation/devicetree/bindings/dts-coding-style.rst
>
> Please reorder as per the DTS coding style document, and also please rename the
> venc node to use a generic name, such as "video-encoder@xxxx"
>
> Cheers,
> Angelo
> _______________________________________________
> Kernel mailing list -- [email protected]
> To unsubscribe send an email to [email protected]