Add Reset Controller bindings to clock bindings for Unisoc's UMS512.
Signed-off-by: Zhifeng Tang <[email protected]>
---
Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
index 43d2b6c31357..6b0892d637fe 100644
--- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
@@ -34,6 +34,9 @@ properties:
"#clock-cells":
const: 1
+ "#reset-cells":
+ const: 1
+
clocks:
minItems: 1
maxItems: 4
--
2.17.1
On Fri, Dec 15, 2023 at 04:10:03PM +0800, Zhifeng Tang wrote:
> Add Reset Controller bindings to clock bindings for Unisoc's UMS512.
This is what the diff is doing, but there's no justification for why
this is the case. I _assume_ that the clock controller register block
also contains reset bits for some of these peripherals, but the commit
message needs to say that.
Cheers,
Conor.
>
> Signed-off-by: Zhifeng Tang <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> index 43d2b6c31357..6b0892d637fe 100644
> --- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
> @@ -34,6 +34,9 @@ properties:
> "#clock-cells":
> const: 1
>
> + "#reset-cells":
> + const: 1
> +
> clocks:
> minItems: 1
> maxItems: 4
> --
> 2.17.1
>