From: Moudy Ho <[email protected]>
Changes since v9:
- Rebase on linux-next.
- Dependent dtsi files:
Message ID = [email protected]
- Depends on:
Message ID = [email protected]
- Include the missing compatible name 'mediatek,mt8188-vdo1-rdma' in
patch [2/16].
Changes since v8:
- Rebase on linux-next.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=797543
- Depends on:
Message ID = [email protected]
- Following Rob's suggestion, the number of 'clocks' and 'mboxes' items are
restricted using the 'minItems' in [2/16] and [3/16].
- Revise the dependent mt8188 disp padding compatible name in [16/16].
Changes since v7:
- Rebase on linux-next.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=797543
- Depends on:
Message ID = [email protected]
- Correct the bindings of the four components: FG, TCC, TDSHP and HDR.
The names of the first three are expanded in the title, and
the descriptions of all four have been enhanced.
Changes since v6:
- Rebase on v6.6-rc5.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=792079
- Depends on:
Message ID = [email protected]
- Discard splitting RDMA's common properties and instead use 'allOf' to
isolate different platform features.
- Revise the incorrect properties in FG, HDR, STITCH, TCC and TDAP bindings.
- Adding SoC-specific compatible string to components, like WROT and RSZ,
that are inherited from MT8183.
- Fixed typos in TCC patch and enhancing its hardware description.
Changes since v5:
- Rebase on v6.6-rc2.
- Dependent dtsi files:
https://patchwork.kernel.org/project/linux-mediatek/list/?series=786511
- Depends on:
Message ID = [email protected]
- Split out common propertis for RDMA.
- Split each component into independent patches.
Changes since v4:
- Rebase on v6.6-rc1
- Organize identical hardware components into their respective files.
Hi,
The purpose of this patch is to separate the MDP3-related bindings from
the original mailing list mentioned below:
https://lore.kernel.org/all/[email protected]/
Those binding files describe additional components that
are present in the mt8195.
Moudy Ho (16):
dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with
generic names
dt-bindings: media: mediatek: mdp3: merge the indentical RDMA under
display
dt-bindings: media: mediatek: mdp3: add config for MT8195 RDMA
dt-bindings: media: mediatek: mdp3: add compatible for MT8195 RSZ
dt-bindings: media: mediatek: mdp3: add compatible for MT8195 WROT
dt-bindings: media: mediatek: mdp3: add component FG for MT8195
dt-bindings: media: mediatek: mdp3: add component HDR for MT8195
dt-bindings: media: mediatek: mdp3: add component STITCH for MT8195
dt-bindings: media: mediatek: mdp3: add component TCC for MT8195
dt-bindings: media: mediatek: mdp3: add component TDSHP for MT8195
dt-bindings: display: mediatek: aal: add compatible for MT8195
dt-bindings: display: mediatek: color: add compatible for MT8195
dt-bindings: display: mediatek: merge: add compatible for MT8195
dt-bindings: display: mediatek: ovl: add compatible for MT8195
dt-bindings: display: mediatek: split: add compatible for MT8195
dt-bindings: display: mediatek: padding: add compatible for MT8195
.../display/mediatek/mediatek,aal.yaml | 1 +
.../display/mediatek/mediatek,color.yaml | 1 +
.../display/mediatek/mediatek,mdp-rdma.yaml | 92 ------------------
.../display/mediatek/mediatek,merge.yaml | 1 +
.../display/mediatek/mediatek,ovl.yaml | 1 +
.../display/mediatek/mediatek,padding.yaml | 4 +-
.../display/mediatek/mediatek,split.yaml | 27 ++++++
.../bindings/media/mediatek,mdp3-fg.yaml | 61 ++++++++++++
.../bindings/media/mediatek,mdp3-hdr.yaml | 61 ++++++++++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 93 ++++++++++++++++---
.../bindings/media/mediatek,mdp3-rsz.yaml | 6 +-
.../bindings/media/mediatek,mdp3-stitch.yaml | 61 ++++++++++++
.../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 ++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 29 ++++--
15 files changed, 442 insertions(+), 119 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
--
2.18.0
To simplify maintenance and avoid branches, the identical component
should be merged and placed in the path belonging to the MDP
(from display/* to media/*).
In addition, currently only MDP utilizes RDMA through CMDQ, and the
necessary properties for "mediatek,gce-events", and "mboxes" have been
set up for this purpose.
Within DISP, it directly receives component interrupt signals.
Signed-off-by: Moudy Ho <[email protected]>
---
.../display/mediatek/mediatek,mdp-rdma.yaml | 92 -------------------
.../bindings/media/mediatek,mdp3-rdma.yaml | 43 ++++++++-
2 files changed, 40 insertions(+), 95 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
deleted file mode 100644
index 7570a0684967..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
+++ /dev/null
@@ -1,92 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek MDP RDMA
-
-maintainers:
- - Chun-Kuang Hu <[email protected]>
- - Philipp Zabel <[email protected]>
-
-description:
- The MediaTek MDP RDMA stands for Read Direct Memory Access.
- It provides real time data to the back-end panel driver, such as DSI,
- DPI and DP_INTF.
- It contains one line buffer to store the sufficient pixel data.
- RDMA device node must be siblings to the central MMSYS_CONFIG node.
- For a description of the MMSYS_CONFIG binding, see
- Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
-
-properties:
- compatible:
- oneOf:
- - const: mediatek,mt8195-vdo1-rdma
- - items:
- - const: mediatek,mt8188-vdo1-rdma
- - const: mediatek,mt8195-vdo1-rdma
-
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- power-domains:
- maxItems: 1
-
- clocks:
- items:
- - description: RDMA Clock
-
- iommus:
- maxItems: 1
-
- mediatek,gce-client-reg:
- description:
- The register of display function block to be set by gce. There are 4 arguments,
- such as gce node, subsys id, offset and register size. The subsys id that is
- mapping to the register of display function blocks is defined in the gce header
- include/dt-bindings/gce/<chip>-gce.h of each chips.
- $ref: /schemas/types.yaml#/definitions/phandle-array
- items:
- items:
- - description: phandle of GCE
- - description: GCE subsys id
- - description: register offset
- - description: register size
- maxItems: 1
-
-required:
- - compatible
- - reg
- - power-domains
- - clocks
- - iommus
- - mediatek,gce-client-reg
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt8195-clk.h>
- #include <dt-bindings/power/mt8195-power.h>
- #include <dt-bindings/gce/mt8195-gce.h>
- #include <dt-bindings/memory/mt8195-memory-port.h>
-
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
-
- rdma@1c104000 {
- compatible = "mediatek,mt8195-vdo1-rdma";
- reg = <0 0x1c104000 0 0x1000>;
- interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
- power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
- iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
- mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
- };
- };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index e1ffe7eb2cdf..e9955639ce19 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -20,8 +20,12 @@ description: |
properties:
compatible:
- items:
+ oneOf:
- const: mediatek,mt8183-mdp3-rdma
+ - const: mediatek,mt8195-vdo1-rdma
+ - items:
+ - const: mediatek,mt8188-vdo1-rdma
+ - const: mediatek,mt8195-vdo1-rdma
reg:
maxItems: 1
@@ -60,6 +64,7 @@ properties:
items:
- description: RDMA clock
- description: RSZ clock
+ minItems: 1
iommus:
maxItems: 1
@@ -68,6 +73,10 @@ properties:
items:
- description: used for 1st data pipe from RDMA
- description: used for 2nd data pipe from RDMA
+ minItems: 1
+
+ interrupts:
+ maxItems: 1
'#dma-cells':
const: 1
@@ -76,13 +85,41 @@ required:
- compatible
- reg
- mediatek,gce-client-reg
- - mediatek,gce-events
- power-domains
- clocks
- iommus
- - mboxes
- '#dma-cells'
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8183-mdp3-rdma
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+
+ mboxes:
+ minItems: 2
+
+ required:
+ - mboxes
+ - mediatek,gce-events
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-vdo1-rdma
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.18.0
Add the fundamental hardware configuration of component TDSHP,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
new file mode 100644
index 000000000000..8ab7f2d8e148
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 Two-Dimensional Sharpness
+
+maintainers:
+ - Matthias Brugger <[email protected]>
+ - Moudy Ho <[email protected]>
+
+description:
+ Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component
+ used to perform image edge sharpening and enhance vividness and contrast.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-tdshp
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ reg = <0x14007000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
--
2.18.0
Add compatible string and GCE property for MT8195 SPLIT, of
which is operated by MDP3.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../display/mediatek/mediatek,split.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
index a8a5c9608598..e4affc854f3d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -23,6 +23,7 @@ properties:
oneOf:
- enum:
- mediatek,mt8173-disp-split
+ - mediatek,mt8195-mdp3-split
- items:
- const: mediatek,mt6795-disp-split
- const: mediatek,mt8173-disp-split
@@ -38,6 +39,21 @@ properties:
the power controller specified by phandle. See
Documentation/devicetree/bindings/power/power-domain.yaml for details.
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
clocks:
items:
- description: SPLIT Clock
@@ -48,6 +64,17 @@ required:
- power-domains
- clocks
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-mdp3-split
+
+ then:
+ required:
+ - mediatek,gce-client-reg
+
additionalProperties: false
examples:
--
2.18.0
Added the configuration for MT8195 RDMA. In comparison to MT8183, it
no longer shares SRAM with RSZ, and there are now preconfigured 5 mbox.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/media/mediatek,mdp3-rdma.yaml | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index e9955639ce19..f9ca66413d51 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -22,6 +22,7 @@ properties:
compatible:
oneOf:
- const: mediatek,mt8183-mdp3-rdma
+ - const: mediatek,mt8195-mdp3-rdma
- const: mediatek,mt8195-vdo1-rdma
- items:
- const: mediatek,mt8188-vdo1-rdma
@@ -73,6 +74,9 @@ properties:
items:
- description: used for 1st data pipe from RDMA
- description: used for 2nd data pipe from RDMA
+ - description: used for 3rd data pipe from RDMA
+ - description: used for 4th data pipe from RDMA
+ - description: used for the data pipe from SPLIT
minItems: 1
interrupts:
@@ -109,6 +113,23 @@ allOf:
- mboxes
- mediatek,gce-events
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-mdp3-rdma
+
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+
+ mboxes:
+ minItems: 5
+
+ required:
+ - mediatek,gce-events
+
- if:
properties:
compatible:
--
2.18.0
Add the fundamental hardware configuration of component STITCH,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
---
.../bindings/media/mediatek,mdp3-stitch.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
new file mode 100644
index 000000000000..d815bea29154
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 STITCH
+
+maintainers:
+ - Matthias Brugger <[email protected]>
+ - Moudy Ho <[email protected]>
+
+description:
+ One of Media Data Path 3 (MDP3) components used to combine multiple video frame
+ with overlapping fields of view to produce a segmented panorame.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-stitch
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
--
2.18.0
Add the fundamental hardware configuration of component TCC,
which is controlled by MDP3 on MT8195.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
new file mode 100644
index 000000000000..14ea556d4f82
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Media Data Path 3 Tone Curve Conversion
+
+maintainers:
+ - Matthias Brugger <[email protected]>
+
+description:
+ Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components.
+ It is used to handle the tone mapping of various gamma curves in order to
+ achieve HDR10 effects. This helps adapt the content to the color and
+ brightness range that standard display devices typically support.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-mdp3-tcc
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ description:
+ The register of display function block to be set by gce. There are 4 arguments,
+ such as gce node, subsys id, offset and register size. The subsys id that is
+ mapping to the register of display function blocks is defined in the gce header
+ include/dt-bindings/gce/<chip>-gce.h of each chips.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: phandle of GCE
+ - description: GCE subsys id
+ - description: register offset
+ - description: register size
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ display@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ reg = <0x1400b000 0x1000>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
--
2.18.0
MT8195 WROT inherited from MT8183, add the corresponding
compatible name to it.
Signed-off-by: Moudy Ho <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
.../devicetree/bindings/media/mediatek,mdp3-wrot.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
index 64ea98aa0592..53a679338402 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -15,9 +15,13 @@ description: |
properties:
compatible:
- items:
+ oneOf:
- enum:
- mediatek,mt8183-mdp3-wrot
+ - items:
+ - enum:
+ - mediatek,mt8195-mdp3-wrot
+ - const: mediatek,mt8183-mdp3-wrot
reg:
maxItems: 1
--
2.18.0
On 20/12/2023 11:08, Moudy Ho wrote:
> To simplify maintenance and avoid branches, the identical component
> should be merged and placed in the path belonging to the MDP
> (from display/* to media/*).
Combining bindings into one bigger meta-binding makes it usually more
difficult to maintain and review.
>
> In addition, currently only MDP utilizes RDMA through CMDQ, and the
> necessary properties for "mediatek,gce-events", and "mboxes" have been
> set up for this purpose.
> Within DISP, it directly receives component interrupt signals.
>
> Signed-off-by: Moudy Ho <[email protected]>
> ---
> .../display/mediatek/mediatek,mdp-rdma.yaml | 92 -------------------
> .../bindings/media/mediatek,mdp3-rdma.yaml | 43 ++++++++-
> 2 files changed, 40 insertions(+), 95 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> deleted file mode 100644
> index 7570a0684967..000000000000
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml
> +++ /dev/null
> @@ -1,92 +0,0 @@
> -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> -%YAML 1.2
> ----
> -$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml#
> -$schema: http://devicetree.org/meta-schemas/core.yaml#
> -
> -title: MediaTek MDP RDMA
> -
> -maintainers:
> - - Chun-Kuang Hu <[email protected]>
> - - Philipp Zabel <[email protected]>
> -
> -description:
> - The MediaTek MDP RDMA stands for Read Direct Memory Access.
> - It provides real time data to the back-end panel driver, such as DSI,
> - DPI and DP_INTF.
> - It contains one line buffer to store the sufficient pixel data.
> - RDMA device node must be siblings to the central MMSYS_CONFIG node.
> - For a description of the MMSYS_CONFIG binding, see
> - Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
> -
> -properties:
> - compatible:
> - oneOf:
> - - const: mediatek,mt8195-vdo1-rdma
> - - items:
> - - const: mediatek,mt8188-vdo1-rdma
> - - const: mediatek,mt8195-vdo1-rdma
> -
> - reg:
> - maxItems: 1
> -
> - interrupts:
> - maxItems: 1
> -
> - power-domains:
> - maxItems: 1
> -
> - clocks:
> - items:
> - - description: RDMA Clock
> -
> - iommus:
> - maxItems: 1
> -
> - mediatek,gce-client-reg:
> - description:
> - The register of display function block to be set by gce. There are 4 arguments,
> - such as gce node, subsys id, offset and register size. The subsys id that is
> - mapping to the register of display function blocks is defined in the gce header
> - include/dt-bindings/gce/<chip>-gce.h of each chips.
> - $ref: /schemas/types.yaml#/definitions/phandle-array
> - items:
> - items:
> - - description: phandle of GCE
> - - description: GCE subsys id
> - - description: register offset
> - - description: register size
> - maxItems: 1
> -
> -required:
> - - compatible
> - - reg
> - - power-domains
> - - clocks
> - - iommus
> - - mediatek,gce-client-reg
> -
> -additionalProperties: false
> -
> -examples:
> - - |
> - #include <dt-bindings/interrupt-controller/arm-gic.h>
> - #include <dt-bindings/clock/mt8195-clk.h>
> - #include <dt-bindings/power/mt8195-power.h>
> - #include <dt-bindings/gce/mt8195-gce.h>
> - #include <dt-bindings/memory/mt8195-memory-port.h>
> -
> - soc {
> - #address-cells = <2>;
> - #size-cells = <2>;
> -
> - rdma@1c104000 {
> - compatible = "mediatek,mt8195-vdo1-rdma";
> - reg = <0 0x1c104000 0 0x1000>;
> - interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>;
> - power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> - iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> - mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> index e1ffe7eb2cdf..e9955639ce19 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> @@ -20,8 +20,12 @@ description: |
>
> properties:
> compatible:
> - items:
> + oneOf:
> - const: mediatek,mt8183-mdp3-rdma
> + - const: mediatek,mt8195-vdo1-rdma
> + - items:
> + - const: mediatek,mt8188-vdo1-rdma
> + - const: mediatek,mt8195-vdo1-rdma
>
> reg:
> maxItems: 1
> @@ -60,6 +64,7 @@ properties:
> items:
> - description: RDMA clock
> - description: RSZ clock
> + minItems: 1
>
> iommus:
> maxItems: 1
> @@ -68,6 +73,10 @@ properties:
> items:
> - description: used for 1st data pipe from RDMA
> - description: used for 2nd data pipe from RDMA
> + minItems: 1
> +
> + interrupts:
> + maxItems: 1
Why existing devices now support interrupts?
>
> '#dma-cells':
> const: 1
> @@ -76,13 +85,41 @@ required:
> - compatible
> - reg
> - mediatek,gce-client-reg
> - - mediatek,gce-events
> - power-domains
> - clocks
> - iommus
> - - mboxes
> - '#dma-cells'
I see little value in this commit, considering that next month you will
want to split it because it will grow unmaintainable.
Best regards,
Krzysztof
On Thu, Dec 21, 2023 at 10:28:52AM +0100, Krzysztof Kozlowski wrote:
> On 20/12/2023 11:08, Moudy Ho wrote:
> > To simplify maintenance and avoid branches, the identical component
> > should be merged and placed in the path belonging to the MDP
> > (from display/* to media/*).
>
> Combining bindings into one bigger meta-binding makes it usually more
> difficult to maintain and review.
Yeah, but these mediatek blocks appear to be used for both display and
video codec pipelines. So having different bindings was probably wrong
to start with.
Rob