The apq8064 rework to use cacheinfo takes more than expected, so I've
spanwed this series. It is an excerpt of the APQ8064 cpufreq series
[1], so it it continues the version numbering for those patches.
The Subsystem Power Manager (SPM) / SPM AutoVoltageScaling Wrapper2
(SAW2) are hardware blocks used on some of Qualcomm platforms to handle
the voltage rails. It does this by bypassing RPM and directly
interfacing the PMIC. Extend current SPM driver to export this
regulator.
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
Changes since v6:
- Added SoC-specific compat strings on MSM8960, IPQ4019, IPQ8064
platforms (Luca)
- Fixed saw2 node names on few remaining platforms.
Changes since v5:
- Added patch that moves SPM structs out of the header file
- Removed support for L2 SAW regulator (Stephan Gerhold).
msm8960/apq8064 do not use this SAW2 to manage this regulator and
other platforms will need changes anyway.
---
Dmitry Baryshkov (22):
dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings
dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
soc: qcom: spm: remove driver-internal structures from the driver API
soc: qcom: spm: add support for voltage regulator
ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit
ARM: dts: qcom: msm8974: use new compat string for L2 SAW2 unit
ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices
ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices
ARM: dts: qcom: ipq8064: use SoC-specific compatibles for SAW2 devices
ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
ARM: dts: qcom: apq8084: rename SAW nodes to power-manager
ARM: dts: qcom: msm8960: rename SAW nodes to power-manager
ARM: dts: qcom: msm8974: rename SAW nodes to power-manager
ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager
ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager
ARM: dts: qcom: apq8064: declare SAW2 regulators
ARM: dts: qcom: msm8960: declare SAW2 regulators
ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device
ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device
ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices
ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices
.../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 -----
.../soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 45 +++-
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 32 ++-
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 13 +-
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 25 +-
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 10 +-
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 20 +-
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 13 +-
drivers/soc/qcom/spm.c | 254 ++++++++++++++++++++-
include/soc/qcom/spm.h | 23 +-
10 files changed, 353 insertions(+), 140 deletions(-)
---
base-commit: 39676dfe52331dba909c617f213fdb21015c8d10
change-id: 20240101-saw2-spm-regulator-af0f81c15cdc
Best regards,
--
Dmitry Baryshkov <[email protected]>
Define compatible strings for SAW2 units present on MSM8960, IPQ4019
and IPQ8064. There is no need to include SAW version into the compat
string, so just use the SoC and SAW2 kind.
Also add missing L2 SAW2 compatibles for MSM8974 and APQ8084, they
follow the existing CPU SAW2 strings.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index 84b3f01d590c..2178fea37b8c 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -25,6 +25,9 @@ properties:
compatible:
items:
- enum:
+ - qcom,ipq4019-saw2-cpu
+ - qcom,ipq4019-saw2-l2
+ - qcom,ipq8064-saw2-cpu
- qcom,sdm660-gold-saw2-v4.1-l2
- qcom,sdm660-silver-saw2-v4.1-l2
- qcom,msm8998-gold-saw2-v4.1-l2
@@ -33,10 +36,13 @@ properties:
- qcom,msm8916-saw2-v3.0-cpu
- qcom,msm8939-saw2-v3.0-cpu
- qcom,msm8226-saw2-v2.1-cpu
+ - qcom,msm8960-saw2-cpu
- qcom,msm8974-saw2-v2.1-cpu
+ - qcom,msm8974-saw2-v2.1-l2
- qcom,msm8976-gold-saw2-v2.3-l2
- qcom,msm8976-silver-saw2-v2.3-l2
- qcom,apq8084-saw2-v2.1-cpu
+ - qcom,apq8084-saw2-v2.1-l2
- qcom,apq8064-saw2-v1.1-cpu
- const: qcom,saw2
--
2.39.2
The SAW2 device can optionally provide a voltage regulator supplying the
CPU core, cluster or L2 cache. Change the boolean 'regulator' property
into a proper regulator description. This breaks schema compatibility
for the sake of properly describing the regulator.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index 2178fea37b8c..f9306f2a6e99 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -53,7 +53,7 @@ properties:
minItems: 1
regulator:
- type: boolean
+ $ref: /schemas/regulator/regulator.yaml#
description: Indicates that this SPM device acts as a regulator device
device for the core (CPU or Cache) the SPM is attached to.
@@ -102,4 +102,17 @@ examples:
reg = <0x17912000 0x1000>;
};
+ - |
+ /*
+ * Example 3: SAW2 with the bundled regulator definition.
+ */
+ power-manager@2089000 {
+ compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
+ reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+
+ regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ };
...
--
2.39.2
The Qualcomm SPM / SAW2 device is described in two bindigns files:
arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into
the latter, adding detailed device node description. While we are at it,
also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual
compatible used for these devices.
The regulator property is retained as is. It will be changed in the
later patches.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
.../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ----------------------
.../soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 26 +++++++---
2 files changed, 20 insertions(+), 64 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
deleted file mode 100644
index c0e3c3a42bea..000000000000
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-SPM AVS Wrapper 2 (SAW2)
-
-The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
-Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
-power-controller that transitions a piece of hardware (like a processor or
-subsystem) into and out of low power modes via a direct connection to
-the PMIC. It can also be wired up to interact with other processors in the
-system, notifying them when a low power state is entered or exited.
-
-Multiple revisions of the SAW hardware are supported using these Device Nodes.
-SAW2 revisions differ in the register offset and configuration data. Also, the
-same revision of the SAW in different SoCs may have different configuration
-data due the differences in hardware capabilities. Hence the SoC name, the
-version of the SAW hardware in that SoC and the distinction between cpu (big
-or Little) or cache, may be needed to uniquely identify the SAW register
-configuration and initialization data. The compatible string is used to
-indicate this parameter.
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: Must have
- "qcom,saw2"
- A more specific value could be one of:
- "qcom,apq8064-saw2-v1.1-cpu"
- "qcom,msm8226-saw2-v2.1-cpu"
- "qcom,msm8974-saw2-v2.1-cpu"
- "qcom,apq8084-saw2-v2.1-cpu"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the first element specifies the base address and size of
- the register region. An optional second element specifies
- the base address and size of the alias register region.
-
-- regulator:
- Usage: optional
- Value type: boolean
- Definition: Indicates that this SPM device acts as a regulator device
- device for the core (CPU or Cache) the SPM is attached
- to.
-
-Example 1:
-
- power-controller@2099000 {
- compatible = "qcom,saw2";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-
-Example 2:
- saw0: power-controller@f9089000 {
- compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
- reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
- };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
similarity index 64%
rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
index 20c8cd38ff0d..84b3f01d590c 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml
@@ -1,18 +1,25 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
+$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Subsystem Power Manager
+title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
maintainers:
- Andy Gross <[email protected]>
- Bjorn Andersson <[email protected]>
description: |
- This binding describes the Qualcomm Subsystem Power Manager, used to control
- the peripheral logic surrounding the application cores in Qualcomm platforms.
+ The Qualcomm Subsystem Power Manager is used to control the peripheral logic
+ surrounding the application cores in Qualcomm platforms.
+
+ The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
+ Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
+ power-controller that transitions a piece of hardware (like a processor or
+ subsystem) into and out of low power modes via a direct connection to
+ the PMIC. It can also be wired up to interact with other processors in the
+ system, notifying them when a low power state is entered or exited.
properties:
compatible:
@@ -34,8 +41,15 @@ properties:
- const: qcom,saw2
reg:
- description: Base address and size of the SPM register region
- maxItems: 1
+ items:
+ - description: Base address and size of the SPM register region
+ - description: Base address and size of the alias register region
+ minItems: 1
+
+ regulator:
+ type: boolean
+ description: Indicates that this SPM device acts as a regulator device
+ device for the core (CPU or Cache) the SPM is attached to.
required:
- compatible
--
2.39.2
Move internal SPM driver structures to the driver itself, removing them
from the public API. The CPUidle driver doesn't use them at all.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/soc/qcom/spm.c | 20 ++++++++++++++++++++
include/soc/qcom/spm.h | 23 +----------------------
2 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 2f0b1bfe7658..b15435f7cb0d 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -36,6 +36,26 @@ enum spm_reg {
SPM_REG_NR,
};
+#define MAX_PMIC_DATA 2
+#define MAX_SEQ_DATA 64
+
+struct spm_reg_data {
+ const u16 *reg_offset;
+ u32 spm_cfg;
+ u32 spm_dly;
+ u32 pmic_dly;
+ u32 pmic_data[MAX_PMIC_DATA];
+ u32 avs_ctl;
+ u32 avs_limit;
+ u8 seq[MAX_SEQ_DATA];
+ u8 start_index[PM_SLEEP_MODE_NR];
+};
+
+struct spm_driver_data {
+ void __iomem *reg_base;
+ const struct spm_reg_data *reg_data;
+};
+
static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
[SPM_REG_AVS_CTL] = 0x904,
[SPM_REG_AVS_LIMIT] = 0x908,
diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h
index 4951f9d8b0bd..5b263c685812 100644
--- a/include/soc/qcom/spm.h
+++ b/include/soc/qcom/spm.h
@@ -7,11 +7,6 @@
#ifndef __SPM_H__
#define __SPM_H__
-#include <linux/cpuidle.h>
-
-#define MAX_PMIC_DATA 2
-#define MAX_SEQ_DATA 64
-
enum pm_sleep_mode {
PM_SLEEP_MODE_STBY,
PM_SLEEP_MODE_RET,
@@ -20,23 +15,7 @@ enum pm_sleep_mode {
PM_SLEEP_MODE_NR,
};
-struct spm_reg_data {
- const u16 *reg_offset;
- u32 spm_cfg;
- u32 spm_dly;
- u32 pmic_dly;
- u32 pmic_data[MAX_PMIC_DATA];
- u32 avs_ctl;
- u32 avs_limit;
- u8 seq[MAX_SEQ_DATA];
- u8 start_index[PM_SLEEP_MODE_NR];
-};
-
-struct spm_driver_data {
- void __iomem *reg_base;
- const struct spm_reg_data *reg_data;
-};
-
+struct spm_driver_data;
void spm_set_low_power_mode(struct spm_driver_data *drv,
enum pm_sleep_mode mode);
--
2.39.2
Add SoC-specific compatibility strings to the L2 SAW2 unit. This is is
to distinguish the SAW2 units related to L2 cache and the CPU cores.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
index 2b1f9d0fb510..8d630db4005b 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
@@ -650,7 +650,7 @@ saw3: power-controller@f90b9000 {
};
saw_l2: power-controller@f9012000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
};
--
2.39.2
The SPM / SAW2 device also provides a voltage regulator functionality
with optional AVS (Adaptive Voltage Scaling) support. The exact register
sequence and voltage ranges differs from device to device.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
drivers/soc/qcom/spm.c | 234 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 229 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index b15435f7cb0d..5eefaec72a13 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -6,20 +6,40 @@
* SAW power controller driver
*/
-#include <linux/kernel.h>
+#include <linux/bitfield.h>
+#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/linear_range.h>
#include <linux/module.h>
-#include <linux/slab.h>
#include <linux/of.h>
-#include <linux/err.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+
+#include <linux/regulator/driver.h>
+
#include <soc/qcom/spm.h>
+#define FIELD_SET(current, mask, val) \
+ (((current) & ~(mask)) | FIELD_PREP((mask), (val)))
+
#define SPM_CTL_INDEX 0x7f
#define SPM_CTL_INDEX_SHIFT 4
#define SPM_CTL_EN BIT(0)
+/* These registers might be specific to SPM 1.1 */
+#define SPM_VCTL_VLVL GENMASK(7, 0)
+#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0)
+#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0)
+#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16)
+
+#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27)
+#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17)
+#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10)
+
enum spm_reg {
SPM_REG_CFG,
SPM_REG_SPM_CTL,
@@ -29,10 +49,12 @@ enum spm_reg {
SPM_REG_PMIC_DATA_1,
SPM_REG_VCTL,
SPM_REG_SEQ_ENTRY,
- SPM_REG_SPM_STS,
+ SPM_REG_STS0,
+ SPM_REG_STS1,
SPM_REG_PMIC_STS,
SPM_REG_AVS_CTL,
SPM_REG_AVS_LIMIT,
+ SPM_REG_RST,
SPM_REG_NR,
};
@@ -49,11 +71,20 @@ struct spm_reg_data {
u32 avs_limit;
u8 seq[MAX_SEQ_DATA];
u8 start_index[PM_SLEEP_MODE_NR];
+
+ smp_call_func_t set_vdd;
+ /* for now we support only a single range */
+ struct linear_range *range;
+ unsigned int ramp_delay;
+ unsigned int init_uV;
};
struct spm_driver_data {
void __iomem *reg_base;
const struct spm_reg_data *reg_data;
+ struct device *dev;
+ unsigned int volt_sel;
+ int reg_cpu;
};
static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = {
@@ -189,6 +220,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = {
static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
+ [SPM_REG_STS0] = 0x0c,
+ [SPM_REG_STS1] = 0x10,
+ [SPM_REG_VCTL] = 0x14,
+ [SPM_REG_AVS_CTL] = 0x18,
[SPM_REG_SPM_CTL] = 0x20,
[SPM_REG_PMIC_DLY] = 0x24,
[SPM_REG_PMIC_DATA_0] = 0x28,
@@ -196,7 +231,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = {
[SPM_REG_SEQ_ENTRY] = 0x80,
};
+static void smp_set_vdd_v1_1(void *data);
+
/* SPM register data for 8064 */
+static struct linear_range spm_v1_1_regulator_range =
+ REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
+
static const struct spm_reg_data spm_reg_8064_cpu = {
.reg_offset = spm_reg_offset_v1_1,
.spm_cfg = 0x1F,
@@ -207,6 +247,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
.start_index[PM_SLEEP_MODE_STBY] = 0,
.start_index[PM_SLEEP_MODE_SPC] = 2,
+ .set_vdd = smp_set_vdd_v1_1,
+ .range = &spm_v1_1_regulator_range,
+ .init_uV = 1300000,
+ .ramp_delay = 1250,
};
static inline void spm_register_write(struct spm_driver_data *drv,
@@ -258,6 +302,185 @@ void spm_set_low_power_mode(struct spm_driver_data *drv,
spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
}
+static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector)
+{
+ struct spm_driver_data *drv = rdev_get_drvdata(rdev);
+
+ drv->volt_sel = selector;
+
+ /* Always do the SAW register writes on the corresponding CPU */
+ return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
+}
+
+static int spm_get_voltage_sel(struct regulator_dev *rdev)
+{
+ struct spm_driver_data *drv = rdev_get_drvdata(rdev);
+
+ return drv->volt_sel;
+}
+
+static const struct regulator_ops spm_reg_ops = {
+ .set_voltage_sel = spm_set_voltage_sel,
+ .get_voltage_sel = spm_get_voltage_sel,
+ .list_voltage = regulator_list_voltage_linear_range,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+};
+
+static void smp_set_vdd_v1_1(void *data)
+{
+ struct spm_driver_data *drv = data;
+ unsigned int vctl, data0, data1, avs_ctl, sts;
+ unsigned int vlevel, volt_sel;
+ bool avs_enabled;
+
+ volt_sel = drv->volt_sel;
+ vlevel = volt_sel | 0x80; /* band */
+
+ avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL);
+ vctl = spm_register_read(drv, SPM_REG_VCTL);
+ data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0);
+ data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1);
+
+ avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED;
+
+ /* If AVS is enabled, switch it off during the voltage change */
+ if (avs_enabled) {
+ avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED;
+ spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+ }
+
+ /* Kick the state machine back to idle */
+ spm_register_write(drv, SPM_REG_RST, 1);
+
+ vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel);
+ data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel);
+ data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel);
+ data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel);
+
+ spm_register_write(drv, SPM_REG_VCTL, vctl);
+ spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0);
+ spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1);
+
+ if (read_poll_timeout_atomic(spm_register_read,
+ sts, sts == vlevel,
+ 1, 200, false,
+ drv, SPM_REG_STS1)) {
+ dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel);
+ goto enable_avs;
+ }
+
+ if (avs_enabled) {
+ unsigned int max_avs = volt_sel;
+ unsigned int min_avs = max(max_avs, 4U) - 4;
+
+ avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs);
+ avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs);
+ spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+ }
+
+enable_avs:
+ if (avs_enabled) {
+ avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED;
+ spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl);
+ }
+}
+
+static int spm_get_cpu(struct device *dev)
+{
+ int cpu;
+ bool found;
+
+ for_each_possible_cpu(cpu) {
+ struct device_node *cpu_node, *saw_node;
+
+ cpu_node = of_cpu_device_node_get(cpu);
+ if (!cpu_node)
+ continue;
+
+ saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
+ found = (saw_node == dev->of_node);
+ of_node_put(saw_node);
+ of_node_put(cpu_node);
+
+ if (found)
+ return cpu;
+ }
+
+ /* L2 SPM is not bound to any CPU, voltage setting is not supported */
+
+ return -EOPNOTSUPP;
+}
+
+#ifdef CONFIG_REGULATOR
+static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
+{
+ struct regulator_config config = {
+ .dev = dev,
+ .driver_data = drv,
+ };
+ struct regulator_desc *rdesc;
+ struct regulator_dev *rdev;
+ int ret;
+ bool found;
+
+ if (!drv->reg_data->set_vdd)
+ return 0;
+
+ rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
+ if (!rdesc)
+ return -ENOMEM;
+
+ rdesc->name = "spm";
+ rdesc->of_match = of_match_ptr("regulator");
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->owner = THIS_MODULE;
+ rdesc->ops = &spm_reg_ops;
+
+ rdesc->linear_ranges = drv->reg_data->range;
+ rdesc->n_linear_ranges = 1;
+ rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1;
+ rdesc->ramp_delay = drv->reg_data->ramp_delay;
+
+ ret = spm_get_cpu(dev);
+ if (ret < 0)
+ return ret;
+
+ drv->reg_cpu = ret;
+ dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu);
+
+ /*
+ * Program initial voltage, otherwise registration will also try
+ * setting the voltage, which might result in undervolting the CPU.
+ */
+ drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV,
+ rdesc->uV_step);
+ ret = linear_range_get_selector_high(drv->reg_data->range,
+ drv->reg_data->init_uV,
+ &drv->volt_sel,
+ &found);
+ if (ret) {
+ dev_err(dev, "Initial uV value out of bounds\n");
+ return ret;
+ }
+
+ /* Always do the SAW register writes on the corresponding CPU */
+ smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true);
+
+ rdev = devm_regulator_register(dev, rdesc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(dev, "failed to register regulator\n");
+ return PTR_ERR(rdev);
+ }
+
+ return 0;
+}
+#else
+static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv)
+{
+ return 0;
+}
+#endif
+
static const struct of_device_id spm_match_table[] = {
{ .compatible = "qcom,sdm660-gold-saw2-v4.1-l2",
.data = &spm_reg_660_gold_l2 },
@@ -308,6 +531,7 @@ static int spm_dev_probe(struct platform_device *pdev)
return -ENODEV;
drv->reg_data = match_id->data;
+ drv->dev = &pdev->dev;
platform_set_drvdata(pdev, drv);
/* Write the SPM sequences first.. */
@@ -335,7 +559,7 @@ static int spm_dev_probe(struct platform_device *pdev)
if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL])
spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
- return 0;
+ return spm_register_regulator(&pdev->dev, drv);
}
static struct platform_driver spm_driver = {
--
2.39.2
There is no such thing as a generic 'SAW2' device. Use device-specific
compatible strings to describe the SAW2 devices.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index f989bd741cd1..948c6fd91f62 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -351,31 +351,31 @@ acc3: power-manager@b0b8000 {
};
saw0: regulator@b089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw1: regulator@b099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw2: regulator@b0a9000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw3: regulator@b0b9000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw_l2: regulator@b012000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
reg = <0xb012000 0x1000>;
regulator;
};
--
2.39.2
There is no such thing as a generic 'SAW2' device. Use device-specific
compatible strings to describe the SAW2 devices.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 6a7f4dd0f775..0621853c24dd 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -587,7 +587,7 @@ acc0: clock-controller@2088000 {
};
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
@@ -602,7 +602,7 @@ acc1: clock-controller@2098000 {
};
saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
--
2.39.2
There is no such thing as a generic 'SAW2' device. Use device-specific
compatible strings to describe the SAW2 devices.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index f420740e068e..5099a161f7f9 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -221,13 +221,13 @@ acc1: clock-controller@2098000 {
};
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
--
2.39.2
Add SoC-specific compatibility strings to the L2 SAW2 unit. This is is
to distinguish the SAW2 units related to L2 cache and the CPU cores.
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index b1413983787c..16ee0baac27c 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -347,7 +347,7 @@ apcs: syscon@f9011000 {
};
saw_l2: power-controller@f9012000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
};
--
2.39.2
Per the power-domain.yaml, the power-controller node name is reserved
for power-domain providers. Rename SAW2 nodes to 'power-manager', the
name which is suggested by qcom,saw2.yaml
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 3faf57035d54..3066ee49daa7 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -365,25 +365,25 @@ acc3: clock-controller@20b8000 {
#clock-cells = <0>;
};
- saw0: power-controller@2089000 {
+ saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw1: power-controller@2099000 {
+ saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw2: power-controller@20a9000 {
+ saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw3: power-controller@20b9000 {
+ saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
regulator;
--
2.39.2
Per the power-domain.yaml, the power-controller node name is reserved
for power-domain providers. Rename SAW2 nodes to 'power-manager', the
name which is suggested by qcom,saw2.yaml
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
index 8d630db4005b..6fdf300ef65d 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
@@ -629,27 +629,27 @@ frame@f9028000 {
};
};
- saw0: power-controller@f9089000 {
+ saw0: power-manager@f9089000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
- saw1: power-controller@f9099000 {
+ saw1: power-manager@f9099000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
- saw2: power-controller@f90a9000 {
+ saw2: power-manager@f90a9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
- saw3: power-controller@f90b9000 {
+ saw3: power-manager@f90b9000 {
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
- saw_l2: power-controller@f9012000 {
+ saw_l2: power-manager@f9012000 {
compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
--
2.39.2
The SAW2 device is not a regulator. It is a frontend to the PMIC, which
handles voltage control, automatic voltage scaling and low-power states,
Rename SAW2 nodes to 'power-manager', the name which is suggested by
qcom,saw2.yaml
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 5099a161f7f9..84c3d3ac63b9 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -220,13 +220,13 @@ acc1: clock-controller@2098000 {
#clock-cells = <0>;
};
- saw0: regulator@2089000 {
+ saw0: power-manager@2089000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
- saw1: regulator@2099000 {
+ saw1: power-manager@2099000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
--
2.39.2
The SAW2 device is not a regulator. It is a frontend to the PMIC, which
handles voltage control, automatic voltage scaling and low-power states,
Rename SAW2 nodes to 'power-manager', the name which is suggested by
qcom,saw2.yaml
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index 948c6fd91f62..cc94942db468 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -350,31 +350,31 @@ acc3: power-manager@b0b8000 {
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
- saw0: regulator@b089000 {
+ saw0: power-manager@b089000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
- saw1: regulator@b099000 {
+ saw1: power-manager@b099000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
- saw2: regulator@b0a9000 {
+ saw2: power-manager@b0a9000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
- saw3: regulator@b0b9000 {
+ saw3: power-manager@b0b9000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
- saw_l2: regulator@b012000 {
+ saw_l2: power-manager@b012000 {
compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
reg = <0xb012000 0x1000>;
regulator;
--
2.39.2
Per the power-domain.yaml, the power-controller node name is reserved
for power-domain providers. Rename SAW2 nodes to 'power-manager', the
name which is suggested by qcom,saw2.yaml
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index 16ee0baac27c..e2008a8b89e1 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -346,7 +346,7 @@ apcs: syscon@f9011000 {
reg = <0xf9011000 0x1000>;
};
- saw_l2: power-controller@f9012000 {
+ saw_l2: power-manager@f9012000 {
compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
regulator;
@@ -424,7 +424,7 @@ acc0: power-manager@f9088000 {
reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
};
- saw0: power-controller@f9089000 {
+ saw0: power-manager@f9089000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
};
@@ -434,7 +434,7 @@ acc1: power-manager@f9098000 {
reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
};
- saw1: power-controller@f9099000 {
+ saw1: power-manager@f9099000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
};
@@ -444,7 +444,7 @@ acc2: power-manager@f90a8000 {
reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
};
- saw2: power-controller@f90a9000 {
+ saw2: power-manager@f90a9000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
};
@@ -454,7 +454,7 @@ acc3: power-manager@f90b8000 {
reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
};
- saw3: power-controller@f90b9000 {
+ saw3: power-manager@f90b9000 {
compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
};
--
2.39.2
The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
handle CPU-related PMIC regulators. Provide a way to control voltage of
these regulators.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
index 84c3d3ac63b9..e02e56a43fd5 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
@@ -223,13 +223,21 @@ acc1: clock-controller@2098000 {
saw0: power-manager@2089000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw0_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw1: power-manager@2099000 {
compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw1_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
gsbi5: gsbi@16400000 {
--
2.39.2
The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.
Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator node show be added
instead.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
index 6fdf300ef65d..8204e64d9a97 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
@@ -652,7 +652,6 @@ saw3: power-manager@f90b9000 {
saw_l2: power-manager@f9012000 {
compatible = "qcom,apq8084-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
- regulator;
};
acc0: power-manager@f9088000 {
--
2.39.2
The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.
Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator node show be added
instead.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index e2008a8b89e1..ec27260fe3d4 100644
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -349,7 +349,6 @@ apcs: syscon@f9011000 {
saw_l2: power-manager@f9012000 {
compatible = "qcom,msm8974-saw2-v2.1-l2", "qcom,saw2";
reg = <0xf9012000 0x1000>;
- regulator;
};
watchdog@f9017000 {
--
2.39.2
The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.
Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator nodes show be added
instead.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 4b35b1fd4b58..eb0eb2af6041 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -589,7 +589,6 @@ acc0: clock-controller@2088000 {
saw0: power-manager@2089000 {
compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
};
acc1: clock-controller@2098000 {
@@ -604,7 +603,6 @@ acc1: clock-controller@2098000 {
saw1: power-manager@2099000 {
compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
};
nss_common: syscon@3000000 {
--
2.39.2
The SAW2 device should describe the regulator constraints rather than
just declaring that it has the regulator.
Drop the 'regulator' property. If/when CPU voltage scaling is
implemented for this platform, proper regulator nodes show be added
instead.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index cc94942db468..bcc7ceb648ff 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -353,31 +353,26 @@ acc3: power-manager@b0b8000 {
saw0: power-manager@b089000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
saw1: power-manager@b099000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
saw2: power-manager@b0a9000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
saw3: power-manager@b0b9000 {
compatible = "qcom,ipq4019-saw2-cpu", "qcom,saw2";
reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
- regulator;
};
saw_l2: power-manager@b012000 {
compatible = "qcom,ipq4019-saw2-l2", "qcom,saw2";
reg = <0xb012000 0x1000>;
- regulator;
};
blsp1_uart1: serial@78af000 {
--
2.39.2
The SAW2 (SPM and AVS Wrapper) among other things is yet another way to
handle CPU-related PMIC regulators. Provide a way to control voltage of
these regulators.
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 3066ee49daa7..d1cbd2248558 100644
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -368,25 +368,41 @@ acc3: clock-controller@20b8000 {
saw0: power-manager@2089000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw0_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw1: power-manager@2099000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw1_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw2: power-manager@20a9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw2_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
saw3: power-manager@20b9000 {
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
- regulator;
+
+ saw3_vreg: regulator {
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <1300000>;
+ };
};
sps_sic_non_secure: sps-sic-non-secure@12100000 {
--
2.39.2
The SAW2 device is not a regulator. It is a frontend to the PMIC, which
handles voltage control, automatic voltage scaling and low-power states,
Rename SAW2 nodes to 'power-manager', the name which is suggested by
qcom,saw2.yaml
Signed-off-by: Dmitry Baryshkov <[email protected]>
---
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
index 0621853c24dd..4b35b1fd4b58 100644
--- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
@@ -586,7 +586,7 @@ acc0: clock-controller@2088000 {
#clock-cells = <0>;
};
- saw0: regulator@2089000 {
+ saw0: power-manager@2089000 {
compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
@@ -601,7 +601,7 @@ acc1: clock-controller@2098000 {
#clock-cells = <0>;
};
- saw1: regulator@2099000 {
+ saw1: power-manager@2099000 {
compatible = "qcom,ipq8064-saw2-cpu", "qcom,saw2";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
--
2.39.2
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> Add SoC-specific compatibility strings to the L2 SAW2 unit. This is is
> to distinguish the SAW2 units related to L2 cache and the CPU cores.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> Add SoC-specific compatibility strings to the L2 SAW2 unit. This is is
> to distinguish the SAW2 units related to L2 cache and the CPU cores.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> There is no such thing as a generic 'SAW2' device. Use device-specific
> compatible strings to describe the SAW2 devices.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> There is no such thing as a generic 'SAW2' device. Use device-specific
> compatible strings to describe the SAW2 devices.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> There is no such thing as a generic 'SAW2' device. Use device-specific
> compatible strings to describe the SAW2 devices.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> Per the power-domain.yaml, the power-controller node name is reserved
> for power-domain providers. Rename SAW2 nodes to 'power-manager', the
> name which is suggested by qcom,saw2.yaml
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> The SAW2 device is not a regulator. It is a frontend to the PMIC, which
> handles voltage control, automatic voltage scaling and low-power states,
> Rename SAW2 nodes to 'power-manager', the name which is suggested by
> qcom,saw2.yaml
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> Per the power-domain.yaml, the power-controller node name is reserved
> for power-domain providers. Rename SAW2 nodes to 'power-manager', the
> name which is suggested by qcom,saw2.yaml
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> The SAW2 device is not a regulator. It is a frontend to the PMIC, which
> handles voltage control, automatic voltage scaling and low-power states,
> Rename SAW2 nodes to 'power-manager', the name which is suggested by
> qcom,saw2.yaml
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> The SAW2 device is not a regulator. It is a frontend to the PMIC, which
> handles voltage control, automatic voltage scaling and low-power states,
> Rename SAW2 nodes to 'power-manager', the name which is suggested by
> qcom,saw2.yaml
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 2.01.2024 06:17, Dmitry Baryshkov wrote:
> The SPM / SAW2 device also provides a voltage regulator functionality
> with optional AVS (Adaptive Voltage Scaling) support. The exact register
> sequence and voltage ranges differs from device to device.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
I don't think I have more complaints here..
Acked-by: Konrad Dybcio <[email protected]>
Konrad
On 02/01/2024 06:17, Dmitry Baryshkov wrote:
> Define compatible strings for SAW2 units present on MSM8960, IPQ4019
> and IPQ8064. There is no need to include SAW version into the compat
> string, so just use the SoC and SAW2 kind.
>
> Also add missing L2 SAW2 compatibles for MSM8974 and APQ8084, they
> follow the existing CPU SAW2 strings.
>
> Signed-off-by: Dmitry Baryshkov <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Tue, 02 Jan 2024 07:17:20 +0200, Dmitry Baryshkov wrote:
> The apq8064 rework to use cacheinfo takes more than expected, so I've
> spanwed this series. It is an excerpt of the APQ8064 cpufreq series
> [1], so it it continues the version numbering for those patches.
>
> The Subsystem Power Manager (SPM) / SPM AutoVoltageScaling Wrapper2
> (SAW2) are hardware blocks used on some of Qualcomm platforms to handle
> the voltage rails. It does this by bypassing RPM and directly
> interfacing the PMIC. Extend current SPM driver to export this
> regulator.
>
> [...]
Applied, thanks!
[01/22] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml
commit: c9491a16e571d7f33e1d00d1ec4ce9b035bb290c
[02/22] dt-bindings: soc: qcom: qcom,saw2: add missing compatible strings
commit: 31ac56a59e7a8ed4ccd4831b73a1cc1ad9653b7f
[03/22] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node
commit: aa4e327fbbf665e96701fa1f53a97ae86b646603
[04/22] soc: qcom: spm: remove driver-internal structures from the driver API
commit: 57e2b067f19b8de616d1e849ce3786df602bfe7f
[05/22] soc: qcom: spm: add support for voltage regulator
commit: 6496dba142f4461360cae263126965e4ac761ab9
[06/22] ARM: dts: qcom: apq8084: use new compat string for L2 SAW2 unit
commit: 551d90275631a7dd2d290aa60aedabc597029216
[07/22] ARM: dts: qcom: msm8974: use new compat string for L2 SAW2 unit
commit: c0fe5442b1e5bcfbfe5272896e4dab23e1dfcc19
[08/22] ARM: dts: qcom: msm8960: use SoC-specific compatibles for SAW2 devices
commit: 9f77f78bd420ffddafe8c019c9e94097ef32c4d6
[09/22] ARM: dts: qcom: ipq4019: use SoC-specific compatibles for SAW2 devices
commit: 8cad85bfe08f419ea57a8a395e4ab0dcf346d617
[10/22] ARM: dts: qcom: ipq8064: use SoC-specific compatibles for SAW2 devices
commit: e6e2986a3d57a4d6590c3654d64cd417585c1c66
[11/22] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager
commit: 3a3b949fd9555190f2a477271b79e6194f0a824b
[12/22] ARM: dts: qcom: apq8084: rename SAW nodes to power-manager
commit: 07eb49b318000f8953c3de73f400b799215d6a32
[13/22] ARM: dts: qcom: msm8960: rename SAW nodes to power-manager
commit: 34725e24f20d98a9bba2850934c2adef65b9ec0e
[14/22] ARM: dts: qcom: msm8974: rename SAW nodes to power-manager
commit: e624dc495a425dc0598688c8c1aa5c028ca30750
[15/22] ARM: dts: qcom: ipq4019: rename SAW nodes to power-manager
commit: 3ea06103ee40351dc4793e37c0e51e00753e3d26
[16/22] ARM: dts: qcom: ipq8064: rename SAW nodes to power-manager
commit: 04e354e0b4dd409298c1909fdd8897055e9b3641
[17/22] ARM: dts: qcom: apq8064: declare SAW2 regulators
commit: 893768803fa4ab7e5d75448980832b517d251a25
[18/22] ARM: dts: qcom: msm8960: declare SAW2 regulators
commit: 378cc1b3e6cd3cab1f8c4a5e1891664545c2c7e9
[19/22] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device
commit: 8c843db2bca12e911e0d0343c52a9e9a17704ae3
[20/22] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device
commit: a560ff0acc0418e3c689ca2b050e00f964020b14
[21/22] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices
commit: c169576dddff63be2108cb289a9ab1b7fc19ef53
[22/22] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices
commit: 4ad2506d5a17387dcbedbd24e60d33f6421e249e
Best regards,
--
Bjorn Andersson <[email protected]>