2024-02-06 18:43:50

by Konrad Dybcio

Subject: [PATCH v2 00/18] Qualcomm GCC/VIDEOCC reset overhaul for Venus

Some resets associated with venus require a larger delay for the hardware
on the other end to function properly. These seem to fall into three
categories:

- 150us for 8250 and earlier
- 400us for 8350 and friends
- 1000us for >=8450

Make some housecleaning changes and describe these delays in preparation
to moving this data out of the venus driver.

Signed-off-by: Konrad Dybcio <[email protected]>
---
Changes in v2:
- Wrap the function parameters in patch 2
- Better describe the sources of reset delay values
- Pick up tags, rebase (with no changes)
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Konrad Dybcio (18):
clk: qcom: reset: Increase max reset delay
clk: qcom: reset: Commonize the de/assert functions
clk: qcom: reset: Ensure write completion on reset de/assertion
clk: qcom: gcc-sa8775p: Set delay for Venus CLK resets
clk: qcom: gcc-sc8180x: Set delay for Venus CLK resets
clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resets
clk: qcom: gcc-sm4450: Set delay for Venus CLK resets
clk: qcom: gcc-sm7150: Set delay for Venus CLK resets
clk: qcom: gcc-sm8250: Set delay for Venus CLK resets
clk: qcom: gcc-sm8350: Set delay for Venus CLK resets
clk: qcom: gcc-sm8450: Set delay for Venus CLK resets
clk: qcom: gcc-sm8550: Set delay for Venus CLK resets
clk: qcom: gcc-sm8650: Set delay for Venus CLK resets
clk: qcom: videocc-sm8150: Set delay for Venus CLK resets
clk: qcom: videocc-sm8250: Set delay for Venus CLK resets
clk: qcom: videocc-sm8350: Set delay for Venus CLK resets
clk: qcom: videocc-sm8450: Set delay for Venus CLK resets
clk: qcom: videocc-sm8550: Set delay for Venus CLK resets

drivers/clk/qcom/gcc-sa8775p.c | 4 ++--
drivers/clk/qcom/gcc-sc8180x.c | 6 +++---
drivers/clk/qcom/gcc-sc8280xp.c | 4 ++--
drivers/clk/qcom/gcc-sm4450.c | 4 ++--
drivers/clk/qcom/gcc-sm7150.c | 2 +-
drivers/clk/qcom/gcc-sm8250.c | 4 ++--
drivers/clk/qcom/gcc-sm8350.c | 4 ++--
drivers/clk/qcom/gcc-sm8450.c | 4 ++--
drivers/clk/qcom/gcc-sm8550.c | 4 ++--
drivers/clk/qcom/gcc-sm8650.c | 4 ++--
drivers/clk/qcom/reset.c | 27 ++++++++++++++-------------
drivers/clk/qcom/reset.h | 2 +-
drivers/clk/qcom/videocc-sm8150.c | 2 +-
drivers/clk/qcom/videocc-sm8250.c | 4 ++--
drivers/clk/qcom/videocc-sm8350.c | 4 ++--
drivers/clk/qcom/videocc-sm8450.c | 4 ++--
drivers/clk/qcom/videocc-sm8550.c | 4 ++--
17 files changed, 44 insertions(+), 43 deletions(-)
---
base-commit: ac139fc7db67968e5061715508b5fc4aa7c40c56
change-id: 20240105-topic-venus_reset-b5461bf1a087

Best regards,
--
Konrad Dybcio <[email protected]>

2024-02-06 18:44:02

by Konrad Dybcio

Subject: [PATCH v2 01/18] clk: qcom: reset: Increase max reset delay

u8 limits us to 255 microseconds of delay. Promote the delay variable to
u16 to hold bigger values.

Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/reset.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/reset.h b/drivers/clk/qcom/reset.h
index 9a47c838d9b1..fe0561bf53d4 100644
--- a/drivers/clk/qcom/reset.h
+++ b/drivers/clk/qcom/reset.h
@@ -11,7 +11,7 @@
struct qcom_reset_map {
unsigned int reg;
u8 bit;
- u8 udelay;
+ u16 udelay;
u32 bitmask;
};


--
2.43.0

2024-02-06 18:44:34

by Konrad Dybcio

Subject: [PATCH v2 03/18] clk: qcom: reset: Ensure write completion on reset de/assertion

Trying to toggle the resets in a rapid fashion can lead to the changes
not actually arriving at the clock controller block when we expect them
to. This was observed at least on SM8250.

Read back the value after regmap_update_bits to ensure write completion.

Fixes: db1029814f1f ("clk: qcom: reset: Ensure write completion on reset de/assertion")
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/reset.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c
index 20d1d35aaf22..d96c96a9089f 100644
--- a/drivers/clk/qcom/reset.c
+++ b/drivers/clk/qcom/reset.c
@@ -33,7 +33,12 @@ static int qcom_reset_set_assert(struct reset_controller_dev *rcdev,
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);

- return regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
+ regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
+
+ /* Read back the register to ensure write completion, ignore the value */
+ regmap_read(rst->regmap, map->reg, &mask);
+
+ return 0;
}

static int qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)

--
2.43.0

2024-02-06 18:44:49

by Konrad Dybcio

Subject: [PATCH v2 04/18] clk: qcom: gcc-sa8775p: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained on a best-guess basis: msm-5.4 being the base
kernel for this SoC and 8775 being generally close to 8350 which is known
to require a higher delay [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sa8775p.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 8171d23c96e6..c2b403cb6301 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4662,8 +4662,8 @@ static const struct qcom_reset_map gcc_sa8775p_resets[] = {
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5c020 },
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x5c024 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x76000 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0x34014, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3401c, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x34014, .bit = 2, .udelay = 400 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x3401c, .bit = 2, .udelay = 400 },
[GCC_VIDEO_BCR] = { 0x34000 },
};


--
2.43.0

2024-02-06 18:45:02

by Konrad Dybcio

Subject: [PATCH v2 05/18] clk: qcom: gcc-sc8180x: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained by referencing the msm-4.19 driver, which uses a
single value for all platforms [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sc8180x.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index ae2147381559..1351c52bcacb 100644
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -4528,9 +4528,9 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
[GCC_USB30_PRIM_BCR] = { 0xf000 },
[GCC_USB30_SEC_BCR] = { 0x10000 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
- [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
- [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
- [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
+ [GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 },
+ [GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 },
+ [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
};

static struct gdsc *gcc_sc8180x_gdscs[] = {

--
2.43.0

2024-02-06 18:45:41

by Konrad Dybcio

Subject: [PATCH v2 07/18] clk: qcom: gcc-sm4450: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained on a best-guess basis: msm-5.4 being the base
kernel for this SoC and 4450 being somewhat close to 8350 which is known
to require a higher delay [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm4450.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm4450.c b/drivers/clk/qcom/gcc-sm4450.c
index 31abe2775fc8..ab8fb77d15a2 100644
--- a/drivers/clk/qcom/gcc-sm4450.c
+++ b/drivers/clk/qcom/gcc-sm4450.c
@@ -2791,8 +2791,8 @@ static const struct qcom_reset_map gcc_sm4450_resets[] = {
[GCC_VENUS_BCR] = { 0xb601c },
[GCC_VIDEO_BCR] = { 0x42000 },
[GCC_VIDEO_VENUS_BCR] = { 0xb6000 },
- [GCC_VENUS_CTL_AXI_CLK_ARES] = { 0x4201c, 2 },
- [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { 0xb6038, 2 },
+ [GCC_VENUS_CTL_AXI_CLK_ARES] = { .reg = 0x4201c, .bit = 2, .udelay = 400 },
+ [GCC_VIDEO_VENUS_CTL_CLK_ARES] = { .reg = 0xb6038, .bit = 2, .udelay = 400 },
};

static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {

--
2.43.0

2024-02-06 18:45:47

by Konrad Dybcio

Subject: [PATCH v2 08/18] clk: qcom: gcc-sm7150: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained by referencing the msm-4.14/19 driver, which uses a
single value for all platforms [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm7150.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-sm7150.c b/drivers/clk/qcom/gcc-sm7150.c
index d9983bb27475..7c5596331c30 100644
--- a/drivers/clk/qcom/gcc-sm7150.c
+++ b/drivers/clk/qcom/gcc-sm7150.c
@@ -2918,7 +2918,7 @@ static const struct qcom_reset_map gcc_sm7150_resets[] = {
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
- [GCC_VIDEO_AXI_CLK_BCR] = { 0xb01c, 2 },
+ [GCC_VIDEO_AXI_CLK_BCR] = { .reg = 0xb01c, .bit = 2, .udelay = 150 },
};

static const struct clk_rcg_dfs_data gcc_sm7150_dfs_desc[] = {

--
2.43.0

2024-02-06 18:46:47

by Konrad Dybcio

Subject: [PATCH v2 12/18] clk: qcom: gcc-sm8550: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value for SM8550 is known and extracted from the msm-5.15 driver.

Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm8550.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c
index b883dffe5f7a..4cbc728f5c72 100644
--- a/drivers/clk/qcom/gcc-sm8550.c
+++ b/drivers/clk/qcom/gcc-sm8550.c
@@ -3276,8 +3276,8 @@ static const struct qcom_reset_map gcc_sm8550_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_BCR] = { 0x32000 },
};


--
2.43.0

2024-02-06 18:46:47

by Konrad Dybcio

Subject: [PATCH v2 10/18] clk: qcom: gcc-sm8350: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8350, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm8350.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
index 1385a98eb3bb..df4842588a24 100644
--- a/drivers/clk/qcom/gcc-sm8350.c
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -3743,8 +3743,8 @@ static const struct qcom_reset_map gcc_sm8350_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
[GCC_VIDEO_BCR] = { 0x28000 },
};


--
2.43.0

2024-02-06 18:47:16

by Konrad Dybcio

Subject: [PATCH v2 13/18] clk: qcom: gcc-sm8650: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The Venus hw on 8650 is similar to the one on 8550, follow its
requirements.

Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm8650.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8650.c b/drivers/clk/qcom/gcc-sm8650.c
index 9174dd82308c..63becb03cd90 100644
--- a/drivers/clk/qcom/gcc-sm8650.c
+++ b/drivers/clk/qcom/gcc-sm8650.c
@@ -3734,8 +3734,8 @@ static const struct qcom_reset_map gcc_sm8650_resets[] = {
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0x32024, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x32018, .bit = 2, .udelay = 1000 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x32024, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_BCR] = { 0x32000 },
};


--
2.43.0

2024-02-06 18:47:18

by Konrad Dybcio

Subject: [PATCH v2 14/18] clk: qcom: videocc-sm8150: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained by referencing the msm-4.14/19 driver, which uses a
single value for all platforms [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/videocc-sm8150.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-sm8150.c
index f1456eaa87c4..bead5186a5d6 100644
--- a/drivers/clk/qcom/videocc-sm8150.c
+++ b/drivers/clk/qcom/videocc-sm8150.c
@@ -215,7 +215,7 @@ static const struct regmap_config video_cc_sm8150_regmap_config = {
};

static const struct qcom_reset_map video_cc_sm8150_resets[] = {
- [VIDEO_CC_MVSC_CORE_CLK_BCR] = { 0x850, 2 },
+ [VIDEO_CC_MVSC_CORE_CLK_BCR] = { .reg = 0x850, .bit = 2, .udelay = 150 },
[VIDEO_CC_INTERFACE_BCR] = { 0x8f0 },
[VIDEO_CC_MVS0_BCR] = { 0x870 },
[VIDEO_CC_MVS1_BCR] = { 0x8b0 },

--
2.43.0

2024-02-06 18:47:31

by Konrad Dybcio

Subject: [PATCH v2 15/18] clk: qcom: videocc-sm8250: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained by referencing the msm-4.14/19 driver, which uses a
single value for all platforms [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/videocc-sm8250.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c
index ad46c4014a40..51b9816ec458 100644
--- a/drivers/clk/qcom/videocc-sm8250.c
+++ b/drivers/clk/qcom/videocc-sm8250.c
@@ -323,10 +323,10 @@ static struct clk_regmap *video_cc_sm8250_clocks[] = {
static const struct qcom_reset_map video_cc_sm8250_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
- [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
+ [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, .bit = 2, .udelay = 150 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
- [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
+ [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, .bit = 2, .udelay = 150 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};


--
2.43.0

2024-02-06 18:47:54

by Konrad Dybcio

Subject: [PATCH v2 16/18] clk: qcom: videocc-sm8350: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8350, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/videocc-sm8350.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c
index 7246f3c99492..8db2bb995558 100644
--- a/drivers/clk/qcom/videocc-sm8350.c
+++ b/drivers/clk/qcom/videocc-sm8350.c
@@ -488,10 +488,10 @@ static struct clk_regmap *video_cc_sm8350_clocks[] = {
static const struct qcom_reset_map video_cc_sm8350_resets[] = {
[VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 },
[VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 },
- [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 },
+ [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0xc34, .bit = 2, .udelay = 400 },
[VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 },
[VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 },
- [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 },
+ [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0xcd4, .bit = 2, .udelay = 400 },
[VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 },
};


--
2.43.0

2024-02-06 18:48:09

by Konrad Dybcio

Subject: [PATCH v2 17/18] clk: qcom: videocc-sm8450: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8450, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/videocc-sm8450.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index 16a61146e619..67ca302a0737 100644
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -373,8 +373,8 @@ static const struct qcom_reset_map video_cc_sm8450_resets[] = {
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
- [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
- [VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
+ [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
+ [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x808c, .bit = 2, .udelay = 1000 },
};

static const struct regmap_config video_cc_sm8450_regmap_config = {

--
2.43.0

2024-02-06 18:48:24

by Konrad Dybcio

Subject: [PATCH v2 18/18] clk: qcom: videocc-sm8550: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value for SM8550 is known and extracted from the msm-5.15 driver.

Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/videocc-sm8550.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
index f3c9dfaee968..e3f146347da7 100644
--- a/drivers/clk/qcom/videocc-sm8550.c
+++ b/drivers/clk/qcom/videocc-sm8550.c
@@ -378,8 +378,8 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80c8 },
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8074 },
- [VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
- [VIDEO_CC_MVS1C_CLK_ARES] = { 0x8090, 2 },
+ [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0x8064, .bit = 2, .udelay = 1000 },
+ [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0x8090, .bit = 2, .udelay = 1000 },
};

static const struct regmap_config video_cc_sm8550_regmap_config = {

--
2.43.0

2024-02-06 18:48:29

by Konrad Dybcio

Subject: [PATCH v2 06/18] clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained on a best-guess basis: msm-5.4 being the base
kernel for this SoC and 8280 being generally close to 8350 which is known
to require a higher delay [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/dfe241edf23daf3c1ccbb79b02798965123fad98
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sc8280xp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c
index bfb77931e868..9f4db815688c 100644
--- a/drivers/clk/qcom/gcc-sc8280xp.c
+++ b/drivers/clk/qcom/gcc-sc8280xp.c
@@ -7448,8 +7448,8 @@ static const struct qcom_reset_map gcc_sc8280xp_resets[] = {
[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x4a004 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
[GCC_VIDEO_BCR] = { 0x28000 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0x28010, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0x28018, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x28010, .bit = 2, .udelay = 400 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x28018, .bit = 2, .udelay = 400 },
};

static struct gdsc *gcc_sc8280xp_gdscs[] = {

--
2.43.0

2024-02-06 19:05:23

by Konrad Dybcio

Subject: [PATCH v2 11/18] clk: qcom: gcc-sm8450: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value is known for SM8450, see [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/commit/d0730ea5867264ee50b793f6700eb6a376ddcbbb
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm8450.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index 563542982551..1825b3456dd0 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -3202,8 +3202,8 @@ static const struct qcom_reset_map gcc_sm8450_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x60004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x60010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x7a000 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0x42018, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0x42020, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { .reg = 0x42018, .bit = 2, .udelay = 1000 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { .reg = 0x42020, .bit = 2, .udelay = 1000 },
[GCC_VIDEO_BCR] = { 0x42000 },
};


--
2.43.0

2024-02-06 19:07:38

by Konrad Dybcio

Subject: [PATCH v2 09/18] clk: qcom: gcc-sm8250: Set delay for Venus CLK resets

Some Venus resets may require more time when toggling. Describe that.

The value was obtained by referencing the msm-4.19 driver, which uses a
single value for all platforms [1].

[1] https://git.codelinaro.org/clo/la/platform/vendor/opensource/video-driver/-/blob/LA.UM.9.15.c26/msm/vidc/hfi_common.c?ref_type=heads#L3662-3663
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/gcc-sm8250.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c
index c6c5261264f1..61d01d4c379b 100644
--- a/drivers/clk/qcom/gcc-sm8250.c
+++ b/drivers/clk/qcom/gcc-sm8250.c
@@ -3576,8 +3576,8 @@ static const struct qcom_reset_map gcc_sm8250_resets[] = {
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
- [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, 2 },
- [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, 2 },
+ [GCC_VIDEO_AXI0_CLK_ARES] = { 0xb024, .bit = 2, .udelay = 150 },
+ [GCC_VIDEO_AXI1_CLK_ARES] = { 0xb028, .bit = 2, .udelay = 150 },
};

static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = {

--
2.43.0

2024-02-06 19:13:14

by Konrad Dybcio

Subject: [PATCH v2 02/18] clk: qcom: reset: Commonize the de/assert functions

They do the same thing, except the last argument of the last function
call differs. Commonize them.

Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/reset.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/qcom/reset.c b/drivers/clk/qcom/reset.c
index e45e32804d2c..20d1d35aaf22 100644
--- a/drivers/clk/qcom/reset.c
+++ b/drivers/clk/qcom/reset.c
@@ -22,8 +22,8 @@ static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
return 0;
}

-static int
-qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
+static int qcom_reset_set_assert(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
{
struct qcom_reset_controller *rst;
const struct qcom_reset_map *map;
@@ -33,21 +33,17 @@ qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
map = &rst->reset_map[id];
mask = map->bitmask ? map->bitmask : BIT(map->bit);

- return regmap_update_bits(rst->regmap, map->reg, mask, mask);
+ return regmap_update_bits(rst->regmap, map->reg, mask, assert ? mask : 0);
}

-static int
-qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+static int qcom_reset_assert(struct reset_controller_dev *rcdev, unsigned long id)
{
- struct qcom_reset_controller *rst;
- const struct qcom_reset_map *map;
- u32 mask;
-
- rst = to_qcom_reset_controller(rcdev);
- map = &rst->reset_map[id];
- mask = map->bitmask ? map->bitmask : BIT(map->bit);
+ return qcom_reset_set_assert(rcdev, id, true);
+}

- return regmap_update_bits(rst->regmap, map->reg, mask, 0);
+static int qcom_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ return qcom_reset_set_assert(rcdev, id, false);
}

const struct reset_control_ops qcom_reset_ops = {

--
2.43.0

2024-02-07 04:48:27

by Bjorn Andersson

Subject: Re: [PATCH v2 00/18] Qualcomm GCC/VIDEOCC reset overhaul for Venus

On Tue, 06 Feb 2024 19:43:33 +0100, Konrad Dybcio wrote:
> Some resets associated with venus require a larger delay for the hardware
> on the other end to function properly. These seem to fall into three
> categories:
>
> - 150us for 8250 and earlier
> - 400us for 8350 and friends
> - 1000us for >=8450
>
> [...]

Applied, thanks!

[01/18] clk: qcom: reset: Increase max reset delay
commit: 316861f383176c6360dcffecceb1f843d860faf0
[02/18] clk: qcom: reset: Commonize the de/assert functions
commit: eda40d9c583e95e0b6ac69d2950eec10f802e0e8
[03/18] clk: qcom: reset: Ensure write completion on reset de/assertion
commit: 1bd8c3ad02b1aaa9163a72fece2c28360a52b345
[04/18] clk: qcom: gcc-sa8775p: Set delay for Venus CLK resets
commit: 6c0530974183709e74c3e809d4f0df386a23465b
[05/18] clk: qcom: gcc-sc8180x: Set delay for Venus CLK resets
commit: 627fcb22966d9e7dcfcc040f3895e5da7f64fb9c
[06/18] clk: qcom: gcc-sc8280xp: Set delay for Venus CLK resets
commit: 446b8e191072b78de4af16f5288dcdbfbda78dd1
[07/18] clk: qcom: gcc-sm4450: Set delay for Venus CLK resets
commit: eff85a0f548e536563d57d42bdd6c215031e8c84
[08/18] clk: qcom: gcc-sm7150: Set delay for Venus CLK resets
commit: b8b2343112083f76a4183aa2acdfe861dcc1bb6b
[09/18] clk: qcom: gcc-sm8250: Set delay for Venus CLK resets
commit: 2013a0bca5679dab16fc0f4b7dde4cf8b15b7621
[10/18] clk: qcom: gcc-sm8350: Set delay for Venus CLK resets
commit: cecdccc3e50924a09411f8f9af760f4d1ef8b5c6
[11/18] clk: qcom: gcc-sm8450: Set delay for Venus CLK resets
commit: 6ad1da7c0f2317ceffdfe50ac913b6123cd6ff71
[12/18] clk: qcom: gcc-sm8550: Set delay for Venus CLK resets
commit: d64c6880c44e3a6d52b97dda1082c17317c82c74
[13/18] clk: qcom: gcc-sm8650: Set delay for Venus CLK resets
commit: 6efbf3e21211ece0b49bb75499398f9f08fb9cd6
[14/18] clk: qcom: videocc-sm8150: Set delay for Venus CLK resets
commit: 23fd517957693846ed279cb86f30f548aed01fda
[15/18] clk: qcom: videocc-sm8250: Set delay for Venus CLK resets
commit: 726184dd7b2f7c41a7007a1c1add301ddf173cf2
[16/18] clk: qcom: videocc-sm8350: Set delay for Venus CLK resets
commit: b68d14f84c2c179d0f56588bda2e3a2675dd6d28
[17/18] clk: qcom: videocc-sm8450: Set delay for Venus CLK resets
commit: ed17763a24f22d04e8da104715eb48ba69989dfa
[18/18] clk: qcom: videocc-sm8550: Set delay for Venus CLK resets
commit: ba4354f6ae160609aea8f7adec22ce1a9d0f586a

Best regards,
--
Bjorn Andersson <[email protected]>

2024-02-07 09:07:29

by Johan Hovold

Subject: Re: [PATCH v2 03/18] clk: qcom: reset: Ensure write completion on reset de/assertion

On Tue, Feb 06, 2024 at 07:43:36PM +0100, Konrad Dybcio wrote:
> Trying to toggle the resets in a rapid fashion can lead to the changes
> not actually arriving at the clock controller block when we expect them
> to. This was observed at least on SM8250.
>
> Read back the value after regmap_update_bits to ensure write completion.
>
> Fixes: db1029814f1f ("clk: qcom: reset: Ensure write completion on reset de/assertion")

This commit does not exist in mainline or linux-next it seems.

Johan

2024-02-07 11:53:08

by Konrad Dybcio

Subject: Re: [PATCH v2 03/18] clk: qcom: reset: Ensure write completion on reset de/assertion

On 7.02.2024 10:07, Johan Hovold wrote:
> On Tue, Feb 06, 2024 at 07:43:36PM +0100, Konrad Dybcio wrote:
>> Trying to toggle the resets in a rapid fashion can lead to the changes
>> not actually arriving at the clock controller block when we expect them
>> to. This was observed at least on SM8250.
>>
>> Read back the value after regmap_update_bits to ensure write completion.
>>
>> Fixes: db1029814f1f ("clk: qcom: reset: Ensure write completion on reset de/assertion")
>
> This commit does not exist in mainline or linux-next it seems.

Yeah, I managed to copy the last and not the first commit hash concerning
reset.c :/

Konrad