- Add dt-bindings
- i.MX95 ELE/V2X use same register layout as i.MX8ULP S4 MU, but
the TR/RR num is different. To make code reusable and not add too much
macros, add runtime detect number of TR and RR by reading PAR_OFF
registers.
- Add i.MX95 ELE/V2X MU entry in driver
Signed-off-by: Peng Fan <[email protected]>
---
Changes in v4:
- Address dt-binding comments in V2 from Krzysztof
- Link to v3: https://lore.kernel.org/r/[email protected]
Changes in v3:
- Following dts coding style Per Krzysztof
- Add return type for init function, patch 2 is new
- Check return value when tr/rr is larger than 4 and return error.
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Support sram property and add example
- Populate the sram node in driver
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Peng Fan (4):
dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
mailbox: imx: support return value of init
mailbox: imx: get RR/TR registers num from Parameter register
mailbox: imx: support i.MX95 ELE/V2X MU
.../devicetree/bindings/mailbox/fsl,mu.yaml | 52 ++++++++++++-
drivers/mailbox/imx-mailbox.c | 87 ++++++++++++++++------
2 files changed, 115 insertions(+), 24 deletions(-)
---
base-commit: ad5c60d66016e544c51ed98635a74073f761f45d
change-id: 20240122-imx-mailbox-243021d12030
Best regards,
--
Peng Fan <[email protected]>
From: Peng Fan <[email protected]>
Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string.
And some MUs has internal RAMs for SCMI shared buffer usage.
Signed-off-by: Peng Fan <[email protected]>
---
.../devicetree/bindings/mailbox/fsl,mu.yaml | 52 +++++++++++++++++++++-
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
index 12e7a7d536a3..86759831b24a 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
@@ -29,10 +29,14 @@ properties:
- const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- const: fsl,imx8-mu-seco
- - const: fsl,imx93-mu-s4
- const: fsl,imx8ulp-mu-s4
+ - const: fsl,imx93-mu-s4
+ - const: fsl,imx95-mu-ele
+ - const: fsl,imx95-mu-v2x
- items:
- - const: fsl,imx93-mu
+ - enum:
+ - fsl,imx93-mu
+ - fsl,imx95-mu
- const: fsl,imx8ulp-mu
- items:
- enum:
@@ -95,6 +99,19 @@ properties:
power-domains:
maxItems: 1
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+patternProperties:
+ "^sram@[a-f0-9]+":
+ $ref: /schemas/sram/sram.yaml#
+ unevaluatedProperties: false
+
required:
- compatible
- reg
@@ -134,3 +151,34 @@ examples:
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mu2: mailbox@445b0000 {
+ compatible = "fsl,imx95-mu", "fsl,imx8ulp-mu";
+ reg = <0x445b0000 0x10000>;
+ ranges;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #mbox-cells = <2>;
+
+ sram@445b1000 {
+ compatible = "mmio-sram";
+ reg = <0x445b1000 0x400>;
+ ranges = <0x0 0x445b1000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scmi_buf0: scmi-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ scmi_buf1: scmi-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+ };
+ };
--
2.37.1
From: Peng Fan <[email protected]>
There will be changes that init may fail, so adding return value for
init function.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/mailbox/imx-mailbox.c | 35 ++++++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 656171362fe9..dced4614065f 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -110,7 +110,7 @@ struct imx_mu_dcfg {
int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
- void (*init)(struct imx_mu_priv *priv);
+ int (*init)(struct imx_mu_priv *priv);
enum imx_mu_type type;
u32 xTR; /* Transmit Register0 */
u32 xRR; /* Receive Register0 */
@@ -737,7 +737,7 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
return imx_mu_xlate(mbox, sp);
}
-static void imx_mu_init_generic(struct imx_mu_priv *priv)
+static int imx_mu_init_generic(struct imx_mu_priv *priv)
{
unsigned int i;
unsigned int val;
@@ -757,7 +757,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
priv->mbox.of_xlate = imx_mu_xlate;
if (priv->side_b)
- return;
+ return 0;
/* Set default MU configuration */
for (i = 0; i < IMX_MU_xCR_MAX; i++)
@@ -770,9 +770,11 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
/* Clear any pending RSR */
for (i = 0; i < IMX_MU_NUM_RR; i++)
imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
+
+ return 0;
}
-static void imx_mu_init_specific(struct imx_mu_priv *priv)
+static int imx_mu_init_specific(struct imx_mu_priv *priv)
{
unsigned int i;
int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
@@ -794,12 +796,20 @@ static void imx_mu_init_specific(struct imx_mu_priv *priv)
/* Set default MU configuration */
for (i = 0; i < IMX_MU_xCR_MAX; i++)
imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
+
+ return 0;
}
-static void imx_mu_init_seco(struct imx_mu_priv *priv)
+static int imx_mu_init_seco(struct imx_mu_priv *priv)
{
- imx_mu_init_generic(priv);
+ int ret;
+
+ ret = imx_mu_init_generic(priv);
+ if (ret)
+ return ret;
priv->mbox.of_xlate = imx_mu_seco_xlate;
+
+ return 0;
}
static int imx_mu_probe(struct platform_device *pdev)
@@ -866,7 +876,11 @@ static int imx_mu_probe(struct platform_device *pdev)
priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
- priv->dcfg->init(priv);
+ ret = priv->dcfg->init(priv);
+ if (ret) {
+ dev_err(dev, "Failed to init MU\n");
+ goto disable_clk;
+ }
spin_lock_init(&priv->xcr_lock);
@@ -878,10 +892,8 @@ static int imx_mu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, priv);
ret = devm_mbox_controller_register(dev, &priv->mbox);
- if (ret) {
- clk_disable_unprepare(priv->clk);
- return ret;
- }
+ if (ret)
+ goto disable_clk;
pm_runtime_enable(dev);
@@ -899,6 +911,7 @@ static int imx_mu_probe(struct platform_device *pdev)
disable_runtime_pm:
pm_runtime_disable(dev);
+disable_clk:
clk_disable_unprepare(priv->clk);
return ret;
}
--
2.37.1
From: Peng Fan <[email protected]>
i.MX8ULP, i.MX93 MU has a Parameter register encoded as below:
BIT: 15 --- 8 | 7 --- 0
RR_NUM TR_NUM
So to make driver easy to support more variants, get the RR/TR
registers number from Parameter register.
The patch only adds support the specific MU, such as ELE MU.
For generic MU, not add support for number larger than 4.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/mailbox/imx-mailbox.c | 46 ++++++++++++++++++++++++++++++++-----------
1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index dced4614065f..9e89f773d2f9 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -29,7 +29,9 @@
#define IMX_MU_S4_CHANS 2
#define IMX_MU_CHAN_NAME_SIZE 20
-#define IMX_MU_NUM_RR 4
+#define IMX_MU_V2_PAR_OFF 0x4
+#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
@@ -93,10 +95,11 @@ struct imx_mu_priv {
struct clk *clk;
int irq[IMX_MU_CHANS];
bool suspend;
-
- u32 xcr[IMX_MU_xCR_MAX];
-
bool side_b;
+
+ u32 xcr[IMX_MU_xCR_MAX];
+ u32 num_tr;
+ u32 num_rr;
};
enum imx_mu_type {
@@ -264,18 +267,17 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
{
u32 *arg = data;
+ u32 num_tr = priv->num_tr;
int i, ret;
u32 xsr;
- u32 size, max_size, num_tr;
+ u32 size, max_size;
if (priv->dcfg->type & IMX_MU_V2_S4) {
size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
max_size = sizeof(struct imx_s4_rpc_msg_max);
- num_tr = 8;
} else {
size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
max_size = sizeof(struct imx_sc_rpc_msg_max);
- num_tr = 4;
}
switch (cp->type) {
@@ -324,6 +326,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
int i, ret;
u32 xsr;
u32 size, max_size;
+ u32 num_rr = priv->num_rr;
data = (u32 *)priv->msg;
@@ -345,13 +348,13 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
for (i = 1; i < size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
- xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
+ xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
5 * USEC_PER_SEC);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;
}
- *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
+ *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
}
imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
@@ -737,11 +740,30 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
return imx_mu_xlate(mbox, sp);
}
+static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
+{
+ u32 val;
+
+ if (priv->dcfg->type & IMX_MU_V2) {
+ val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
+ priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
+ priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
+ } else {
+ priv->num_tr = 4;
+ priv->num_rr = 4;
+ }
+}
+
static int imx_mu_init_generic(struct imx_mu_priv *priv)
{
unsigned int i;
unsigned int val;
+ if (priv->num_rr > 4 || priv->num_tr > 4) {
+ WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
+ return -EOPNOTSUPP;
+ }
+
for (i = 0; i < IMX_MU_CHANS; i++) {
struct imx_mu_con_priv *cp = &priv->con_priv[i];
@@ -768,8 +790,8 @@ static int imx_mu_init_generic(struct imx_mu_priv *priv)
imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
/* Clear any pending RSR */
- for (i = 0; i < IMX_MU_NUM_RR; i++)
- imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
+ for (i = 0; i < priv->num_rr; i++)
+ imx_mu_read(priv, priv->dcfg->xRR + i * 4);
return 0;
}
@@ -874,6 +896,8 @@ static int imx_mu_probe(struct platform_device *pdev)
return ret;
}
+ imx_mu_get_tr_rr(priv);
+
priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
ret = priv->dcfg->init(priv);
--
2.37.1
From: Peng Fan <[email protected]>
Add i.MX95 ELE/V2X MU support, its register layout is same as
i.MX8ULP, but the Parameter registers would show different
TR/RR. Since the driver already supports get TR/RR from Parameter
registers, not hardcoding the number, this patch just add
the compatible entry to reuse i.MX8ULP S4 cfg data.
To use the internal SRAM, need populate its sub-nodes.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/mailbox/imx-mailbox.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 9e89f773d2f9..fff891d40f2f 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -4,6 +4,7 @@
* Copyright 2022 NXP, Peng Fan <[email protected]>
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/firmware/imx/ipc.h>
#include <linux/firmware/imx/s4.h>
@@ -15,6 +16,7 @@
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/suspend.h>
@@ -919,6 +921,8 @@ static int imx_mu_probe(struct platform_device *pdev)
if (ret)
goto disable_clk;
+ of_platform_populate(dev->of_node, NULL, NULL, dev);
+
pm_runtime_enable(dev);
ret = pm_runtime_resume_and_get(dev);
@@ -1031,6 +1035,8 @@ static const struct of_device_id imx_mu_dt_ids[] = {
{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
{ .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
+ { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
+ { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
{ },
--
2.37.1
On Thu, Jan 25, 2024 at 01:20:04PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> There will be changes that init may fail, so adding return value for
> init function.
>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Sascha Hauer <[email protected]>
Sascha
> ---
> drivers/mailbox/imx-mailbox.c | 35 ++++++++++++++++++++++++-----------
> 1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index 656171362fe9..dced4614065f 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -110,7 +110,7 @@ struct imx_mu_dcfg {
> int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
> int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
> int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
> - void (*init)(struct imx_mu_priv *priv);
> + int (*init)(struct imx_mu_priv *priv);
> enum imx_mu_type type;
> u32 xTR; /* Transmit Register0 */
> u32 xRR; /* Receive Register0 */
> @@ -737,7 +737,7 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
> return imx_mu_xlate(mbox, sp);
> }
>
> -static void imx_mu_init_generic(struct imx_mu_priv *priv)
> +static int imx_mu_init_generic(struct imx_mu_priv *priv)
> {
> unsigned int i;
> unsigned int val;
> @@ -757,7 +757,7 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
> priv->mbox.of_xlate = imx_mu_xlate;
>
> if (priv->side_b)
> - return;
> + return 0;
>
> /* Set default MU configuration */
> for (i = 0; i < IMX_MU_xCR_MAX; i++)
> @@ -770,9 +770,11 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
> /* Clear any pending RSR */
> for (i = 0; i < IMX_MU_NUM_RR; i++)
> imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> +
> + return 0;
> }
>
> -static void imx_mu_init_specific(struct imx_mu_priv *priv)
> +static int imx_mu_init_specific(struct imx_mu_priv *priv)
> {
> unsigned int i;
> int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
> @@ -794,12 +796,20 @@ static void imx_mu_init_specific(struct imx_mu_priv *priv)
> /* Set default MU configuration */
> for (i = 0; i < IMX_MU_xCR_MAX; i++)
> imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
> +
> + return 0;
> }
>
> -static void imx_mu_init_seco(struct imx_mu_priv *priv)
> +static int imx_mu_init_seco(struct imx_mu_priv *priv)
> {
> - imx_mu_init_generic(priv);
> + int ret;
> +
> + ret = imx_mu_init_generic(priv);
> + if (ret)
> + return ret;
> priv->mbox.of_xlate = imx_mu_seco_xlate;
> +
> + return 0;
> }
>
> static int imx_mu_probe(struct platform_device *pdev)
> @@ -866,7 +876,11 @@ static int imx_mu_probe(struct platform_device *pdev)
>
> priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
>
> - priv->dcfg->init(priv);
> + ret = priv->dcfg->init(priv);
> + if (ret) {
> + dev_err(dev, "Failed to init MU\n");
> + goto disable_clk;
> + }
>
> spin_lock_init(&priv->xcr_lock);
>
> @@ -878,10 +892,8 @@ static int imx_mu_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, priv);
>
> ret = devm_mbox_controller_register(dev, &priv->mbox);
> - if (ret) {
> - clk_disable_unprepare(priv->clk);
> - return ret;
> - }
> + if (ret)
> + goto disable_clk;
>
> pm_runtime_enable(dev);
>
> @@ -899,6 +911,7 @@ static int imx_mu_probe(struct platform_device *pdev)
>
> disable_runtime_pm:
> pm_runtime_disable(dev);
> +disable_clk:
> clk_disable_unprepare(priv->clk);
> return ret;
> }
>
> --
> 2.37.1
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
On Thu, Jan 25, 2024 at 01:20:05PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> i.MX8ULP, i.MX93 MU has a Parameter register encoded as below:
> BIT: 15 --- 8 | 7 --- 0
> RR_NUM TR_NUM
>
> So to make driver easy to support more variants, get the RR/TR
> registers number from Parameter register.
>
> The patch only adds support the specific MU, such as ELE MU.
> For generic MU, not add support for number larger than 4.
>
> Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Sascha Hauer <[email protected]>
Sascha
> ---
> drivers/mailbox/imx-mailbox.c | 46 ++++++++++++++++++++++++++++++++-----------
> 1 file changed, 35 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index dced4614065f..9e89f773d2f9 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -29,7 +29,9 @@
> #define IMX_MU_S4_CHANS 2
> #define IMX_MU_CHAN_NAME_SIZE 20
>
> -#define IMX_MU_NUM_RR 4
> +#define IMX_MU_V2_PAR_OFF 0x4
> +#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
> +#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
>
> #define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
> #define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
> @@ -93,10 +95,11 @@ struct imx_mu_priv {
> struct clk *clk;
> int irq[IMX_MU_CHANS];
> bool suspend;
> -
> - u32 xcr[IMX_MU_xCR_MAX];
> -
> bool side_b;
> +
> + u32 xcr[IMX_MU_xCR_MAX];
> + u32 num_tr;
> + u32 num_rr;
> };
>
> enum imx_mu_type {
> @@ -264,18 +267,17 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
> static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
> {
> u32 *arg = data;
> + u32 num_tr = priv->num_tr;
> int i, ret;
> u32 xsr;
> - u32 size, max_size, num_tr;
> + u32 size, max_size;
>
> if (priv->dcfg->type & IMX_MU_V2_S4) {
> size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
> max_size = sizeof(struct imx_s4_rpc_msg_max);
> - num_tr = 8;
> } else {
> size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
> max_size = sizeof(struct imx_sc_rpc_msg_max);
> - num_tr = 4;
> }
>
> switch (cp->type) {
> @@ -324,6 +326,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
> int i, ret;
> u32 xsr;
> u32 size, max_size;
> + u32 num_rr = priv->num_rr;
>
> data = (u32 *)priv->msg;
>
> @@ -345,13 +348,13 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
>
> for (i = 1; i < size; i++) {
> ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
> - xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
> + xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
> 5 * USEC_PER_SEC);
> if (ret) {
> dev_err(priv->dev, "timeout read idx %d\n", i);
> return ret;
> }
> - *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> + *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
> }
>
> imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
> @@ -737,11 +740,30 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
> return imx_mu_xlate(mbox, sp);
> }
>
> +static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
> +{
> + u32 val;
> +
> + if (priv->dcfg->type & IMX_MU_V2) {
> + val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
> + priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
> + priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
> + } else {
> + priv->num_tr = 4;
> + priv->num_rr = 4;
> + }
> +}
> +
> static int imx_mu_init_generic(struct imx_mu_priv *priv)
> {
> unsigned int i;
> unsigned int val;
>
> + if (priv->num_rr > 4 || priv->num_tr > 4) {
> + WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
> + return -EOPNOTSUPP;
> + }
> +
> for (i = 0; i < IMX_MU_CHANS; i++) {
> struct imx_mu_con_priv *cp = &priv->con_priv[i];
>
> @@ -768,8 +790,8 @@ static int imx_mu_init_generic(struct imx_mu_priv *priv)
> imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
>
> /* Clear any pending RSR */
> - for (i = 0; i < IMX_MU_NUM_RR; i++)
> - imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> + for (i = 0; i < priv->num_rr; i++)
> + imx_mu_read(priv, priv->dcfg->xRR + i * 4);
>
> return 0;
> }
> @@ -874,6 +896,8 @@ static int imx_mu_probe(struct platform_device *pdev)
> return ret;
> }
>
> + imx_mu_get_tr_rr(priv);
> +
> priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
>
> ret = priv->dcfg->init(priv);
>
> --
> 2.37.1
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Peng,
Am Donnerstag, 25. Januar 2024, 06:20:04 CET schrieb Peng Fan (OSS):
> From: Peng Fan <[email protected]>
>
> There will be changes that init may fail, so adding return value for
> init function.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> drivers/mailbox/imx-mailbox.c | 35 ++++++++++++++++++++++++-----------
> 1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
> index 656171362fe9..dced4614065f 100644
> --- a/drivers/mailbox/imx-mailbox.c
> +++ b/drivers/mailbox/imx-mailbox.c
> @@ -110,7 +110,7 @@ struct imx_mu_dcfg {
> int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void
> *data); int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
> int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); - void
> (*init)(struct imx_mu_priv *priv);
> + int (*init)(struct imx_mu_priv *priv);
> enum imx_mu_type type;
> u32 xTR; /* Transmit Register0 */
> u32 xRR; /* Receive Register0 */
> @@ -737,7 +737,7 @@ static struct mbox_chan *imx_mu_seco_xlate(struct
> mbox_controller *mbox, return imx_mu_xlate(mbox, sp);
> }
>
> -static void imx_mu_init_generic(struct imx_mu_priv *priv)
> +static int imx_mu_init_generic(struct imx_mu_priv *priv)
> {
> unsigned int i;
> unsigned int val;
> @@ -757,7 +757,7 @@ static void imx_mu_init_generic(struct imx_mu_priv
> *priv) priv->mbox.of_xlate = imx_mu_xlate;
>
> if (priv->side_b)
> - return;
> + return 0;
>
> /* Set default MU configuration */
> for (i = 0; i < IMX_MU_xCR_MAX; i++)
> @@ -770,9 +770,11 @@ static void imx_mu_init_generic(struct imx_mu_priv
> *priv) /* Clear any pending RSR */
> for (i = 0; i < IMX_MU_NUM_RR; i++)
> imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> +
> + return 0;
> }
>
> -static void imx_mu_init_specific(struct imx_mu_priv *priv)
> +static int imx_mu_init_specific(struct imx_mu_priv *priv)
> {
> unsigned int i;
> int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS :
> IMX_MU_SCU_CHANS; @@ -794,12 +796,20 @@ static void
> imx_mu_init_specific(struct imx_mu_priv *priv) /* Set default MU
> configuration */
> for (i = 0; i < IMX_MU_xCR_MAX; i++)
> imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
> +
> + return 0;
> }
>
> -static void imx_mu_init_seco(struct imx_mu_priv *priv)
> +static int imx_mu_init_seco(struct imx_mu_priv *priv)
> {
> - imx_mu_init_generic(priv);
> + int ret;
> +
> + ret = imx_mu_init_generic(priv);
> + if (ret)
> + return ret;
> priv->mbox.of_xlate = imx_mu_seco_xlate;
> +
> + return 0;
> }
>
> static int imx_mu_probe(struct platform_device *pdev)
> @@ -866,7 +876,11 @@ static int imx_mu_probe(struct platform_device *pdev)
>
> priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
>
> - priv->dcfg->init(priv);
> + ret = priv->dcfg->init(priv);
> + if (ret) {
> + dev_err(dev, "Failed to init MU\n");
As this is during probe, I rather use dev_err_probe right away. Even if dcfg-
>init won't return -EPROBE_DEFER for now.
Best regards,
Alexander
> + goto disable_clk;
> + }
>
> spin_lock_init(&priv->xcr_lock);
>
> @@ -878,10 +892,8 @@ static int imx_mu_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, priv);
>
> ret = devm_mbox_controller_register(dev, &priv->mbox);
> - if (ret) {
> - clk_disable_unprepare(priv->clk);
> - return ret;
> - }
> + if (ret)
> + goto disable_clk;
>
> pm_runtime_enable(dev);
>
> @@ -899,6 +911,7 @@ static int imx_mu_probe(struct platform_device *pdev)
>
> disable_runtime_pm:
> pm_runtime_disable(dev);
> +disable_clk:
> clk_disable_unprepare(priv->clk);
> return ret;
> }
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
> Subject: Re: [PATCH v4 2/4] mailbox: imx: support return value of init
>
> Hi Peng,
>
> Am Donnerstag, 25. Januar 2024, 06:20:04 CET schrieb Peng Fan (OSS):
> > From: Peng Fan <[email protected]>
> >
> > There will be changes that init may fail, so adding return value for
> > init function.
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> > drivers/mailbox/imx-mailbox.c | 35
> > ++++++++++++++++++++++++-----------
> > 1 file changed, 24 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/mailbox/imx-mailbox.c
> > b/drivers/mailbox/imx-mailbox.c index 656171362fe9..dced4614065f
> > 100644
> > --- a/drivers/mailbox/imx-mailbox.c
> > +++ b/drivers/mailbox/imx-mailbox.c
> > @@ -110,7 +110,7 @@ struct imx_mu_dcfg {
> > int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void
> > *data); int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
> > int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); -
> void
> > (*init)(struct imx_mu_priv *priv);
> > + int (*init)(struct imx_mu_priv *priv);
> > enum imx_mu_type type;
> > u32 xTR; /* Transmit Register0 */
> > u32 xRR; /* Receive Register0 */
> > @@ -737,7 +737,7 @@ static struct mbox_chan
> *imx_mu_seco_xlate(struct
> > mbox_controller *mbox, return imx_mu_xlate(mbox, sp); }
> >
> > -static void imx_mu_init_generic(struct imx_mu_priv *priv)
> > +static int imx_mu_init_generic(struct imx_mu_priv *priv)
> > {
> > unsigned int i;
> > unsigned int val;
> > @@ -757,7 +757,7 @@ static void imx_mu_init_generic(struct
> imx_mu_priv
> > *priv) priv->mbox.of_xlate = imx_mu_xlate;
> >
> > if (priv->side_b)
> > - return;
> > + return 0;
> >
> > /* Set default MU configuration */
> > for (i = 0; i < IMX_MU_xCR_MAX; i++) @@ -770,9 +770,11 @@ static
> > void imx_mu_init_generic(struct imx_mu_priv
> > *priv) /* Clear any pending RSR */
> > for (i = 0; i < IMX_MU_NUM_RR; i++)
> > imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
> > +
> > + return 0;
> > }
> >
> > -static void imx_mu_init_specific(struct imx_mu_priv *priv)
> > +static int imx_mu_init_specific(struct imx_mu_priv *priv)
> > {
> > unsigned int i;
> > int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ?
> IMX_MU_S4_CHANS :
> > IMX_MU_SCU_CHANS; @@ -794,12 +796,20 @@ static void
> > imx_mu_init_specific(struct imx_mu_priv *priv) /* Set default MU
> > configuration */
> > for (i = 0; i < IMX_MU_xCR_MAX; i++)
> > imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
> > +
> > + return 0;
> > }
> >
> > -static void imx_mu_init_seco(struct imx_mu_priv *priv)
> > +static int imx_mu_init_seco(struct imx_mu_priv *priv)
> > {
> > - imx_mu_init_generic(priv);
> > + int ret;
> > +
> > + ret = imx_mu_init_generic(priv);
> > + if (ret)
> > + return ret;
> > priv->mbox.of_xlate = imx_mu_seco_xlate;
> > +
> > + return 0;
> > }
> >
> > static int imx_mu_probe(struct platform_device *pdev) @@ -866,7
> > +876,11 @@ static int imx_mu_probe(struct platform_device *pdev)
> >
> > priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
> >
> > - priv->dcfg->init(priv);
> > + ret = priv->dcfg->init(priv);
> > + if (ret) {
> > + dev_err(dev, "Failed to init MU\n");
>
> As this is during probe, I rather use dev_err_probe right away. Even if dcfg-
> >init won't return -EPROBE_DEFER for now.
Let's defer this action until init could return -EPROBE_DEFER.
Thanks,
Peng.
>
> Best regards,
> Alexander
>
> > + goto disable_clk;
> > + }
> >
> > spin_lock_init(&priv->xcr_lock);
> >
> > @@ -878,10 +892,8 @@ static int imx_mu_probe(struct platform_device
> *pdev)
> > platform_set_drvdata(pdev, priv);
> >
> > ret = devm_mbox_controller_register(dev, &priv->mbox);
> > - if (ret) {
> > - clk_disable_unprepare(priv->clk);
> > - return ret;
> > - }
> > + if (ret)
> > + goto disable_clk;
> >
> > pm_runtime_enable(dev);
> >
> > @@ -899,6 +911,7 @@ static int imx_mu_probe(struct platform_device
> > *pdev)
> >
> > disable_runtime_pm:
> > pm_runtime_disable(dev);
> > +disable_clk:
> > clk_disable_unprepare(priv->clk);
> > return ret;
> > }
>
>
> --
> TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht M?nchen, HRB 105018
> Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
> http://www.t/
> q-
> group.com%2F&data=05%7C02%7Cpeng.fan%40nxp.com%7C77ae5cd17000
> 42c9a4f008dc1d85b1ba%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7
> C0%7C638417707259707963%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7
> C%7C%7C&sdata=OuTmDvQM0MYTBv%2BhwtQNPgd%2BuA9cMKoBIHe%2Fi
> Zl9Iu4%3D&reserved=0
>
On Thu, Jan 25, 2024 at 01:20:03PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string.
> And some MUs has internal RAMs for SCMI shared buffer usage.
Please restrict the SRAM child none to whatever the "some MUs" are that
actually have it.
Thanks,
Conor.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> .../devicetree/bindings/mailbox/fsl,mu.yaml | 52 +++++++++++++++++++++-
> 1 file changed, 50 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> index 12e7a7d536a3..86759831b24a 100644
> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> @@ -29,10 +29,14 @@ properties:
> - const: fsl,imx8ulp-mu
> - const: fsl,imx8-mu-scu
> - const: fsl,imx8-mu-seco
> - - const: fsl,imx93-mu-s4
> - const: fsl,imx8ulp-mu-s4
> + - const: fsl,imx93-mu-s4
> + - const: fsl,imx95-mu-ele
> + - const: fsl,imx95-mu-v2x
> - items:
> - - const: fsl,imx93-mu
> + - enum:
> + - fsl,imx93-mu
> + - fsl,imx95-mu
> - const: fsl,imx8ulp-mu
> - items:
> - enum:
> @@ -95,6 +99,19 @@ properties:
> power-domains:
> maxItems: 1
>
> + ranges: true
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> +patternProperties:
> + "^sram@[a-f0-9]+":
> + $ref: /schemas/sram/sram.yaml#
> + unevaluatedProperties: false
> +
> required:
> - compatible
> - reg
> @@ -134,3 +151,34 @@ examples:
> interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> #mbox-cells = <2>;
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + mu2: mailbox@445b0000 {
> + compatible = "fsl,imx95-mu", "fsl,imx8ulp-mu";
> + reg = <0x445b0000 0x10000>;
> + ranges;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + #mbox-cells = <2>;
> +
> + sram@445b1000 {
> + compatible = "mmio-sram";
> + reg = <0x445b1000 0x400>;
> + ranges = <0x0 0x445b1000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + scmi_buf0: scmi-sram-section@0 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x80>;
> + };
> +
> + scmi_buf1: scmi-sram-section@80 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x80 0x80>;
> + };
> + };
> + };
>
> --
> 2.37.1
>
> Subject: Re: [PATCH v4 1/4] dt-bindings: mailbox: fsl,mu: add i.MX95
> Generic/ELE/V2X MU compatible
>
> On Thu, Jan 25, 2024 at 01:20:03PM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible
> string.
> > And some MUs has internal RAMs for SCMI shared buffer usage.
>
> Please restrict the SRAM child none to whatever the "some MUs" are that
> actually have it.
Ok, will update it in V5.
Thanks,
Peng.
>
> Thanks,
> Conor.
>
> >
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> > .../devicetree/bindings/mailbox/fsl,mu.yaml | 52
> +++++++++++++++++++++-
> > 1 file changed, 50 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> > b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> > index 12e7a7d536a3..86759831b24a 100644
> > --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> > +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
> > @@ -29,10 +29,14 @@ properties:
> > - const: fsl,imx8ulp-mu
> > - const: fsl,imx8-mu-scu
> > - const: fsl,imx8-mu-seco
> > - - const: fsl,imx93-mu-s4
> > - const: fsl,imx8ulp-mu-s4
> > + - const: fsl,imx93-mu-s4
> > + - const: fsl,imx95-mu-ele
> > + - const: fsl,imx95-mu-v2x
> > - items:
> > - - const: fsl,imx93-mu
> > + - enum:
> > + - fsl,imx93-mu
> > + - fsl,imx95-mu
> > - const: fsl,imx8ulp-mu
> > - items:
> > - enum:
> > @@ -95,6 +99,19 @@ properties:
> > power-domains:
> > maxItems: 1
> >
> > + ranges: true
> > +
> > + '#address-cells':
> > + const: 1
> > +
> > + '#size-cells':
> > + const: 1
> > +
> > +patternProperties:
> > + "^sram@[a-f0-9]+":
> > + $ref: /schemas/sram/sram.yaml#
> > + unevaluatedProperties: false
> > +
> > required:
> > - compatible
> > - reg
> > @@ -134,3 +151,34 @@ examples:
> > interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> > #mbox-cells = <2>;
> > };
> > +
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + mu2: mailbox@445b0000 {
> > + compatible = "fsl,imx95-mu", "fsl,imx8ulp-mu";
> > + reg = <0x445b0000 0x10000>;
> > + ranges;
> > + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + #mbox-cells = <2>;
> > +
> > + sram@445b1000 {
> > + compatible = "mmio-sram";
> > + reg = <0x445b1000 0x400>;
> > + ranges = <0x0 0x445b1000 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + scmi_buf0: scmi-sram-section@0 {
> > + compatible = "arm,scmi-shmem";
> > + reg = <0x0 0x80>;
> > + };
> > +
> > + scmi_buf1: scmi-sram-section@80 {
> > + compatible = "arm,scmi-shmem";
> > + reg = <0x80 0x80>;
> > + };
> > + };
> > + };
> >
> > --
> > 2.37.1
> >