The "msg_addr" variable is u64. However, the "aligned_offset" is an
unsigned int. This means that when the code does:
msg_addr &= ~aligned_offset;
it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN()
to do the alignment instead.
Cc: [email protected]
Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
Signed-off-by: Dan Carpenter <[email protected]>
Reviewed-by: Niklas Cassel <[email protected]>
---
v4: Add stable and r-b from Niklas
v3: Use ALIGN_DOWN()
v2: fix typo in commit message
drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 5befed2dc02b..51679c6702cf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
}
aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
- msg_addr &= ~aligned_offset;
+ msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
epc->mem->window.page_size);
if (ret)
--
2.43.0
I recently changed the alignment code in dw_pcie_ep_raise_msix_irq().
The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match
as well, just for consistency. (No effect on runtime, just a cleanup).
Signed-off-by: Dan Carpenter <[email protected]>
---
v4: style improvements
v3: use ALIGN_DOWN()
v2: new patch
drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 51679c6702cf..d2de41f02a77 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -482,9 +482,10 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
reg = ep_func->msi_cap + PCI_MSI_DATA_32;
msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
}
- aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
- msg_addr = ((u64)msg_addr_upper) << 32 |
- (msg_addr_lower & ~aligned_offset);
+ msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
+
+ aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
+ msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
epc->mem->window.page_size);
if (ret)
--
2.43.0
On Wed, 24 Jan 2024, Dan Carpenter wrote:
> I recently changed the alignment code in dw_pcie_ep_raise_msix_irq().
> The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match
> as well, just for consistency. (No effect on runtime, just a cleanup).
>
> Signed-off-by: Dan Carpenter <[email protected]>
> ---
> v4: style improvements
> v3: use ALIGN_DOWN()
> v2: new patch
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 51679c6702cf..d2de41f02a77 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -482,9 +482,10 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> reg = ep_func->msi_cap + PCI_MSI_DATA_32;
> msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> }
> - aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
> - msg_addr = ((u64)msg_addr_upper) << 32 |
> - (msg_addr_lower & ~aligned_offset);
> + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
> +
> + aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
After you've added the #include in 1/2, for both patches:
Reviewed-by: Ilpo J?rvinen <[email protected]>
--
i.
On Wed, 24 Jan 2024, Dan Carpenter wrote:
> The "msg_addr" variable is u64. However, the "aligned_offset" is an
> unsigned int. This means that when the code does:
>
> msg_addr &= ~aligned_offset;
>
> it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN()
> to do the alignment instead.
>
> Cc: [email protected]
> Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
> Signed-off-by: Dan Carpenter <[email protected]>
> Reviewed-by: Niklas Cassel <[email protected]>
> ---
> v4: Add stable and r-b from Niklas
> v3: Use ALIGN_DOWN()
> v2: fix typo in commit message
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 5befed2dc02b..51679c6702cf 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> - msg_addr &= ~aligned_offset;
> + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
> ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> epc->mem->window.page_size);
> if (ret)
Hi Dan,
You should also add the include for it:
#include <linux/align.h>
--
i.
On Wed, Jan 24, 2024 at 06:03:51PM +0300, Dan Carpenter wrote:
> I recently changed the alignment code in dw_pcie_ep_raise_msix_irq().
> The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match
> as well, just for consistency. (No effect on runtime, just a cleanup).
>
> Signed-off-by: Dan Carpenter <[email protected]>
> ---
> v4: style improvements
> v3: use ALIGN_DOWN()
> v2: new patch
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 51679c6702cf..d2de41f02a77 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -482,9 +482,10 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> reg = ep_func->msi_cap + PCI_MSI_DATA_32;
> msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> }
> - aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
> - msg_addr = ((u64)msg_addr_upper) << 32 |
> - (msg_addr_lower & ~aligned_offset);
> + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
> +
> + aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
> ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> epc->mem->window.page_size);
> if (ret)
> --
> 2.43.0
>
Reviewed-by: Niklas Cassel <[email protected]>
(Feel free to keep my R-b tags even if you send out a new version with the
#include requested by Ilpo.)
On Wed, Jan 24, 2024 at 06:01:42PM +0300, Dan Carpenter wrote:
> The "msg_addr" variable is u64. However, the "aligned_offset" is an
> unsigned int. This means that when the code does:
>
> msg_addr &= ~aligned_offset;
>
> it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN()
> to do the alignment instead.
>
> Cc: [email protected]
> Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")
> Signed-off-by: Dan Carpenter <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
> Reviewed-by: Niklas Cassel <[email protected]>
> ---
> v4: Add stable and r-b from Niklas
> v3: Use ALIGN_DOWN()
> v2: fix typo in commit message
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 5befed2dc02b..51679c6702cf 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
> }
>
> aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> - msg_addr &= ~aligned_offset;
> + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
> ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> epc->mem->window.page_size);
> if (ret)
> --
> 2.43.0
>
--
மணிவண்ணன் சதாசிவம்
On Wed, Jan 24, 2024 at 06:03:51PM +0300, Dan Carpenter wrote:
> I recently changed the alignment code in dw_pcie_ep_raise_msix_irq().
> The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match
> as well, just for consistency. (No effect on runtime, just a cleanup).
>
> Signed-off-by: Dan Carpenter <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
> ---
> v4: style improvements
> v3: use ALIGN_DOWN()
> v2: new patch
>
> drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 51679c6702cf..d2de41f02a77 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -482,9 +482,10 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
> reg = ep_func->msi_cap + PCI_MSI_DATA_32;
> msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg);
> }
> - aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
> - msg_addr = ((u64)msg_addr_upper) << 32 |
> - (msg_addr_lower & ~aligned_offset);
> + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower;
> +
> + aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
> + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
> ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
> epc->mem->window.page_size);
> if (ret)
> --
> 2.43.0
>
--
மணிவண்ணன் சதாசிவம்