2024-02-02 01:49:26

by Mike Tipton

Subject: [PATCH 0/2] interconnect: qcom: ACV enable_mask fixes

A couple small fixes for targets using incorrect ACV enable_masks.

Mike Tipton (2):
interconnect: qcom: sm8650: Use correct ACV enable_mask
interconnect: qcom: x1e80100: Add missing ACV enable_mask

drivers/interconnect/qcom/sm8650.c | 2 +-
drivers/interconnect/qcom/x1e80100.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)

--
2.17.1

2024-02-02 01:57:29

by Mike Tipton

Subject: [PATCH 1/2] interconnect: qcom: sm8650: Use correct ACV enable_mask

The ACV enable_mask is historically BIT(3), but it's BIT(0) on this
target. Fix it.

Fixes: c062bcab5924 ("interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC")
Signed-off-by: Mike Tipton <[email protected]>
---
drivers/interconnect/qcom/sm8650.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
index b83de54577b6..b962e6c233ef 100644
--- a/drivers/interconnect/qcom/sm8650.c
+++ b/drivers/interconnect/qcom/sm8650.c
@@ -1160,7 +1160,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {

static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
- .enable_mask = BIT(3),
+ .enable_mask = BIT(0),
.num_nodes = 1,
.nodes = { &ebi },
};
--
2.17.1

2024-02-02 01:58:16

by Mike Tipton

Subject: [PATCH 2/2] interconnect: qcom: x1e80100: Add missing ACV enable_mask

The ACV BCM is voted using bitmasks. Add the proper mask for this
target.

Fixes: 9f196772841e ("interconnect: qcom: Add X1E80100 interconnect provider driver")
Signed-off-by: Mike Tipton <[email protected]>
---
drivers/interconnect/qcom/x1e80100.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
index 5b2de9c3a1d6..281295a9a077 100644
--- a/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@ -1372,6 +1372,7 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = {

static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
+ .enable_mask = BIT(3),
.num_nodes = 1,
.nodes = { &ebi },
};
--
2.17.1

2024-02-02 11:30:00

by Konrad Dybcio

Subject: Re: [PATCH 1/2] interconnect: qcom: sm8650: Use correct ACV enable_mask

On 2.02.2024 02:48, Mike Tipton wrote:
> The ACV enable_mask is historically BIT(3), but it's BIT(0) on this
> target. Fix it.
>
> Fixes: c062bcab5924 ("interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC")
> Signed-off-by: Mike Tipton <[email protected]>
> ---

Downstream agrees

Reviewed-by: Konrad Dybcio <[email protected]>

Konrad

2024-02-02 11:30:17

by Konrad Dybcio

Subject: Re: [PATCH 2/2] interconnect: qcom: x1e80100: Add missing ACV enable_mask

On 2.02.2024 02:48, Mike Tipton wrote:
> The ACV BCM is voted using bitmasks. Add the proper mask for this
> target.
>
> Fixes: 9f196772841e ("interconnect: qcom: Add X1E80100 interconnect provider driver")
> Signed-off-by: Mike Tipton <[email protected]>
> ---

Reviewed-by: Konrad Dybcio <[email protected]>

Konrad

2024-02-02 16:57:55

by Abel Vesa

Subject: Re: [PATCH 2/2] interconnect: qcom: x1e80100: Add missing ACV enable_mask

On 24-02-01 17:48:06, Mike Tipton wrote:
> The ACV BCM is voted using bitmasks. Add the proper mask for this
> target.
>
> Fixes: 9f196772841e ("interconnect: qcom: Add X1E80100 interconnect provider driver")
> Signed-off-by: Mike Tipton <[email protected]>

Tested-by: Abel Vesa <[email protected]>

> ---
> drivers/interconnect/qcom/x1e80100.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c
> index 5b2de9c3a1d6..281295a9a077 100644
> --- a/drivers/interconnect/qcom/x1e80100.c
> +++ b/drivers/interconnect/qcom/x1e80100.c
> @@ -1372,6 +1372,7 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = {
>
> static struct qcom_icc_bcm bcm_acv = {
> .name = "ACV",
> + .enable_mask = BIT(3),
> .num_nodes = 1,
> .nodes = { &ebi },
> };
> --
> 2.17.1
>

2024-02-03 14:49:36

by Neil Armstrong

Subject: Re: [PATCH 1/2] interconnect: qcom: sm8650: Use correct ACV enable_mask

On 02/02/2024 02:48, Mike Tipton wrote:
> The ACV enable_mask is historically BIT(3), but it's BIT(0) on this
> target. Fix it.
>
> Fixes: c062bcab5924 ("interconnect: qcom: introduce RPMh Network-On-Chip Interconnect on SM8650 SoC")
> Signed-off-by: Mike Tipton <[email protected]>
> ---
> drivers/interconnect/qcom/sm8650.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom/sm8650.c
> index b83de54577b6..b962e6c233ef 100644
> --- a/drivers/interconnect/qcom/sm8650.c
> +++ b/drivers/interconnect/qcom/sm8650.c
> @@ -1160,7 +1160,7 @@ static struct qcom_icc_node qns_gemnoc_sf = {
>
> static struct qcom_icc_bcm bcm_acv = {
> .name = "ACV",
> - .enable_mask = BIT(3),
> + .enable_mask = BIT(0),
> .num_nodes = 1,
> .nodes = { &ebi },
> };

Indeed it changed in the meantime


Reviewed-by: Neil Armstrong <[email protected]>