As per the S905X2 datasheet add missing cache information to the Amlogic
G12A SoC.
- Each Cortex-A53 core has 32KB of L1 instruction cache available and
32KB of L1 data cache available.
- Along with 512KB Unified L2 cache.
To improve system performance.
Signed-off-by: Anand Moon <[email protected]>
---
No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
nence used the same cache size as S905 and S905X.
---
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 543e70669df5..6e1e3a3f5f18 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -17,6 +17,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -26,6 +32,12 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -35,6 +47,12 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -44,6 +62,12 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -52,6 +76,9 @@ l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x7d000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
--
2.43.0
Hi!
You missed the AXG family with the Cortex-A53 CPU. The datasheet does
not provide information on cache sizes. Given that the A113X/A113D are
equipped with the Arm Cortex-A53 processor, it is assumed they use the
same cache size as the S905/S905X/S905X2 models.
05/02/2024 20.19, Anand Moon wrote:
> As per the S905X2 datasheet add missing cache information to the Amlogic
> G12A SoC.
>
> - Each Cortex-A53 core has 32KB of L1 instruction cache available and
> 32KB of L1 data cache available.
> - Along with 512KB Unified L2 cache.
>
> To improve system performance.
>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
> nence used the same cache size as S905 and S905X.
> ---
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> index 543e70669df5..6e1e3a3f5f18 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -17,6 +17,12 @@ cpu0: cpu@0 {
> compatible = "arm,cortex-a53";
> reg = <0x0 0x0>;
> enable-method = "psci";
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> next-level-cache = <&l2>;
> #cooling-cells = <2>;
> };
> @@ -26,6 +32,12 @@ cpu1: cpu@1 {
> compatible = "arm,cortex-a53";
> reg = <0x0 0x1>;
> enable-method = "psci";
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> next-level-cache = <&l2>;
> #cooling-cells = <2>;
> };
> @@ -35,6 +47,12 @@ cpu2: cpu@2 {
> compatible = "arm,cortex-a53";
> reg = <0x0 0x2>;
> enable-method = "psci";
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> next-level-cache = <&l2>;
> #cooling-cells = <2>;
> };
> @@ -44,6 +62,12 @@ cpu3: cpu@3 {
> compatible = "arm,cortex-a53";
> reg = <0x0 0x3>;
> enable-method = "psci";
> + d-cache-line-size = <32>;
> + d-cache-size = <0x8000>;
> + d-cache-sets = <32>;
> + i-cache-line-size = <32>;
> + i-cache-size = <0x8000>;
> + i-cache-sets = <32>;
> next-level-cache = <&l2>;
> #cooling-cells = <2>;
> };
> @@ -52,6 +76,9 @@ l2: l2-cache0 {
> compatible = "cache";
> cache-level = <2>;
> cache-unified;
> + cache-size = <0x7d000>; /* L2. 512 KB */
> + cache-line-size = <64>;
> + cache-sets = <512>;
> };
> };
>
Best regards,
--
Viacheslav Bocharov <[email protected]>
> On 6 Feb 2024, at 11:48 am, Viacheslav <[email protected]> wrote:
>
> You missed the AXG family with the Cortex-A53 CPU. The datasheet does not provide information on cache sizes. Given that the A113X/A113D are equipped with the Arm Cortex-A53 processor, it is assumed they use the same cache size as the S905/S905X/S905X2 models.
GXM is also missing, and also using A53 cores.
Christian
> 05/02/2024 20.19, Anand Moon wrote:
>> As per the S905X2 datasheet add missing cache information to the Amlogic
>> G12A SoC.
>> - Each Cortex-A53 core has 32KB of L1 instruction cache available and
>> 32KB of L1 data cache available.
>> - Along with 512KB Unified L2 cache.
>> To improve system performance.
>> Signed-off-by: Anand Moon <[email protected]>
>> ---
>> No public dataheet available, since S905X2 support Arm Cortex-A53 cpu
>> nence used the same cache size as S905 and S905X.
>> ---
>> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 +++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> index 543e70669df5..6e1e3a3f5f18 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>> @@ -17,6 +17,12 @@ cpu0: cpu@0 {
>> compatible = "arm,cortex-a53";
>> reg = <0x0 0x0>;
>> enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>> next-level-cache = <&l2>;
>> #cooling-cells = <2>;
>> };
>> @@ -26,6 +32,12 @@ cpu1: cpu@1 {
>> compatible = "arm,cortex-a53";
>> reg = <0x0 0x1>;
>> enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>> next-level-cache = <&l2>;
>> #cooling-cells = <2>;
>> };
>> @@ -35,6 +47,12 @@ cpu2: cpu@2 {
>> compatible = "arm,cortex-a53";
>> reg = <0x0 0x2>;
>> enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>> next-level-cache = <&l2>;
>> #cooling-cells = <2>;
>> };
>> @@ -44,6 +62,12 @@ cpu3: cpu@3 {
>> compatible = "arm,cortex-a53";
>> reg = <0x0 0x3>;
>> enable-method = "psci";
>> + d-cache-line-size = <32>;
>> + d-cache-size = <0x8000>;
>> + d-cache-sets = <32>;
>> + i-cache-line-size = <32>;
>> + i-cache-size = <0x8000>;
>> + i-cache-sets = <32>;
>> next-level-cache = <&l2>;
>> #cooling-cells = <2>;
>> };
>> @@ -52,6 +76,9 @@ l2: l2-cache0 {
>> compatible = "cache";
>> cache-level = <2>;
>> cache-unified;
>> + cache-size = <0x7d000>; /* L2. 512 KB */
>> + cache-line-size = <64>;
>> + cache-sets = <512>;
>> };
>> };
>>
>
>
> Best regards,
> --
> Viacheslav Bocharov <[email protected]>
>
> _______________________________________________
> linux-amlogic mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
Hi Christian / Viacheslav,
On Tue, 6 Feb 2024 at 13:23, Christian Hewitt
<[email protected]> wrote:
>
> > On 6 Feb 2024, at 11:48 am, Viacheslav <[email protected]> wrote:
> >
> > You missed the AXG family with the Cortex-A53 CPU. The datasheet does not provide information on cache sizes. Given that the A113X/A113D are equipped with the Arm Cortex-A53 processor, it is assumed they use the same cache size as the S905/S905X/S905X2 models.
>
> GXM is also missing, and also using A53 cores.
>
> Christian
>
This patch is valid if the hardware supports perf PMU events, see below
I dont have the hardware.
Best way to let the Amlogic SoC members comment on the CPU L1/ /L2 cache size.
But with the lack of pref PMU events we cannot test this feature.
alarm@archl-librecm ~]$ sudo perf list
List of pre-defined events (to be used in -e or -M):
branch-instructions OR branches [Hardware event]
branch-misses [Hardware event]
bus-cycles [Hardware event]
cache-misses [Hardware event]
cache-references [Hardware event]
cpu-cycles OR cycles [Hardware event]
instructions [Hardware event]
alignment-faults [Software event]
bpf-output [Software event]
cgroup-switches [Software event]
context-switches OR cs [Software event]
cpu-clock [Software event]
cpu-migrations OR migrations [Software event]
dummy [Software event]
emulation-faults [Software event]
major-faults [Software event]
minor-faults [Software event]
page-faults OR faults [Software event]
task-clock [Software event]
duration_time [Tool event]
user_time [Tool event]
system_time [Tool event]
armv8_cortex_a53:
L1-dcache-loads OR armv8_cortex_a53/L1-dcache-loads/
L1-dcache-load-misses OR armv8_cortex_a53/L1-dcache-load-misses/
L1-dcache-prefetch-misses OR armv8_cortex_a53/L1-dcache-prefetch-misses/
L1-icache-loads OR armv8_cortex_a53/L1-icache-loads/
L1-icache-load-misses OR armv8_cortex_a53/L1-icache-load-misses/
dTLB-load-misses OR armv8_cortex_a53/dTLB-load-misses/
iTLB-load-misses OR armv8_cortex_a53/iTLB-load-misses/
branch-loads OR armv8_cortex_a53/branch-loads/
branch-load-misses OR armv8_cortex_a53/branch-load-misses/
node-loads OR armv8_cortex_a53/node-loads/
node-stores OR armv8_cortex_a53/node-stores/
br_immed_retired OR armv8_cortex_a53/br_immed_retired/[Kernel PMU event]
br_mis_pred OR armv8_cortex_a53/br_mis_pred/ [Kernel PMU event]
br_pred OR armv8_cortex_a53/br_pred/ [Kernel PMU event]
bus_access OR armv8_cortex_a53/bus_access/ [Kernel PMU event]
bus_cycles OR armv8_cortex_a53/bus_cycles/ [Kernel PMU event]
cid_write_retired OR armv8_cortex_a53/cid_write_retired/[Kernel PMU event]
cpu_cycles OR armv8_cortex_a53/cpu_cycles/ [Kernel PMU event]
exc_return OR armv8_cortex_a53/exc_return/ [Kernel PMU event]
> >
> > Best regards,
> > --
> > Viacheslav Bocharov <[email protected]>
> >
> > _______________________________________________
> > linux-amlogic mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-amlogic
>
>