The series implements CPU clock support for Exynos850, adds CPU CMUs to
the clock driver and enables those in dts. This is the first step
towards cpufreq implementation.
If possible, all patches should go through Krzysztof's tree. As
inter-series dependencies go:
* All driver changes (patch 02..14) must be taken together following
the order established in this series
* Patch 15 (dts changes) depends on patch 01 (bindings additions)
* Patch 14 (driver changes) depends on patch 01 (bindings additions)
The series was tested on E850-96 board, via DebugFS with
CLOCK_ALLOW_WRITE_DEBUGFS enabled, by setting different CPU clock rates,
like this:
# cd /sys/kernel/debug/clk/cluster0_clk/
# cat clk_rate
1053000000
# echo 10000000 > clk_rate
# cat clk_rate
130000000
Of course, DVFS/cpufreq is not implemented yet, so the CPU can't be
overclocked too much right now, and the cpufreq interface is not
available too. As per the TRM, the CPU operates at a voltage level of
0.65 V, 0.75 V, 0.85 V and 1.05 V. When the voltage is 0.85 V, A55
quad-core operates at 1.6 GHz and CoreSight at 200 MHz.
To check the actual frequency, the "perf" tool was used:
# perf stat sleep 1
And to check that on a particular CPU core:
# taskset -c 4 perf stat sleep 1
Some takeaways:
* Max functional frequency right now is 1.586 GHz
* 1.742 GHz or more leads to the system freeze, as it requires
more voltage to be operational
* Max possible frequency: 2.210 GHz
* The lowest possible frequency: 130 MHz
* Default boot up frequency: 1.053 GHz
Changes in v2:
- Removed confusing "breakup by patch" list from patch #0 commit message
- Dropped the patch for making clk.h a single included header
- Rebased the series on top of the latest linux-next
Sam Protsenko (15):
dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
clk: samsung: Improve clk-cpu.c style
clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
clk: samsung: Reduce params count in exynos_register_cpu_clock()
clk: samsung: Use single CPU clock notifier callback for all chips
clk: samsung: Group CPU clock functions by chip
clk: samsung: Pass actual CPU clock registers base to CPU_CLK()
clk: samsung: Pass register layout type explicitly to CLK_CPU()
clk: samsung: Keep CPU clock chip specific data in a dedicated struct
clk: samsung: Keep register offsets in chip specific structure
clk: samsung: Pass mask to wait_until_mux_stable()
clk: samsung: Add CPU clock support for Exynos850
clk: samsung: Implement manual PLL control for ARM64 SoCs
clk: samsung: exynos850: Add CMU_CPUCL0 and CMU_CPUCL1
arm64: dts: exynos: Add CPU clocks for Exynos850
.../clock/samsung,exynos850-clock.yaml | 42 ++
arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +
drivers/clk/samsung/clk-cpu.c | 562 +++++++++++++-----
drivers/clk/samsung/clk-cpu.h | 53 +-
drivers/clk/samsung/clk-exynos-arm64.c | 44 +-
drivers/clk/samsung/clk-exynos3250.c | 2 +-
drivers/clk/samsung/clk-exynos4.c | 9 +-
drivers/clk/samsung/clk-exynos5250.c | 5 +-
drivers/clk/samsung/clk-exynos5420.c | 16 +-
drivers/clk/samsung/clk-exynos5433.c | 10 +-
drivers/clk/samsung/clk-exynos850.c | 440 +++++++++++++-
drivers/clk/samsung/clk.h | 9 +-
include/dt-bindings/clock/exynos850.h | 54 ++
13 files changed, 1040 insertions(+), 232 deletions(-)
--
2.39.2
Document CPU clock management unit compatibles and add corresponding
clock indices. Exynos850 has two CPU clusters (CL0 and CL1), each
containing 4 Cortex-A55 cores. CPU PLLs are generating main CPU clocks
for each cluster, and there are alternate ("switch") clocks that can be
used temporarily while re-configuring the PLL for the new rate. ACLK,
ATCLK, PCLKDBG and PERIPHCLK clocks are driving corresponding buses.
CLK_CLUSTERx_SCLK are actual leaf CPU clocks and should be used to
change CPU rates. Also some CoreSight clocks can be derived from
DBG_USER (debug clock).
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
.../clock/samsung,exynos850-clock.yaml | 42 +++++++++++++++
include/dt-bindings/clock/exynos850.h | 54 +++++++++++++++++++
2 files changed, 96 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index c752c8985a53..cdc5ded59fe5 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -36,6 +36,8 @@ properties:
- samsung,exynos850-cmu-aud
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
+ - samsung,exynos850-cmu-cpucl0
+ - samsung,exynos850-cmu-cpucl1
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-g3d
- samsung,exynos850-cmu-hsi
@@ -152,6 +154,46 @@ allOf:
- const: dout_core_mmc_embd
- const: dout_core_sss
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cpucl0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CPUCL0 switch clock (from CMU_TOP)
+ - description: CPUCL0 debug clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cpucl0_switch
+ - const: dout_cpucl0_dbg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cpucl1
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CPUCL1 switch clock (from CMU_TOP)
+ - description: CPUCL1 debug clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_cpucl1_switch
+ - const: dout_cpucl1_dbg
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index bc15108aa3c2..7666241520f8 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -88,6 +88,18 @@
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
+#define CLK_MOUT_CPUCL0_DBG 79
+#define CLK_MOUT_CPUCL0_SWITCH 80
+#define CLK_GOUT_CPUCL0_DBG 81
+#define CLK_GOUT_CPUCL0_SWITCH 82
+#define CLK_DOUT_CPUCL0_DBG 83
+#define CLK_DOUT_CPUCL0_SWITCH 84
+#define CLK_MOUT_CPUCL1_DBG 85
+#define CLK_MOUT_CPUCL1_SWITCH 86
+#define CLK_GOUT_CPUCL1_DBG 87
+#define CLK_GOUT_CPUCL1_SWITCH 88
+#define CLK_DOUT_CPUCL1_DBG 89
+#define CLK_DOUT_CPUCL1_SWITCH 90
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@@ -195,6 +207,48 @@
#define CLK_GOUT_CMGP_USI1_PCLK 14
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
+/* CMU_CPUCL0 */
+#define CLK_FOUT_CPUCL0_PLL 1
+#define CLK_MOUT_PLL_CPUCL0 2
+#define CLK_MOUT_CPUCL0_SWITCH_USER 3
+#define CLK_MOUT_CPUCL0_DBG_USER 4
+#define CLK_MOUT_CPUCL0_PLL 5
+#define CLK_DOUT_CPUCL0_CPU 6
+#define CLK_DOUT_CPUCL0_CMUREF 7
+#define CLK_DOUT_CPUCL0_PCLK 8
+#define CLK_DOUT_CLUSTER0_ACLK 9
+#define CLK_DOUT_CLUSTER0_ATCLK 10
+#define CLK_DOUT_CLUSTER0_PCLKDBG 11
+#define CLK_DOUT_CLUSTER0_PERIPHCLK 12
+#define CLK_GOUT_CLUSTER0_ATCLK 13
+#define CLK_GOUT_CLUSTER0_PCLK 14
+#define CLK_GOUT_CLUSTER0_PERIPHCLK 15
+#define CLK_GOUT_CLUSTER0_SCLK 16
+#define CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK 17
+#define CLK_GOUT_CLUSTER0_CPU 18
+#define CLK_CLUSTER0_SCLK 19
+
+/* CMU_CPUCL1 */
+#define CLK_FOUT_CPUCL1_PLL 1
+#define CLK_MOUT_PLL_CPUCL1 2
+#define CLK_MOUT_CPUCL1_SWITCH_USER 3
+#define CLK_MOUT_CPUCL1_DBG_USER 4
+#define CLK_MOUT_CPUCL1_PLL 5
+#define CLK_DOUT_CPUCL1_CPU 6
+#define CLK_DOUT_CPUCL1_CMUREF 7
+#define CLK_DOUT_CPUCL1_PCLK 8
+#define CLK_DOUT_CLUSTER1_ACLK 9
+#define CLK_DOUT_CLUSTER1_ATCLK 10
+#define CLK_DOUT_CLUSTER1_PCLKDBG 11
+#define CLK_DOUT_CLUSTER1_PERIPHCLK 12
+#define CLK_GOUT_CLUSTER1_ATCLK 13
+#define CLK_GOUT_CLUSTER1_PCLK 14
+#define CLK_GOUT_CLUSTER1_PERIPHCLK 15
+#define CLK_GOUT_CLUSTER1_SCLK 16
+#define CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK 17
+#define CLK_GOUT_CLUSTER1_CPU 18
+#define CLK_CLUSTER1_SCLK 19
+
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_G3D_PLL 2
--
2.39.2
Reduce the scope of struct exynos_cpuclk, as it's only used in clk-cpu.c
internally. All drivers using clk-pll.h already include clk.h as well,
so this change doesn't break anything.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-cpu.c | 29 +++++++++++++++++++++++++
drivers/clk/samsung/clk-cpu.h | 41 +++++------------------------------
2 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index e02730776aaa..6412fd2580e0 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -34,6 +34,8 @@
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
+
+#include "clk.h"
#include "clk-cpu.h"
#define E4210_SRC_CPU 0x0
@@ -64,6 +66,33 @@
#define DIV_MASK_ALL GENMASK(31, 0)
#define MUX_MASK GENMASK(2, 0)
+/**
+ * struct exynos_cpuclk - information about clock supplied to a CPU core
+ * @hw: handle between CCF and CPU clock
+ * @alt_parent: alternate parent clock to use when switching the speed
+ * of the primary parent clock
+ * @ctrl_base: base address of the clock controller
+ * @lock: cpu clock domain register access lock
+ * @cfg: cpu clock rate configuration data
+ * @num_cfgs: number of array elements in @cfg array
+ * @clk_nb: clock notifier registered for changes in clock speed of the
+ * primary parent clock
+ * @flags: configuration flags for the CPU clock
+ *
+ * This structure holds information required for programming the CPU clock for
+ * various clock speeds.
+ */
+struct exynos_cpuclk {
+ struct clk_hw hw;
+ const struct clk_hw *alt_parent;
+ void __iomem *ctrl_base;
+ spinlock_t *lock;
+ const struct exynos_cpuclk_cfg_data *cfg;
+ const unsigned long num_cfgs;
+ struct notifier_block clk_nb;
+ unsigned long flags;
+};
+
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 0164bd9ad021..ee57f3638fed 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -8,7 +8,12 @@
#ifndef __SAMSUNG_CLK_CPU_H
#define __SAMSUNG_CLK_CPU_H
-#include "clk.h"
+/* The CPU clock registers have DIV1 configuration register */
+#define CLK_CPU_HAS_DIV1 BIT(0)
+/* When ALT parent is active, debug clocks need safe divider values */
+#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1)
+/* The CPU clock registers have Exynos5433-compatible layout */
+#define CLK_CPU_HAS_E5433_REGS_LAYOUT BIT(2)
/**
* struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
@@ -28,38 +33,4 @@ struct exynos_cpuclk_cfg_data {
unsigned long div1;
};
-/**
- * struct exynos_cpuclk - information about clock supplied to a CPU core
- * @hw: handle between CCF and CPU clock
- * @alt_parent: alternate parent clock to use when switching the speed
- * of the primary parent clock
- * @ctrl_base: base address of the clock controller
- * @lock: cpu clock domain register access lock
- * @cfg: cpu clock rate configuration data
- * @num_cfgs: number of array elements in @cfg array
- * @clk_nb: clock notifier registered for changes in clock speed of the
- * primary parent clock
- * @flags: configuration flags for the CPU clock
- *
- * This structure holds information required for programming the CPU clock for
- * various clock speeds.
- */
-struct exynos_cpuclk {
- struct clk_hw hw;
- const struct clk_hw *alt_parent;
- void __iomem *ctrl_base;
- spinlock_t *lock;
- const struct exynos_cpuclk_cfg_data *cfg;
- const unsigned long num_cfgs;
- struct notifier_block clk_nb;
- unsigned long flags;
-
-/* The CPU clock registers have DIV1 configuration register */
-#define CLK_CPU_HAS_DIV1 (1 << 0)
-/* When ALT parent is active, debug clocks need safe divider values */
-#define CLK_CPU_NEEDS_DEBUG_ALT_DIV (1 << 1)
-/* The CPU clock registers have Exynos5433-compatible layout */
-#define CLK_CPU_HAS_E5433_REGS_LAYOUT (1 << 2)
-};
-
#endif /* __SAMSUNG_CLK_CPU_H */
--
2.39.2
clk-cpu.c has numerous style issues reported by checkpatch and easily
identified otherwise. Give it some love and fix those warnings where it
makes sense. Also make stabilization time a named constant to get rid of
the magic number in clk-cpu.c.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-cpu.c | 65 ++++++++++++++++++-----------------
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 3e62ade120c5..e02730776aaa 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -16,18 +16,18 @@
* of the SoC or supplied after the SoC characterization.
*
* The below implementation of the CPU clock allows the rate changes of the CPU
- * clock and the corresponding rate changes of the auxillary clocks of the CPU
+ * clock and the corresponding rate changes of the auxiliary clocks of the CPU
* domain. The platform clock driver provides a clock register configuration
* for each configurable rate which is then used to program the clock hardware
- * registers to acheive a fast co-oridinated rate change for all the CPU domain
+ * registers to achieve a fast coordinated rate change for all the CPU domain
* clocks.
*
* On a rate change request for the CPU clock, the rate change is propagated
- * upto the PLL supplying the clock to the CPU domain clock blocks. While the
+ * up to the PLL supplying the clock to the CPU domain clock blocks. While the
* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
* alternate clock source. If required, the alternate clock source is divided
* down in order to keep the output clock rate within the previous OPP limits.
-*/
+ */
#include <linux/errno.h>
#include <linux/io.h>
@@ -50,17 +50,19 @@
#define E5433_DIV_STAT_CPU0 0x500
#define E5433_DIV_STAT_CPU1 0x504
-#define E4210_DIV0_RATIO0_MASK 0x7
-#define E4210_DIV1_HPM_MASK (0x7 << 4)
-#define E4210_DIV1_COPY_MASK (0x7 << 0)
-#define E4210_MUX_HPM_MASK (1 << 20)
+#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
+#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
+#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
+#define E4210_MUX_HPM_MASK BIT(20)
#define E4210_DIV0_ATB_SHIFT 16
#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
+/* Divider stabilization time, msec */
+#define MAX_STAB_TIME 10
#define MAX_DIV 8
-#define DIV_MASK 7
-#define DIV_MASK_ALL 0xffffffff
-#define MUX_MASK 7
+#define DIV_MASK GENMASK(2, 0)
+#define DIV_MASK_ALL GENMASK(31, 0)
+#define MUX_MASK GENMASK(2, 0)
/*
* Helper function to wait until divider(s) have stabilized after the divider
@@ -68,7 +70,7 @@
*/
static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
{
- unsigned long timeout = jiffies + msecs_to_jiffies(10);
+ unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
do {
if (!(readl(div_reg) & mask))
@@ -86,9 +88,9 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
* value was changed.
*/
static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
- unsigned long mux_value)
+ unsigned long mux_value)
{
- unsigned long timeout = jiffies + msecs_to_jiffies(10);
+ unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
do {
if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
@@ -101,18 +103,18 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
pr_err("%s: re-parenting mux timed-out\n", __func__);
}
-/* common round rate callback useable for all types of CPU clocks */
-static long exynos_cpuclk_round_rate(struct clk_hw *hw,
- unsigned long drate, unsigned long *prate)
+/* common round rate callback usable for all types of CPU clocks */
+static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
{
struct clk_hw *parent = clk_hw_get_parent(hw);
*prate = clk_hw_round_rate(parent, drate);
return *prate;
}
-/* common recalc rate callback useable for all types of CPU clocks */
+/* common recalc rate callback usable for all types of CPU clocks */
static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+ unsigned long parent_rate)
{
/*
* The CPU clock output (armclk) rate is the same as its parent
@@ -135,7 +137,7 @@ static const struct clk_ops exynos_cpuclk_clk_ops = {
* dividers to be programmed.
*/
static void exynos_set_safe_div(void __iomem *base, unsigned long div,
- unsigned long mask)
+ unsigned long mask)
{
unsigned long div0;
@@ -151,7 +153,6 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
- unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@@ -187,6 +188,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
*/
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
+ unsigned long alt_div, alt_div_mask = DIV_MASK;
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
WARN_ON(alt_div >= MAX_DIV);
@@ -215,7 +217,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
writel(div1, base + E4210_DIV_CPU1);
wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
- DIV_MASK_ALL);
+ DIV_MASK_ALL);
}
spin_unlock_irqrestore(cpuclk->lock, flags);
@@ -263,7 +265,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
* dividers to be programmed.
*/
static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
- unsigned long mask)
+ unsigned long mask)
{
unsigned long div0;
@@ -279,7 +281,6 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
- unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@@ -309,6 +310,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
*/
if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
+ unsigned long alt_div, alt_div_mask = DIV_MASK;
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
WARN_ON(alt_div >= MAX_DIV);
@@ -358,7 +360,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
* notifications of the parent clock of cpuclk.
*/
static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
- unsigned long event, void *data)
+ unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
@@ -381,7 +383,7 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
* notifications of the parent clock of cpuclk.
*/
static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
- unsigned long event, void *data)
+ unsigned long event, void *data)
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
@@ -438,11 +440,10 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
else
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
-
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
- __func__, name);
+ __func__, name);
goto free_cpuclk;
}
@@ -454,7 +455,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
ret = clk_hw_register(NULL, &cpuclk->hw);
if (ret) {
- pr_err("%s: could not register cpuclk %s\n", __func__, name);
+ pr_err("%s: could not register cpuclk %s\n", __func__, name);
goto free_cpuclk_data;
}
@@ -482,8 +483,8 @@ void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )
num_cfgs++;
- exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],
- hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,
- list->flags);
+ exynos_register_cpu_clock(ctx, list->id, list->name,
+ hws[list->parent_id], hws[list->alt_parent_id],
+ list->offset, list->cfg, num_cfgs, list->flags);
}
}
--
2.39.2
Pass CPU clock data structure to exynos_register_cpu_clock() instead of
passing its fields separately there. That simplifies the signature of
exynos_register_cpu_clock() and makes it easier to add more fields to
struct samsung_cpu_clock later. This style follows the example of
samsung_clk_register_pll().
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-cpu.c | 46 +++++++++++++++++------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 6412fd2580e0..7b6fd331a7ec 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -432,16 +432,19 @@ static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
/* helper function to register a CPU clock */
static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
- unsigned int lookup_id, const char *name,
- const struct clk_hw *parent, const struct clk_hw *alt_parent,
- unsigned long offset, const struct exynos_cpuclk_cfg_data *cfg,
- unsigned long num_cfgs, unsigned long flags)
+ const struct samsung_cpu_clock *clk_data)
{
+ const struct clk_hw *parent, *alt_parent;
+ struct clk_hw **hws;
struct exynos_cpuclk *cpuclk;
struct clk_init_data init;
const char *parent_name;
+ unsigned int num_cfgs;
int ret = 0;
+ hws = ctx->clk_data.hws;
+ parent = hws[clk_data->parent_id];
+ alt_parent = hws[clk_data->alt_parent_id];
if (IS_ERR(parent) || IS_ERR(alt_parent)) {
pr_err("%s: invalid parent clock(s)\n", __func__);
return -EINVAL;
@@ -453,7 +456,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
parent_name = clk_hw_get_name(parent);
- init.name = name;
+ init.name = clk_data->name;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
@@ -461,10 +464,10 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->alt_parent = alt_parent;
cpuclk->hw.init = &init;
- cpuclk->ctrl_base = ctx->reg_base + offset;
+ cpuclk->ctrl_base = ctx->reg_base + clk_data->offset;
cpuclk->lock = &ctx->lock;
- cpuclk->flags = flags;
- if (flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
+ cpuclk->flags = clk_data->flags;
+ if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
else
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
@@ -472,11 +475,16 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {
pr_err("%s: failed to register clock notifier for %s\n",
- __func__, name);
+ __func__, clk_data->name);
goto free_cpuclk;
}
- cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
+ /* Find count of configuration rates in cfg */
+ for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; )
+ num_cfgs++;
+
+ cpuclk->cfg = kmemdup(clk_data->cfg, sizeof(*clk_data->cfg) * num_cfgs,
+ GFP_KERNEL);
if (!cpuclk->cfg) {
ret = -ENOMEM;
goto unregister_clk_nb;
@@ -484,11 +492,12 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
ret = clk_hw_register(NULL, &cpuclk->hw);
if (ret) {
- pr_err("%s: could not register cpuclk %s\n", __func__, name);
+ pr_err("%s: could not register cpuclk %s\n", __func__,
+ clk_data->name);
goto free_cpuclk_data;
}
- samsung_clk_add_lookup(ctx, &cpuclk->hw, lookup_id);
+ samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id);
return 0;
free_cpuclk_data:
@@ -504,16 +513,7 @@ void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
const struct samsung_cpu_clock *list, unsigned int nr_clk)
{
unsigned int idx;
- unsigned int num_cfgs;
- struct clk_hw **hws = ctx->clk_data.hws;
- for (idx = 0; idx < nr_clk; idx++, list++) {
- /* find count of configuration rates in cfg */
- for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )
- num_cfgs++;
-
- exynos_register_cpu_clock(ctx, list->id, list->name,
- hws[list->parent_id], hws[list->alt_parent_id],
- list->offset, list->cfg, num_cfgs, list->flags);
- }
+ for (idx = 0; idx < nr_clk; idx++)
+ exynos_register_cpu_clock(ctx, &list[idx]);
}
--
2.39.2
Reduce the code duplication by making all chips use a single version of
exynos_cpuclk_notifier_cb() function. That will prevent the code bloat
when adding new chips support too.
Also don't pass base address to pre/post rate change functions, as it
can be easily derived from already passed cpuclk param.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-cpu.c | 63 ++++++++++++++++-------------------
1 file changed, 28 insertions(+), 35 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 7b6fd331a7ec..427018e8dd8c 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -66,6 +66,11 @@
#define DIV_MASK_ALL GENMASK(31, 0)
#define MUX_MASK GENMASK(2, 0)
+struct exynos_cpuclk;
+
+typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk);
+
/**
* struct exynos_cpuclk - information about clock supplied to a CPU core
* @hw: handle between CCF and CPU clock
@@ -78,6 +83,8 @@
* @clk_nb: clock notifier registered for changes in clock speed of the
* primary parent clock
* @flags: configuration flags for the CPU clock
+ * @pre_rate_cb: callback to run before CPU clock rate change
+ * @post_rate_cb: callback to run after CPU clock rate change
*
* This structure holds information required for programming the CPU clock for
* various clock speeds.
@@ -91,6 +98,9 @@ struct exynos_cpuclk {
const unsigned long num_cfgs;
struct notifier_block clk_nb;
unsigned long flags;
+
+ exynos_rate_change_fn_t pre_rate_cb;
+ exynos_rate_change_fn_t post_rate_cb;
};
/*
@@ -178,9 +188,10 @@ static void exynos_set_safe_div(void __iomem *base, unsigned long div,
/* handler for pre-rate change notification from parent clock */
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
- struct exynos_cpuclk *cpuclk, void __iomem *base)
+ struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ void __iomem *base = cpuclk->ctrl_base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@@ -255,9 +266,10 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* handler for post-rate change notification from parent clock */
static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
- struct exynos_cpuclk *cpuclk, void __iomem *base)
+ struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ void __iomem *base = cpuclk->ctrl_base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
@@ -306,9 +318,10 @@ static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
/* handler for pre-rate change notification from parent clock */
static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
- struct exynos_cpuclk *cpuclk, void __iomem *base)
+ struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ void __iomem *base = cpuclk->ctrl_base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@@ -366,8 +379,9 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* handler for post-rate change notification from parent clock */
static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
- struct exynos_cpuclk *cpuclk, void __iomem *base)
+ struct exynos_cpuclk *cpuclk)
{
+ void __iomem *base = cpuclk->ctrl_base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
@@ -393,39 +407,14 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
{
struct clk_notifier_data *ndata = data;
struct exynos_cpuclk *cpuclk;
- void __iomem *base;
int err = 0;
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
- base = cpuclk->ctrl_base;
if (event == PRE_RATE_CHANGE)
- err = exynos_cpuclk_pre_rate_change(ndata, cpuclk, base);
+ err = cpuclk->pre_rate_cb(ndata, cpuclk);
else if (event == POST_RATE_CHANGE)
- err = exynos_cpuclk_post_rate_change(ndata, cpuclk, base);
-
- return notifier_from_errno(err);
-}
-
-/*
- * This notifier function is called for the pre-rate and post-rate change
- * notifications of the parent clock of cpuclk.
- */
-static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
- unsigned long event, void *data)
-{
- struct clk_notifier_data *ndata = data;
- struct exynos_cpuclk *cpuclk;
- void __iomem *base;
- int err = 0;
-
- cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
- base = cpuclk->ctrl_base;
-
- if (event == PRE_RATE_CHANGE)
- err = exynos5433_cpuclk_pre_rate_change(ndata, cpuclk, base);
- else if (event == POST_RATE_CHANGE)
- err = exynos5433_cpuclk_post_rate_change(ndata, cpuclk, base);
+ err = cpuclk->post_rate_cb(ndata, cpuclk);
return notifier_from_errno(err);
}
@@ -467,10 +456,14 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->ctrl_base = ctx->reg_base + clk_data->offset;
cpuclk->lock = &ctx->lock;
cpuclk->flags = clk_data->flags;
- if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT)
- cpuclk->clk_nb.notifier_call = exynos5433_cpuclk_notifier_cb;
- else
- cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
+ cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
+ if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) {
+ cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change;
+ cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change;
+ } else {
+ cpuclk->pre_rate_cb = exynos_cpuclk_pre_rate_change;
+ cpuclk->post_rate_cb = exynos_cpuclk_post_rate_change;
+ }
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {
--
2.39.2
clk-cpu.c is going to get messy as new chips support is added.
Restructure the code by pulling related functions and definitions
together, grouping those by their relation to a particular chip or other
categories, to simplify the code navigation.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-cpu.c | 114 ++++++++++++++++++----------------
1 file changed, 61 insertions(+), 53 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 427018e8dd8c..d550a4bb632f 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -38,34 +38,6 @@
#include "clk.h"
#include "clk-cpu.h"
-#define E4210_SRC_CPU 0x0
-#define E4210_STAT_CPU 0x200
-#define E4210_DIV_CPU0 0x300
-#define E4210_DIV_CPU1 0x304
-#define E4210_DIV_STAT_CPU0 0x400
-#define E4210_DIV_STAT_CPU1 0x404
-
-#define E5433_MUX_SEL2 0x008
-#define E5433_MUX_STAT2 0x208
-#define E5433_DIV_CPU0 0x400
-#define E5433_DIV_CPU1 0x404
-#define E5433_DIV_STAT_CPU0 0x500
-#define E5433_DIV_STAT_CPU1 0x504
-
-#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
-#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
-#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
-#define E4210_MUX_HPM_MASK BIT(20)
-#define E4210_DIV0_ATB_SHIFT 16
-#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
-
-/* Divider stabilization time, msec */
-#define MAX_STAB_TIME 10
-#define MAX_DIV 8
-#define DIV_MASK GENMASK(2, 0)
-#define DIV_MASK_ALL GENMASK(31, 0)
-#define MUX_MASK GENMASK(2, 0)
-
struct exynos_cpuclk;
typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
@@ -103,6 +75,15 @@ struct exynos_cpuclk {
exynos_rate_change_fn_t post_rate_cb;
};
+/* ---- Common code --------------------------------------------------------- */
+
+/* Divider stabilization time, msec */
+#define MAX_STAB_TIME 10
+#define MAX_DIV 8
+#define DIV_MASK GENMASK(2, 0)
+#define DIV_MASK_ALL GENMASK(31, 0)
+#define MUX_MASK GENMASK(2, 0)
+
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
@@ -142,33 +123,21 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
pr_err("%s: re-parenting mux timed-out\n", __func__);
}
-/* common round rate callback usable for all types of CPU clocks */
-static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
-{
- struct clk_hw *parent = clk_hw_get_parent(hw);
- *prate = clk_hw_round_rate(parent, drate);
- return *prate;
-}
+/* ---- Exynos 3/4/5 -------------------------------------------------------- */
-/* common recalc rate callback usable for all types of CPU clocks */
-static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- /*
- * The CPU clock output (armclk) rate is the same as its parent
- * rate. Although there exist certain dividers inside the CPU
- * clock block that could be used to divide the parent clock,
- * the driver does not make use of them currently, except during
- * frequency transitions.
- */
- return parent_rate;
-}
+#define E4210_SRC_CPU 0x0
+#define E4210_STAT_CPU 0x200
+#define E4210_DIV_CPU0 0x300
+#define E4210_DIV_CPU1 0x304
+#define E4210_DIV_STAT_CPU0 0x400
+#define E4210_DIV_STAT_CPU1 0x404
-static const struct clk_ops exynos_cpuclk_clk_ops = {
- .recalc_rate = exynos_cpuclk_recalc_rate,
- .round_rate = exynos_cpuclk_round_rate,
-};
+#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
+#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
+#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
+#define E4210_MUX_HPM_MASK BIT(20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
/*
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
@@ -300,6 +269,15 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
return 0;
}
+/* ---- Exynos5433 ---------------------------------------------------------- */
+
+#define E5433_MUX_SEL2 0x008
+#define E5433_MUX_STAT2 0x208
+#define E5433_DIV_CPU0 0x400
+#define E5433_DIV_CPU1 0x404
+#define E5433_DIV_STAT_CPU0 0x500
+#define E5433_DIV_STAT_CPU1 0x504
+
/*
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
* div and mask contain the divider value and the register bit mask of the
@@ -398,6 +376,36 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
return 0;
}
+/* -------------------------------------------------------------------------- */
+
+/* Common round rate callback usable for all types of CPU clocks */
+static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
+{
+ struct clk_hw *parent = clk_hw_get_parent(hw);
+ *prate = clk_hw_round_rate(parent, drate);
+ return *prate;
+}
+
+/* Common recalc rate callback usable for all types of CPU clocks */
+static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ /*
+ * The CPU clock output (armclk) rate is the same as its parent
+ * rate. Although there exist certain dividers inside the CPU
+ * clock block that could be used to divide the parent clock,
+ * the driver does not make use of them currently, except during
+ * frequency transitions.
+ */
+ return parent_rate;
+}
+
+static const struct clk_ops exynos_cpuclk_clk_ops = {
+ .recalc_rate = exynos_cpuclk_recalc_rate,
+ .round_rate = exynos_cpuclk_round_rate,
+};
+
/*
* This notifier function is called for the pre-rate and post-rate change
* notifications of the parent clock of cpuclk.
--
2.39.2
Use a dedicated enum field to explicitly specify which register layout
should be used for the CPU clock, instead of passing it as a bit flag.
This way it would be possible to keep the chip-specific data in some
array, where each chip structure could be accessed by its corresponding
layout index. It prepares clk-cpu.c for adding new chips support, which
might have different data for different CPU clusters.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Improved the commit message: explained why enum is needed for
specifying the layout (vs bit flag)
- Included clk-cpu.h in clk.h as it uses enum exynos_cpuclk_layout
from clk-cpu.h (it's needed because preceding patch adding headers
was dropped)
drivers/clk/samsung/clk-cpu.c | 2 +-
drivers/clk/samsung/clk-cpu.h | 12 ++++++++++--
drivers/clk/samsung/clk-exynos3250.c | 2 +-
drivers/clk/samsung/clk-exynos4.c | 6 +++---
drivers/clk/samsung/clk-exynos5250.c | 3 ++-
drivers/clk/samsung/clk-exynos5420.c | 8 ++++----
drivers/clk/samsung/clk-exynos5433.c | 8 ++++----
drivers/clk/samsung/clk.h | 5 ++++-
8 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 82d54b0c9040..635ab8cc54a2 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -465,7 +465,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->lock = &ctx->lock;
cpuclk->flags = clk_data->flags;
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
- if (clk_data->flags & CLK_CPU_HAS_E5433_REGS_LAYOUT) {
+ if (clk_data->reg_layout == CPUCLK_LAYOUT_E5433) {
cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change;
cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change;
} else {
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index ee57f3638fed..4382ab005ad3 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -12,8 +12,16 @@
#define CLK_CPU_HAS_DIV1 BIT(0)
/* When ALT parent is active, debug clocks need safe divider values */
#define CLK_CPU_NEEDS_DEBUG_ALT_DIV BIT(1)
-/* The CPU clock registers have Exynos5433-compatible layout */
-#define CLK_CPU_HAS_E5433_REGS_LAYOUT BIT(2)
+
+/**
+ * enum exynos_cpuclk_layout - CPU clock registers layout compatibility
+ * @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout
+ * @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout
+ */
+enum exynos_cpuclk_layout {
+ CPUCLK_LAYOUT_E4210,
+ CPUCLK_LAYOUT_E5433,
+};
/**
* struct exynos_cpuclk_cfg_data - config data to setup cpu clocks
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index bf149fae04c3..cd4fec323a42 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -775,7 +775,7 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
- CLK_CPU_HAS_DIV1, 0x14000, e3250_armclk_d),
+ CLK_CPU_HAS_DIV1, 0x14000, CPUCLK_LAYOUT_E4210, e3250_armclk_d),
};
static void __init exynos3_core_down_clock(void __iomem *reg_base)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d5b1e9f49d8b..a026ccca7315 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1253,19 +1253,19 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
- e4210_armclk_d),
+ CPUCLK_LAYOUT_E4210, e4210_armclk_d),
};
static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
- e4212_armclk_d),
+ CPUCLK_LAYOUT_E4210, e4212_armclk_d),
};
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
- e4412_armclk_d),
+ CPUCLK_LAYOUT_E4210, e4412_armclk_d),
};
/* register exynos4 clocks */
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 58df80de52ef..e02e7c013f3d 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -777,7 +777,8 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL,
- CLK_CPU_HAS_DIV1, 0x0, exynos5250_armclk_d),
+ CLK_CPU_HAS_DIV1, 0x0, CPUCLK_LAYOUT_E4210,
+ exynos5250_armclk_d),
};
static const struct of_device_id ext_clk_match[] __initconst = {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index bd7b304d2c00..c630135c686b 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1556,16 +1556,16 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
- 0x0, exynos5420_eglclk_d),
+ 0x0, CPUCLK_LAYOUT_E4210, exynos5420_eglclk_d),
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
- 0x28000, exynos5420_kfcclk_d),
+ 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
};
static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
- 0x0, exynos5800_eglclk_d),
+ 0x0, CPUCLK_LAYOUT_E4210, exynos5800_eglclk_d),
CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
- 0x28000, exynos5420_kfcclk_d),
+ 0x28000, CPUCLK_LAYOUT_E4210, exynos5420_kfcclk_d),
};
static const struct of_device_id ext_clk_match[] __initconst = {
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index d3779eefb438..609d31a7aa52 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3700,8 +3700,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst
static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
- CLK_MOUT_BUS_PLL_APOLLO_USER, CLK_CPU_HAS_E5433_REGS_LAYOUT,
- 0x0, exynos5433_apolloclk_d),
+ CLK_MOUT_BUS_PLL_APOLLO_USER, 0, 0x0,
+ CPUCLK_LAYOUT_E5433, exynos5433_apolloclk_d),
};
static const struct samsung_cmu_info apollo_cmu_info __initconst = {
@@ -3944,8 +3944,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst =
static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
- CLK_MOUT_BUS_PLL_ATLAS_USER, CLK_CPU_HAS_E5433_REGS_LAYOUT,
- 0x0, exynos5433_atlasclk_d),
+ CLK_MOUT_BUS_PLL_ATLAS_USER, 0, 0x0,
+ CPUCLK_LAYOUT_E5433, exynos5433_atlasclk_d),
};
static const struct samsung_cmu_info atlas_cmu_info __initconst = {
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index 516b716407e5..a763309e6f12 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -12,6 +12,7 @@
#include <linux/clk-provider.h>
#include "clk-pll.h"
+#include "clk-cpu.h"
/**
* struct samsung_clk_provider - information about clock provider
@@ -282,10 +283,11 @@ struct samsung_cpu_clock {
unsigned int alt_parent_id;
unsigned long flags;
int offset;
+ enum exynos_cpuclk_layout reg_layout;
const struct exynos_cpuclk_cfg_data *cfg;
};
-#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _cfg) \
+#define CPU_CLK(_id, _name, _pid, _apid, _flags, _offset, _layout, _cfg) \
{ \
.id = _id, \
.name = _name, \
@@ -293,6 +295,7 @@ struct samsung_cpu_clock {
.alt_parent_id = _apid, \
.flags = _flags, \
.offset = _offset, \
+ .reg_layout = _layout, \
.cfg = _cfg, \
}
--
2.39.2
The documentation for struct exynos_cpuclk says .ctrl_base field should
contain the controller base address. There are two different problems
with that:
1. All Exynos clock drivers are actually passing CPU_SRC register offset
via CPU_CLK() macro, which in turn gets assigned to mentioned
.ctrl_base field. Because CPU_SRC register usually already has 0x200
offset from controller's base, all other register offsets in
clk-cpu.c (like DIVs and MUXes) are specified as offsets from CPU_SRC
offset, and not from controller's base. That makes things confusing
and inconsistent with register offsets provided in Exynos clock
drivers, also breaking the contract for .ctrl_base field as described
in struct exynos_cpuclk doc.
2. Furthermore, some Exynos chips have an additional offset for the
start of CPU clock registers block (inside of the CMU). There might
be different reasons for that, e.g.:
- The CMU contains clocks for two different CPUs (like in Exynos5420)
- The CMU contains also non-CPU clocks as well (like in Exynos4)
- The CPU CMU exists as a dedicated hardware block in the SoC layout,
but is modelled as a part of bigger CMU in the driver (like in case
of Exynos3250)
That means the .ctrl_base field is actually not a controller's base,
but instead it's a start address of the CPU clock registers inside of
the CMU.
Rework all register offsets in clk-cpu.c to be actual offsets from the
CPU clock register block start, and fix offsets provided to CPU_CLK()
macro in all Exynos clock drivers. Also clarify the .ctrl_base field
documentation and rename it to just .base, because it doesn't really
contain the CMU base.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Renamed .ctrl_base field to .base and fixed its documentation
- Fixed typo in commit message: Exynis -> Exynos
- Improved the commit message: mentioned that .ctrl_base is actually a
start address of the CPU clock register block, not the CMU base
drivers/clk/samsung/clk-cpu.c | 38 ++++++++++++++--------------
drivers/clk/samsung/clk-exynos3250.c | 2 +-
drivers/clk/samsung/clk-exynos4.c | 9 ++++---
drivers/clk/samsung/clk-exynos5250.c | 4 +--
drivers/clk/samsung/clk-exynos5420.c | 16 ++++++------
drivers/clk/samsung/clk-exynos5433.c | 10 +++-----
6 files changed, 40 insertions(+), 39 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index d550a4bb632f..82d54b0c9040 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -48,7 +48,7 @@ typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
* @hw: handle between CCF and CPU clock
* @alt_parent: alternate parent clock to use when switching the speed
* of the primary parent clock
- * @ctrl_base: base address of the clock controller
+ * @base: start address of the CPU clock registers block
* @lock: cpu clock domain register access lock
* @cfg: cpu clock rate configuration data
* @num_cfgs: number of array elements in @cfg array
@@ -64,7 +64,7 @@ typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
struct exynos_cpuclk {
struct clk_hw hw;
const struct clk_hw *alt_parent;
- void __iomem *ctrl_base;
+ void __iomem *base;
spinlock_t *lock;
const struct exynos_cpuclk_cfg_data *cfg;
const unsigned long num_cfgs;
@@ -125,12 +125,12 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
/* ---- Exynos 3/4/5 -------------------------------------------------------- */
-#define E4210_SRC_CPU 0x0
-#define E4210_STAT_CPU 0x200
-#define E4210_DIV_CPU0 0x300
-#define E4210_DIV_CPU1 0x304
-#define E4210_DIV_STAT_CPU0 0x400
-#define E4210_DIV_STAT_CPU1 0x404
+#define E4210_SRC_CPU 0x200
+#define E4210_STAT_CPU 0x400
+#define E4210_DIV_CPU0 0x500
+#define E4210_DIV_CPU1 0x504
+#define E4210_DIV_STAT_CPU0 0x600
+#define E4210_DIV_STAT_CPU1 0x604
#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
@@ -160,7 +160,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
- void __iomem *base = cpuclk->ctrl_base;
+ void __iomem *base = cpuclk->base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@@ -238,7 +238,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
- void __iomem *base = cpuclk->ctrl_base;
+ void __iomem *base = cpuclk->base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
@@ -271,12 +271,12 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
/* ---- Exynos5433 ---------------------------------------------------------- */
-#define E5433_MUX_SEL2 0x008
-#define E5433_MUX_STAT2 0x208
-#define E5433_DIV_CPU0 0x400
-#define E5433_DIV_CPU1 0x404
-#define E5433_DIV_STAT_CPU0 0x500
-#define E5433_DIV_STAT_CPU1 0x504
+#define E5433_MUX_SEL2 0x208
+#define E5433_MUX_STAT2 0x408
+#define E5433_DIV_CPU0 0x600
+#define E5433_DIV_CPU1 0x604
+#define E5433_DIV_STAT_CPU0 0x700
+#define E5433_DIV_STAT_CPU1 0x704
/*
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
@@ -299,7 +299,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
- void __iomem *base = cpuclk->ctrl_base;
+ void __iomem *base = cpuclk->base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
unsigned long flags;
@@ -359,7 +359,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
- void __iomem *base = cpuclk->ctrl_base;
+ void __iomem *base = cpuclk->base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
unsigned long flags;
@@ -461,7 +461,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->alt_parent = alt_parent;
cpuclk->hw.init = &init;
- cpuclk->ctrl_base = ctx->reg_base + clk_data->offset;
+ cpuclk->base = ctx->reg_base + clk_data->offset;
cpuclk->lock = &ctx->lock;
cpuclk->flags = clk_data->flags;
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index a02461667664..bf149fae04c3 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -775,7 +775,7 @@ static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = {
static const struct samsung_cpu_clock exynos3250_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
- CLK_CPU_HAS_DIV1, 0x14200, e3250_armclk_d),
+ CLK_CPU_HAS_DIV1, 0x14000, e3250_armclk_d),
};
static void __init exynos3_core_down_clock(void __iomem *reg_base)
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 4ec41221e68f..d5b1e9f49d8b 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1252,17 +1252,20 @@ static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {
static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_SCLK_MPLL,
- CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
+ e4210_armclk_d),
};
static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
- CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
+ e4212_armclk_d),
};
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
- CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
+ CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14000,
+ e4412_armclk_d),
};
/* register exynos4 clocks */
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 8ebe6155d8b7..58df80de52ef 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -776,8 +776,8 @@ static const struct exynos_cpuclk_cfg_data exynos5250_armclk_d[] __initconst = {
};
static const struct samsung_cpu_clock exynos5250_cpu_clks[] __initconst = {
- CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL, CLK_CPU_HAS_DIV1, 0x200,
- exynos5250_armclk_d),
+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL,
+ CLK_CPU_HAS_DIV1, 0x0, exynos5250_armclk_d),
};
static const struct of_device_id ext_clk_match[] __initconst = {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 199843f12ae5..bd7b304d2c00 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1555,17 +1555,17 @@ static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
};
static const struct samsung_cpu_clock exynos5420_cpu_clks[] __initconst = {
- CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
- exynos5420_eglclk_d),
- CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
- exynos5420_kfcclk_d),
+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
+ 0x0, exynos5420_eglclk_d),
+ CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
+ 0x28000, exynos5420_kfcclk_d),
};
static const struct samsung_cpu_clock exynos5800_cpu_clks[] __initconst = {
- CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0, 0x200,
- exynos5800_eglclk_d),
- CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0, 0x28200,
- exynos5420_kfcclk_d),
+ CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MSPLL_CPU, 0,
+ 0x0, exynos5800_eglclk_d),
+ CPU_CLK(CLK_KFC_CLK, "kfcclk", CLK_MOUT_KPLL, CLK_MOUT_MSPLL_KFC, 0,
+ 0x28000, exynos5420_kfcclk_d),
};
static const struct of_device_id ext_clk_match[] __initconst = {
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 6bfc5d0cd924..d3779eefb438 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -3700,9 +3700,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst
static const struct samsung_cpu_clock apollo_cpu_clks[] __initconst = {
CPU_CLK(CLK_SCLK_APOLLO, "apolloclk", CLK_MOUT_APOLLO_PLL,
- CLK_MOUT_BUS_PLL_APOLLO_USER,
- CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
- exynos5433_apolloclk_d),
+ CLK_MOUT_BUS_PLL_APOLLO_USER, CLK_CPU_HAS_E5433_REGS_LAYOUT,
+ 0x0, exynos5433_apolloclk_d),
};
static const struct samsung_cmu_info apollo_cmu_info __initconst = {
@@ -3945,9 +3944,8 @@ static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst =
static const struct samsung_cpu_clock atlas_cpu_clks[] __initconst = {
CPU_CLK(CLK_SCLK_ATLAS, "atlasclk", CLK_MOUT_ATLAS_PLL,
- CLK_MOUT_BUS_PLL_ATLAS_USER,
- CLK_CPU_HAS_E5433_REGS_LAYOUT, 0x200,
- exynos5433_atlasclk_d),
+ CLK_MOUT_BUS_PLL_ATLAS_USER, CLK_CPU_HAS_E5433_REGS_LAYOUT,
+ 0x0, exynos5433_atlasclk_d),
};
static const struct samsung_cmu_info atlas_cmu_info __initconst = {
--
2.39.2
Keep chip specific data in the data structure, don't mix it with code.
It makes it easier to add more chip specific data further. Having all
chip specific data in the table eliminates possible code bloat when
adding more rate handlers for new chips, and also makes it possible to
keep some other chip related data in that array.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Improved the commit message: explained why it's beneficial for new
chips to keep chip-specific data in one table
drivers/clk/samsung/clk-cpu.c | 40 +++++++++++++++++++++++------------
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 635ab8cc54a2..eb2b67d08f89 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -43,6 +43,16 @@ struct exynos_cpuclk;
typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk);
+/**
+ * struct exynos_cpuclk_chip - Chip specific data for CPU clock
+ * @pre_rate_cb: callback to run before CPU clock rate change
+ * @post_rate_cb: callback to run after CPU clock rate change
+ */
+struct exynos_cpuclk_chip {
+ exynos_rate_change_fn_t pre_rate_cb;
+ exynos_rate_change_fn_t post_rate_cb;
+};
+
/**
* struct exynos_cpuclk - information about clock supplied to a CPU core
* @hw: handle between CCF and CPU clock
@@ -55,8 +65,7 @@ typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
* @clk_nb: clock notifier registered for changes in clock speed of the
* primary parent clock
* @flags: configuration flags for the CPU clock
- * @pre_rate_cb: callback to run before CPU clock rate change
- * @post_rate_cb: callback to run after CPU clock rate change
+ * @chip: chip-specific data for the CPU clock
*
* This structure holds information required for programming the CPU clock for
* various clock speeds.
@@ -70,9 +79,7 @@ struct exynos_cpuclk {
const unsigned long num_cfgs;
struct notifier_block clk_nb;
unsigned long flags;
-
- exynos_rate_change_fn_t pre_rate_cb;
- exynos_rate_change_fn_t post_rate_cb;
+ const struct exynos_cpuclk_chip *chip;
};
/* ---- Common code --------------------------------------------------------- */
@@ -420,13 +427,24 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb);
if (event == PRE_RATE_CHANGE)
- err = cpuclk->pre_rate_cb(ndata, cpuclk);
+ err = cpuclk->chip->pre_rate_cb(ndata, cpuclk);
else if (event == POST_RATE_CHANGE)
- err = cpuclk->post_rate_cb(ndata, cpuclk);
+ err = cpuclk->chip->post_rate_cb(ndata, cpuclk);
return notifier_from_errno(err);
}
+static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = {
+ [CPUCLK_LAYOUT_E4210] = {
+ .pre_rate_cb = exynos_cpuclk_pre_rate_change,
+ .post_rate_cb = exynos_cpuclk_post_rate_change,
+ },
+ [CPUCLK_LAYOUT_E5433] = {
+ .pre_rate_cb = exynos5433_cpuclk_pre_rate_change,
+ .post_rate_cb = exynos5433_cpuclk_post_rate_change,
+ },
+};
+
/* helper function to register a CPU clock */
static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
const struct samsung_cpu_clock *clk_data)
@@ -465,13 +483,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
cpuclk->lock = &ctx->lock;
cpuclk->flags = clk_data->flags;
cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
- if (clk_data->reg_layout == CPUCLK_LAYOUT_E5433) {
- cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change;
- cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change;
- } else {
- cpuclk->pre_rate_cb = exynos_cpuclk_pre_rate_change;
- cpuclk->post_rate_cb = exynos_cpuclk_post_rate_change;
- }
+ cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout];
ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
if (ret) {
--
2.39.2
Make it possible to use wait_until_mux_stable() for MUX registers where
the mask is different from MUX_MASK (e.g. in upcoming CPU clock
implementation for Exynos850).
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-cpu.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 93e961855875..89b24fd5d0a9 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -135,16 +135,16 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
* value was changed.
*/
static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
- unsigned long mux_value)
+ unsigned long mask, unsigned long mux_value)
{
unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
do {
- if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+ if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
return;
} while (time_before(jiffies, timeout));
- if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
+ if (((readl(mux_reg) >> mux_pos) & mask) == mux_value)
return;
pr_err("%s: re-parenting mux timed-out\n", __func__);
@@ -249,7 +249,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* select sclk_mpll as the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg | (1 << 16), base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 16, 2);
+ wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2);
/* alternate parent is active now. set the dividers */
writel(div0, base + regs->div_cpu0);
@@ -290,7 +290,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
/* select mout_apll as the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 16, 1);
+ wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1);
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
@@ -362,7 +362,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
/* select the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg | 1, base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 0, 2);
+ wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2);
/* alternate parent is active now. set the dividers */
writel(div0, base + regs->div_cpu0);
@@ -390,7 +390,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
/* select apll as the alternate parent */
mux_reg = readl(base + regs->mux_sel);
writel(mux_reg & ~1, base + regs->mux_sel);
- wait_until_mux_stable(base + regs->mux_stat, 0, 1);
+ wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1);
exynos_set_safe_div(cpuclk, div, div_mask);
spin_unlock_irqrestore(cpuclk->lock, flags);
--
2.39.2
Abstract CPU clock registers by keeping their offsets in a dedicated
chip specific structure to accommodate for oncoming Exynos850 support,
which has different offsets for cluster 0 and cluster 1. This rework
also makes it possible to use exynos_set_safe_div() for all chips, so
exynos5433_set_safe_div() is removed here to reduce the code
duplication. The ".regs" field has to be (void *) as different Exynos
chips can have very different register layout, so this way it's possible
for ".regs" to point to different structures, each representing its own
chip's layout.
No functional change.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Improved the commit message: explained why .regs field has to be
(void *)
- Changed .ctrl_base field to .base to reflect changes in previous
commits
drivers/clk/samsung/clk-cpu.c | 156 +++++++++++++++++++---------------
1 file changed, 86 insertions(+), 70 deletions(-)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index eb2b67d08f89..93e961855875 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -45,12 +45,14 @@ typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata,
/**
* struct exynos_cpuclk_chip - Chip specific data for CPU clock
+ * @regs: register offsets for CPU related clocks
* @pre_rate_cb: callback to run before CPU clock rate change
* @post_rate_cb: callback to run after CPU clock rate change
*/
struct exynos_cpuclk_chip {
- exynos_rate_change_fn_t pre_rate_cb;
- exynos_rate_change_fn_t post_rate_cb;
+ const void * const regs;
+ exynos_rate_change_fn_t pre_rate_cb;
+ exynos_rate_change_fn_t post_rate_cb;
};
/**
@@ -91,6 +93,24 @@ struct exynos_cpuclk {
#define DIV_MASK_ALL GENMASK(31, 0)
#define MUX_MASK GENMASK(2, 0)
+/**
+ * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
+ * @mux_sel: offset of CPU MUX_SEL register (for selecting MUX clock parent)
+ * @mux_stat: offset of CPU MUX_STAT register (for checking MUX clock status)
+ * @div_cpu0: offset of CPU DIV0 register (for modifying divider values)
+ * @div_cpu1: offset of CPU DIV1 register (for modifying divider values)
+ * @div_stat_cpu0: offset of CPU DIV0_STAT register (for checking DIV status)
+ * @div_stat_cpu1: offset of CPU DIV1_STAT register (for checking DIV status)
+ */
+struct exynos_cpuclk_regs {
+ u32 mux_sel;
+ u32 mux_stat;
+ u32 div_cpu0;
+ u32 div_cpu1;
+ u32 div_stat_cpu0;
+ u32 div_stat_cpu1;
+};
+
/*
* Helper function to wait until divider(s) have stabilized after the divider
* value has changed.
@@ -130,43 +150,48 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
pr_err("%s: re-parenting mux timed-out\n", __func__);
}
-/* ---- Exynos 3/4/5 -------------------------------------------------------- */
-
-#define E4210_SRC_CPU 0x200
-#define E4210_STAT_CPU 0x400
-#define E4210_DIV_CPU0 0x500
-#define E4210_DIV_CPU1 0x504
-#define E4210_DIV_STAT_CPU0 0x600
-#define E4210_DIV_STAT_CPU1 0x604
-
-#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
-#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
-#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
-#define E4210_MUX_HPM_MASK BIT(20)
-#define E4210_DIV0_ATB_SHIFT 16
-#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
-
/*
* Helper function to set the 'safe' dividers for the CPU clock. The parameters
* div and mask contain the divider value and the register bit mask of the
* dividers to be programmed.
*/
-static void exynos_set_safe_div(void __iomem *base, unsigned long div,
+static void exynos_set_safe_div(struct exynos_cpuclk *cpuclk, unsigned long div,
unsigned long mask)
{
+ const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
+ void __iomem *base = cpuclk->base;
unsigned long div0;
- div0 = readl(base + E4210_DIV_CPU0);
+ div0 = readl(base + regs->div_cpu0);
div0 = (div0 & ~mask) | (div & mask);
- writel(div0, base + E4210_DIV_CPU0);
- wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, mask);
+ writel(div0, base + regs->div_cpu0);
+ wait_until_divider_stable(base + regs->div_stat_cpu0, mask);
}
+/* ---- Exynos 3/4/5 -------------------------------------------------------- */
+
+#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
+#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
+#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
+#define E4210_MUX_HPM_MASK BIT(20)
+#define E4210_DIV0_ATB_SHIFT 16
+#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
+
+static const struct exynos_cpuclk_regs e4210_cpuclk_regs = {
+ .mux_sel = 0x200,
+ .mux_stat = 0x400,
+ .div_cpu0 = 0x500,
+ .div_cpu1 = 0x504,
+ .div_stat_cpu0 = 0x600,
+ .div_stat_cpu1 = 0x604,
+};
+
/* handler for pre-rate change notification from parent clock */
static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
void __iomem *base = cpuclk->base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
@@ -189,8 +214,8 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
div0 = cfg_data->div0;
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
div1 = cfg_data->div1;
- if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK)
- div1 = readl(base + E4210_DIV_CPU1) &
+ if (readl(base + regs->mux_sel) & E4210_MUX_HPM_MASK)
+ div1 = readl(base + regs->div_cpu1) &
(E4210_DIV1_HPM_MASK | E4210_DIV1_COPY_MASK);
}
@@ -217,22 +242,22 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
alt_div |= E4210_DIV0_ATB_MASK;
alt_div_mask |= E4210_DIV0_ATB_MASK;
}
- exynos_set_safe_div(base, alt_div, alt_div_mask);
+ exynos_set_safe_div(cpuclk, alt_div, alt_div_mask);
div0 |= alt_div;
}
/* select sclk_mpll as the alternate parent */
- mux_reg = readl(base + E4210_SRC_CPU);
- writel(mux_reg | (1 << 16), base + E4210_SRC_CPU);
- wait_until_mux_stable(base + E4210_STAT_CPU, 16, 2);
+ mux_reg = readl(base + regs->mux_sel);
+ writel(mux_reg | (1 << 16), base + regs->mux_sel);
+ wait_until_mux_stable(base + regs->mux_stat, 16, 2);
/* alternate parent is active now. set the dividers */
- writel(div0, base + E4210_DIV_CPU0);
- wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL);
+ writel(div0, base + regs->div_cpu0);
+ wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
- writel(div1, base + E4210_DIV_CPU1);
- wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
+ writel(div1, base + regs->div_cpu1);
+ wait_until_divider_stable(base + regs->div_stat_cpu1,
DIV_MASK_ALL);
}
@@ -245,6 +270,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
void __iomem *base = cpuclk->base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
@@ -262,50 +288,37 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
spin_lock_irqsave(cpuclk->lock, flags);
/* select mout_apll as the alternate parent */
- mux_reg = readl(base + E4210_SRC_CPU);
- writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU);
- wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1);
+ mux_reg = readl(base + regs->mux_sel);
+ writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
+ wait_until_mux_stable(base + regs->mux_stat, 16, 1);
if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
div_mask |= E4210_DIV0_ATB_MASK;
}
- exynos_set_safe_div(base, div, div_mask);
+ exynos_set_safe_div(cpuclk, div, div_mask);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
/* ---- Exynos5433 ---------------------------------------------------------- */
-#define E5433_MUX_SEL2 0x208
-#define E5433_MUX_STAT2 0x408
-#define E5433_DIV_CPU0 0x600
-#define E5433_DIV_CPU1 0x604
-#define E5433_DIV_STAT_CPU0 0x700
-#define E5433_DIV_STAT_CPU1 0x704
-
-/*
- * Helper function to set the 'safe' dividers for the CPU clock. The parameters
- * div and mask contain the divider value and the register bit mask of the
- * dividers to be programmed.
- */
-static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
- unsigned long mask)
-{
- unsigned long div0;
-
- div0 = readl(base + E5433_DIV_CPU0);
- div0 = (div0 & ~mask) | (div & mask);
- writel(div0, base + E5433_DIV_CPU0);
- wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, mask);
-}
+static const struct exynos_cpuclk_regs e5433_cpuclk_regs = {
+ .mux_sel = 0x208,
+ .mux_stat = 0x408,
+ .div_cpu0 = 0x600,
+ .div_cpu1 = 0x604,
+ .div_stat_cpu0 = 0x700,
+ .div_stat_cpu1 = 0x704,
+};
/* handler for pre-rate change notification from parent clock */
static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
void __iomem *base = cpuclk->base;
unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
unsigned long div0, div1 = 0, mux_reg;
@@ -342,21 +355,21 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
WARN_ON(alt_div >= MAX_DIV);
- exynos5433_set_safe_div(base, alt_div, alt_div_mask);
+ exynos_set_safe_div(cpuclk, alt_div, alt_div_mask);
div0 |= alt_div;
}
/* select the alternate parent */
- mux_reg = readl(base + E5433_MUX_SEL2);
- writel(mux_reg | 1, base + E5433_MUX_SEL2);
- wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 2);
+ mux_reg = readl(base + regs->mux_sel);
+ writel(mux_reg | 1, base + regs->mux_sel);
+ wait_until_mux_stable(base + regs->mux_stat, 0, 2);
/* alternate parent is active now. set the dividers */
- writel(div0, base + E5433_DIV_CPU0);
- wait_until_divider_stable(base + E5433_DIV_STAT_CPU0, DIV_MASK_ALL);
+ writel(div0, base + regs->div_cpu0);
+ wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
- writel(div1, base + E5433_DIV_CPU1);
- wait_until_divider_stable(base + E5433_DIV_STAT_CPU1, DIV_MASK_ALL);
+ writel(div1, base + regs->div_cpu1);
+ wait_until_divider_stable(base + regs->div_stat_cpu1, DIV_MASK_ALL);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -366,6 +379,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
struct exynos_cpuclk *cpuclk)
{
+ const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
void __iomem *base = cpuclk->base;
unsigned long div = 0, div_mask = DIV_MASK;
unsigned long mux_reg;
@@ -374,11 +388,11 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
spin_lock_irqsave(cpuclk->lock, flags);
/* select apll as the alternate parent */
- mux_reg = readl(base + E5433_MUX_SEL2);
- writel(mux_reg & ~1, base + E5433_MUX_SEL2);
- wait_until_mux_stable(base + E5433_MUX_STAT2, 0, 1);
+ mux_reg = readl(base + regs->mux_sel);
+ writel(mux_reg & ~1, base + regs->mux_sel);
+ wait_until_mux_stable(base + regs->mux_stat, 0, 1);
- exynos5433_set_safe_div(base, div, div_mask);
+ exynos_set_safe_div(cpuclk, div, div_mask);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
}
@@ -436,10 +450,12 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = {
[CPUCLK_LAYOUT_E4210] = {
+ .regs = &e4210_cpuclk_regs,
.pre_rate_cb = exynos_cpuclk_pre_rate_change,
.post_rate_cb = exynos_cpuclk_post_rate_change,
},
[CPUCLK_LAYOUT_E5433] = {
+ .regs = &e5433_cpuclk_regs,
.pre_rate_cb = exynos5433_cpuclk_pre_rate_change,
.post_rate_cb = exynos5433_cpuclk_post_rate_change,
},
--
2.39.2
Implement CPU clock control for Exynos850 SoC. It follows the same
procedure which is already implemented for other SoCs in clk-cpu.c:
1. Set the correct rate for the alternate parent (if needed) before
switching to use it as the CPU clock
2. Switch to the alternate parent, so the CPU continues to get clocked
while the PLL is being re-configured
3. Adjust the dividers for the CPU related buses (ACLK, ATCLK, etc)
4. Re-configure the PLL for the new CPU clock rate. It's done
automatically, as the CPU clock rate change propagates to the PLL
clock, because the CPU clock has CLK_SET_RATE_PARENT flag set in
exynos_register_cpu_clock()
5. Once the PLL is locked, set it back as the CPU clock source
6. Set alternate parent clock rate back to max speed
As in already existing clk-cpu.c code, the divider and mux clocks are
configured in a low-level fashion (using direct register access instead
of CCF API), to avoid affecting how DIV and MUX clock flags are declared
in the actual clock driver (clk-exynos850.c).
No functional change. This patch adds support for Exynos850 CPU clock,
but doesn't enable it per se.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Changed .ctrl_base field to .base, to reflect changes made in
previous commits
drivers/clk/samsung/clk-cpu.c | 183 ++++++++++++++++++++++++++++++++++
drivers/clk/samsung/clk-cpu.h | 4 +
2 files changed, 187 insertions(+)
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 89b24fd5d0a9..34c195a980b2 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -29,6 +29,7 @@
* down in order to keep the output clock rate within the previous OPP limits.
*/
+#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/slab.h>
@@ -397,6 +398,178 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
return 0;
}
+/* ---- Exynos850 ----------------------------------------------------------- */
+
+#define E850_DIV_RATIO_MASK GENMASK(3, 0)
+#define E850_BUSY_MASK BIT(16)
+
+/* Max time for divider or mux to stabilize, usec */
+#define E850_DIV_MUX_STAB_TIME 100
+/* OSCCLK clock rate, Hz */
+#define E850_OSCCLK (26 * MHZ)
+
+/**
+ * struct exynos850_cpuclk_regs - Register offsets for Exynos850 CPU clocks
+ * @mux: offset of MUX register for choosing CPU clock source
+ * @divs: offsets of DIV registers (ACLK, ATCLK, PCLKDBG and
+ * PERIPHCLK)
+ */
+struct exynos850_cpuclk_regs {
+ u32 mux;
+ u32 divs[4];
+};
+
+static const struct exynos850_cpuclk_regs e850cl0_cpuclk_regs = {
+ .mux = 0x100c,
+ .divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
+};
+
+static const struct exynos850_cpuclk_regs e850cl1_cpuclk_regs = {
+ .mux = 0x1000,
+ .divs = { 0x1800, 0x1808, 0x180c, 0x1810 },
+};
+
+/*
+ * Set alternate parent rate to "rate" value or less.
+ *
+ * rate: Desired alt_parent rate, or 0 for max alt_parent rate
+ *
+ * Exynos850 doesn't have CPU clock divider in CMU_CPUCLx block (CMUREF divider
+ * doesn't affect CPU speed). So CPUCLx_SWITCH divider from CMU_TOP is used
+ * instead to adjust alternate parent speed.
+ *
+ * It's possible to use clk_set_max_rate() instead of this function, but it
+ * would set overly pessimistic rate values to alternate parent.
+ */
+static int exynos850_alt_parent_set_max_rate(const struct clk_hw *alt_parent,
+ unsigned long rate)
+{
+ struct clk_hw *clk_div, *clk_divp;
+ unsigned long divp_rate, div_rate, div;
+ int ret;
+
+ /* Divider from CMU_TOP */
+ clk_div = clk_hw_get_parent(alt_parent);
+ if (!clk_div)
+ return -ENOENT;
+ /* Divider's parent from CMU_TOP */
+ clk_divp = clk_hw_get_parent(clk_div);
+ if (!clk_divp)
+ return -ENOENT;
+ /* Divider input rate */
+ divp_rate = clk_hw_get_rate(clk_divp);
+ if (!divp_rate)
+ return -EINVAL;
+
+ /* Calculate new alt_parent rate for integer divider value */
+ if (rate == 0)
+ div = 1;
+ else
+ div = DIV_ROUND_UP(divp_rate, rate);
+ div_rate = DIV_ROUND_UP(divp_rate, div);
+ WARN_ON(div >= MAX_DIV);
+
+ /* alt_parent will propagate this change up to the divider */
+ ret = clk_set_rate(alt_parent->clk, div_rate);
+ if (ret)
+ return ret;
+ udelay(E850_DIV_MUX_STAB_TIME);
+
+ return 0;
+}
+
+/* Handler for pre-rate change notification from parent clock */
+static int exynos850_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk)
+{
+ const unsigned int shifts[4] = { 16, 12, 8, 4 }; /* E850_CPU_DIV0() */
+ const struct exynos850_cpuclk_regs * const regs = cpuclk->chip->regs;
+ const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
+ const struct clk_hw *alt_parent = cpuclk->alt_parent;
+ void __iomem *base = cpuclk->base;
+ unsigned long alt_prate = clk_hw_get_rate(alt_parent);
+ unsigned long flags;
+ u32 mux_reg;
+ size_t i;
+ int ret;
+
+ /* No actions are needed when switching to or from OSCCLK parent */
+ if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
+ return 0;
+
+ /* Find out the divider values to use for clock data */
+ while ((cfg_data->prate * 1000) != ndata->new_rate) {
+ if (cfg_data->prate == 0)
+ return -EINVAL;
+ cfg_data++;
+ }
+
+ /*
+ * If the old parent clock speed is less than the clock speed of
+ * the alternate parent, then it should be ensured that at no point
+ * the armclk speed is more than the old_prate until the dividers are
+ * set. Also workaround the issue of the dividers being set to lower
+ * values before the parent clock speed is set to new lower speed
+ * (this can result in too high speed of armclk output clocks).
+ */
+ if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
+ unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
+
+ ret = exynos850_alt_parent_set_max_rate(alt_parent, tmp_rate);
+ if (ret)
+ return ret;
+ }
+
+ spin_lock_irqsave(cpuclk->lock, flags);
+
+ /* Select the alternate parent */
+ mux_reg = readl(base + regs->mux);
+ writel(mux_reg | 1, base + regs->mux);
+ wait_until_mux_stable(base + regs->mux, 16, 1, 0);
+
+ /* Alternate parent is active now. Set the dividers */
+ for (i = 0; i < ARRAY_SIZE(shifts); ++i) {
+ unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf;
+ u32 val;
+
+ val = readl(base + regs->divs[i]);
+ val = (val & ~E850_DIV_RATIO_MASK) | div;
+ writel(val, base + regs->divs[i]);
+ wait_until_divider_stable(base + regs->divs[i], E850_BUSY_MASK);
+ }
+
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+
+ return 0;
+}
+
+/* Handler for post-rate change notification from parent clock */
+static int exynos850_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
+ struct exynos_cpuclk *cpuclk)
+{
+ const struct exynos850_cpuclk_regs * const regs = cpuclk->chip->regs;
+ const struct clk_hw *alt_parent = cpuclk->alt_parent;
+ void __iomem *base = cpuclk->base;
+ unsigned long flags;
+ u32 mux_reg;
+
+ /* No actions are needed when switching to or from OSCCLK parent */
+ if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
+ return 0;
+
+ spin_lock_irqsave(cpuclk->lock, flags);
+
+ /* Select main parent (PLL) for mux */
+ mux_reg = readl(base + regs->mux);
+ writel(mux_reg & ~1, base + regs->mux);
+ wait_until_mux_stable(base + regs->mux, 16, 1, 0);
+
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+
+ /* Set alt_parent rate back to max */
+ return exynos850_alt_parent_set_max_rate(alt_parent, 0);
+}
+
/* -------------------------------------------------------------------------- */
/* Common round rate callback usable for all types of CPU clocks */
@@ -459,6 +632,16 @@ static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = {
.pre_rate_cb = exynos5433_cpuclk_pre_rate_change,
.post_rate_cb = exynos5433_cpuclk_post_rate_change,
},
+ [CPUCLK_LAYOUT_E850_CL0] = {
+ .regs = &e850cl0_cpuclk_regs,
+ .pre_rate_cb = exynos850_cpuclk_pre_rate_change,
+ .post_rate_cb = exynos850_cpuclk_post_rate_change,
+ },
+ [CPUCLK_LAYOUT_E850_CL1] = {
+ .regs = &e850cl1_cpuclk_regs,
+ .pre_rate_cb = exynos850_cpuclk_pre_rate_change,
+ .post_rate_cb = exynos850_cpuclk_post_rate_change,
+ },
};
/* helper function to register a CPU clock */
diff --git a/drivers/clk/samsung/clk-cpu.h b/drivers/clk/samsung/clk-cpu.h
index 4382ab005ad3..892843611b0a 100644
--- a/drivers/clk/samsung/clk-cpu.h
+++ b/drivers/clk/samsung/clk-cpu.h
@@ -17,10 +17,14 @@
* enum exynos_cpuclk_layout - CPU clock registers layout compatibility
* @CPUCLK_LAYOUT_E4210: Exynos4210 compatible layout
* @CPUCLK_LAYOUT_E5433: Exynos5433 compatible layout
+ * @CPUCLK_LAYOUT_E850_CL0: Exynos850 cluster 0 compatible layout
+ * @CPUCLK_LAYOUT_E850_CL1: Exynos850 cluster 1 compatible layout
*/
enum exynos_cpuclk_layout {
CPUCLK_LAYOUT_E4210,
CPUCLK_LAYOUT_E5433,
+ CPUCLK_LAYOUT_E850_CL0,
+ CPUCLK_LAYOUT_E850_CL1,
};
/**
--
2.39.2
Define CPU cluster 0 and CPU cluster 1 CMUs, which generate CPU clocks,
and add corresponding CPU clocks to CPU nodes.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Add "for Exynos850" part to the commit title
arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 2ba67c3d0681..0706c8534ceb 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -93,6 +93,8 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
+ clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>;
+ clock-names = "cluster0_clk";
};
cpu1: cpu@1 {
device_type = "cpu";
@@ -117,6 +119,8 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
+ clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>;
+ clock-names = "cluster1_clk";
};
cpu5: cpu@101 {
device_type = "cpu";
@@ -254,6 +258,28 @@ cmu_peri: clock-controller@10030000 {
"dout_peri_uart", "dout_peri_ip";
};
+ cmu_cpucl1: clock-controller@10800000 {
+ compatible = "samsung,exynos850-cmu-cpucl1";
+ reg = <0x10800000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
+ <&cmu_top CLK_DOUT_CPUCL1_DBG>;
+ clock-names = "oscclk", "dout_cpucl1_switch",
+ "dout_cpucl1_dbg";
+ };
+
+ cmu_cpucl0: clock-controller@10900000 {
+ compatible = "samsung,exynos850-cmu-cpucl0";
+ reg = <0x10900000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
+ <&cmu_top CLK_DOUT_CPUCL0_DBG>;
+ clock-names = "oscclk", "dout_cpucl0_switch",
+ "dout_cpucl0_dbg";
+ };
+
cmu_g3d: clock-controller@11400000 {
compatible = "samsung,exynos850-cmu-g3d";
reg = <0x11400000 0x8000>;
--
2.39.2
Some ARM64 Exynos chips are capable to control PLL clocks automatically.
For those chips, whether the PLL is controlled automatically or manually
is chosen in PLL_CON1 register with next bits:
[28] ENABLE_AUTOMATIC_CLKGATING
[1] MANUAL_PLL_CTRL
[0] AUTO_PLL_CTRL
The bl2 bootloader sets 0x10000001 value for some PLL_CON1 registers,
which means any attempt to control those PLLs manually (e.g.
disabling/enabling those PLLs or changing MUX parent clocks) would lead
to PLL lock timeout with error message like this:
Could not lock PLL ...
At the moment, all Samsung clock drivers implement manual clock control.
So in order to make it possible to control PLLs, corresponding PLL_CON1
registers should be set to 0x2 first.
Some older ARM64 chips don't implement the automatic clock control
though. It also might be desirable to configure some PLLs for manual
control, while keeping the default configuration for the rest. So it'd
convenient to choose this PLL mode for each CMU separately. Introduce
manual_plls field to CMU structure to choose the PLL control mode.
Because it'll be initialized with "false" in all existing CMU
structures by default, it won't affect any existing clock drivers,
allowing for this feature to be enabled gradually when it's needed with
no change for the rest of users. In case .manual_plls is set, set
PLL_CON1 registers to manual control, akin to what's already done for
gate clocks in exynos_arm64_init_clocks(). Of course, PLL_CON1 registers
should be added to corresponding struct samsung_cmu_info::clk_regs array
to make sure they get initialized.
No functional change. This patch adds a feature, but doesn't enable it
for any users.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-exynos-arm64.c | 44 +++++++++++++++++---------
drivers/clk/samsung/clk.h | 4 +++
2 files changed, 33 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos-arm64.c b/drivers/clk/samsung/clk-exynos-arm64.c
index 6fb7194df7ab..55490209b9a9 100644
--- a/drivers/clk/samsung/clk-exynos-arm64.c
+++ b/drivers/clk/samsung/clk-exynos-arm64.c
@@ -25,6 +25,19 @@
#define GATE_OFF_START 0x2000
#define GATE_OFF_END 0x2fff
+/* PLL CON register offsets range */
+#define PLL_CON_START 0x100
+#define PLL_CON_END 0x600
+
+/* PLL register bits */
+#define PLL_CON1_MANUAL BIT(1)
+
+/* Helper macros to check for particular clock regiter by its offset */
+#define IS_GATE_REG(o) ((o) >= GATE_OFF_START && (o) <= GATE_OFF_END)
+#define IS_PLL_CONx_REG(o) ((o) >= PLL_CON_START && (o) <= PLL_CON_END)
+#define IS_PLL_CON1_REG(o) \
+ (IS_PLL_CONx_REG(o) && ((o) & 0xf) == 0x4 && !((o) & 0x10))
+
struct exynos_arm64_cmu_data {
struct samsung_clk_reg_dump *clk_save;
unsigned int nr_clk_save;
@@ -40,15 +53,16 @@ struct exynos_arm64_cmu_data {
/**
* exynos_arm64_init_clocks - Set clocks initial configuration
- * @np: CMU device tree node with "reg" property (CMU addr)
- * @reg_offs: Register offsets array for clocks to init
- * @reg_offs_len: Number of register offsets in reg_offs array
+ * @np: CMU device tree node with "reg" property (CMU addr)
+ * @cmu: CMU data
*
- * Set manual control mode for all gate clocks.
+ * Set manual control mode for all gate and PLL clocks.
*/
static void __init exynos_arm64_init_clocks(struct device_node *np,
- const unsigned long *reg_offs, size_t reg_offs_len)
+ const struct samsung_cmu_info *cmu)
{
+ const unsigned long *reg_offs = cmu->clk_regs;
+ size_t reg_offs_len = cmu->nr_clk_regs;
void __iomem *reg_base;
size_t i;
@@ -60,14 +74,14 @@ static void __init exynos_arm64_init_clocks(struct device_node *np,
void __iomem *reg = reg_base + reg_offs[i];
u32 val;
- /* Modify only gate clock registers */
- if (reg_offs[i] < GATE_OFF_START || reg_offs[i] > GATE_OFF_END)
- continue;
-
- val = readl(reg);
- val |= GATE_MANUAL;
- val &= ~GATE_ENABLE_HWACG;
- writel(val, reg);
+ if (cmu->manual_plls && IS_PLL_CON1_REG(reg_offs[i])) {
+ writel(PLL_CON1_MANUAL, reg);
+ } else if (IS_GATE_REG(reg_offs[i])) {
+ val = readl(reg);
+ val |= GATE_MANUAL;
+ val &= ~GATE_ENABLE_HWACG;
+ writel(val, reg);
+ }
}
iounmap(reg_base);
@@ -177,7 +191,7 @@ void __init exynos_arm64_register_cmu(struct device *dev,
pr_err("%s: could not enable bus clock %s; err = %d\n",
__func__, cmu->clk_name, err);
- exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
+ exynos_arm64_init_clocks(np, cmu);
samsung_cmu_register_one(np, cmu);
}
@@ -224,7 +238,7 @@ int __init exynos_arm64_register_cmu_pm(struct platform_device *pdev,
__func__, cmu->clk_name, ret);
if (set_manual)
- exynos_arm64_init_clocks(np, cmu->clk_regs, cmu->nr_clk_regs);
+ exynos_arm64_init_clocks(np, cmu);
reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg_base))
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index a763309e6f12..a70bd7cce39f 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -330,6 +330,7 @@ struct samsung_clock_reg_cache {
* @suspend_regs: list of clock registers to set before suspend
* @nr_suspend_regs: count of clock registers in @suspend_regs
* @clk_name: name of the parent clock needed for CMU register access
+ * @manual_plls: Enable manual control for PLL clocks
*/
struct samsung_cmu_info {
const struct samsung_pll_clock *pll_clks;
@@ -354,6 +355,9 @@ struct samsung_cmu_info {
const struct samsung_clk_reg_dump *suspend_regs;
unsigned int nr_suspend_regs;
const char *clk_name;
+
+ /* ARM64 Exynos CMUs */
+ bool manual_plls;
};
struct samsung_clk_provider *samsung_clk_init(struct device *dev,
--
2.39.2
Implement support for CPU clock management units:
- CMU_CPUCL0: clocks for cluster 0: 4 x Cortex-A55 (cpu0..cpu3)
- CMU_CPUCL1: clocks for cluster 1: 4 x Cortex-A55 (cpu4..cpu7)
CPU PLLs are generating main CPU clocks for each cluster, and there are
alternate ("switch") clocks that can be used temporarily while
re-configuring the PLL for a new rate. ACLK, ATCLK, PCLKDBG and
PERIPHCLK clocks are driving corresponding buses. CLK_CLUSTERx_SCLK are
actual leaf CPU clocks and should be used to change CPU rates. Also some
CoreSight clocks can be derived from DBG_USER (debug clock).
PLL table was extracted from ECT table. ECT stands for "Exynos
Characteristic Table", it's a Samsung specific binary data populated by
BL2 bootloader in RAM at 0x90000000 address, containing PLL tables for
various CMUs and other hardware specific information.
The particular PLL type used in CMU_CPUCL0 and CMU_CPUCL1 (pll0822x) is
an integer PLL with middle FVCO. The equation to calculate its output
rate is:
fout = fin * M / (P*2^S)
where:
fin = 26 MHz (OSCCLK frequency)
M = 64..1023
P = 1..63
S = 0..6
The PLL table tries to keep "P" value low to reduce the locking time,
which for pll0822x is "t = P * 150" (in OSCCLK cycles).
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- none
drivers/clk/samsung/clk-exynos850.c | 440 +++++++++++++++++++++++++++-
1 file changed, 439 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 82cfa22c0788..6215471c4ac6 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -14,13 +14,16 @@
#include <dt-bindings/clock/exynos850.h>
#include "clk.h"
+#include "clk-cpu.h"
#include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */
-#define CLKS_NR_TOP (CLK_DOUT_G3D_SWITCH + 1)
+#define CLKS_NR_TOP (CLK_DOUT_CPUCL1_SWITCH + 1)
#define CLKS_NR_APM (CLK_GOUT_SYSREG_APM_PCLK + 1)
#define CLKS_NR_AUD (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
#define CLKS_NR_CMGP (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
+#define CLKS_NR_CPUCL0 (CLK_CLUSTER0_SCLK + 1)
+#define CLKS_NR_CPUCL1 (CLK_CLUSTER1_SCLK + 1)
#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1)
#define CLKS_NR_HSI (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
#define CLKS_NR_IS (CLK_GOUT_IS_SYSREG_PCLK + 1)
@@ -47,6 +50,10 @@
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
#define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG 0x102c
+#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1030
#define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034
#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
@@ -69,6 +76,10 @@
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
#define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c
+#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1830
+#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1834
+#define CLK_CON_DIV_CLKCMU_CPUCL1_DBG 0x1838
+#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
#define CLK_CON_DIV_CLKCMU_DPU 0x1840
#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
@@ -97,6 +108,10 @@
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
#define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG 0x2034
+#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2038
#define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c
#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
@@ -130,6 +145,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_DPU,
CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
@@ -152,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
CLK_CON_DIV_CLKCMU_CORE_SSS,
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
+ CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_DIV_CLKCMU_CPUCL1_DBG,
+ CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
CLK_CON_DIV_CLKCMU_DPU,
CLK_CON_DIV_CLKCMU_G3D_SWITCH,
CLK_CON_DIV_CLKCMU_HSI_BUS,
@@ -180,6 +203,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
CLK_CON_GAT_GATE_CLKCMU_CORE_SSS,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG,
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_DPU,
CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
@@ -234,6 +261,14 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2",
"oscclk", "oscclk" };
PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL0 */
+PNAME(mout_cpucl0_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
+ "dout_shared0_div2", "dout_shared1_div2" };
+PNAME(mout_cpucl0_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_CPUCL1 */
+PNAME(mout_cpucl1_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
+ "dout_shared0_div2", "dout_shared1_div2" };
+PNAME(mout_cpucl1_dbg_p) = { "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */
PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
@@ -300,6 +335,18 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CORE_SSS, "mout_core_sss", mout_core_sss_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, 0, 2),
+ /* CPUCL0 */
+ MUX(CLK_MOUT_CPUCL0_DBG, "mout_cpucl0_dbg", mout_cpucl0_dbg_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1),
+ MUX(CLK_MOUT_CPUCL0_SWITCH, "mout_cpucl0_switch", mout_cpucl0_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 2),
+
+ /* CPUCL1 */
+ MUX(CLK_MOUT_CPUCL1_DBG, "mout_cpucl1_dbg", mout_cpucl1_dbg_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_DBG, 0, 1),
+ MUX(CLK_MOUT_CPUCL1_SWITCH, "mout_cpucl1_switch", mout_cpucl1_switch_p,
+ CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2),
+
/* DPU */
MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p,
CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2),
@@ -378,6 +425,18 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CORE_SSS, "dout_core_sss", "gout_core_sss",
CLK_CON_DIV_CLKCMU_CORE_SSS, 0, 4),
+ /* CPUCL0 */
+ DIV(CLK_DOUT_CPUCL0_DBG, "dout_cpucl0_dbg", "gout_cpucl0_dbg",
+ CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
+ DIV(CLK_DOUT_CPUCL0_SWITCH, "dout_cpucl0_switch", "gout_cpucl0_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
+
+ /* CPUCL1 */
+ DIV(CLK_DOUT_CPUCL1_DBG, "dout_cpucl1_dbg", "gout_cpucl1_dbg",
+ CLK_CON_DIV_CLKCMU_CPUCL1_DBG, 0, 3),
+ DIV(CLK_DOUT_CPUCL1_SWITCH, "dout_cpucl1_switch", "gout_cpucl1_switch",
+ CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
+
/* DPU */
DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu",
CLK_CON_DIV_CLKCMU_DPU, 0, 4),
@@ -442,6 +501,18 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
+ /* CPUCL0 */
+ GATE(CLK_GOUT_CPUCL0_DBG, "gout_cpucl0_dbg", "mout_cpucl0_dbg",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0),
+ GATE(CLK_GOUT_CPUCL0_SWITCH, "gout_cpucl0_switch", "mout_cpucl0_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0),
+
+ /* CPUCL1 */
+ GATE(CLK_GOUT_CPUCL1_DBG, "gout_cpucl1_dbg", "mout_cpucl1_dbg",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_DBG, 21, 0, 0),
+ GATE(CLK_GOUT_CPUCL1_SWITCH, "gout_cpucl1_switch", "mout_cpucl1_switch",
+ CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0),
+
/* DPU */
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
@@ -1030,6 +1101,373 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
.clk_name = "gout_clkcmu_cmgp_bus",
};
+/* ---- CMU_CPUCL0 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_CPUCL0 (0x10900000) */
+#define PLL_LOCKTIME_PLL_CPUCL0 0x0000
+#define PLL_CON0_PLL_CPUCL0 0x0100
+#define PLL_CON1_PLL_CPUCL0 0x0104
+#define PLL_CON3_PLL_CPUCL0 0x010c
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0610
+#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x100c
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK 0x1808
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x180c
+#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK 0x1810
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x1814
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1818
+#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x181c
+#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK 0x2000
+#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK 0x2004
+#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK 0x2008
+#define CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK 0x200c
+#define CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK 0x2010
+#define CLK_CON_GAT_GATE_CLK_CPUCL0_CPU 0x2020
+
+static const unsigned long cpucl0_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CPUCL0,
+ PLL_CON0_PLL_CPUCL0,
+ PLL_CON1_PLL_CPUCL0,
+ PLL_CON3_PLL_CPUCL0,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
+ CLK_CON_MUX_MUX_CLK_CPUCL0_PLL,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG,
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK,
+ CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF,
+ CLK_CON_DIV_DIV_CLK_CPUCL0_CPU,
+ CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK,
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK,
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK,
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK,
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK,
+ CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK,
+ CLK_CON_GAT_GATE_CLK_CPUCL0_CPU,
+};
+
+/* List of parent clocks for Muxes in CMU_CPUCL0 */
+PNAME(mout_pll_cpucl0_p) = { "oscclk", "fout_cpucl0_pll" };
+PNAME(mout_cpucl0_switch_user_p) = { "oscclk", "dout_cpucl0_switch" };
+PNAME(mout_cpucl0_dbg_user_p) = { "oscclk", "dout_cpucl0_dbg" };
+PNAME(mout_cpucl0_pll_p) = { "mout_pll_cpucl0",
+ "mout_cpucl0_switch_user" };
+
+static const struct samsung_pll_rate_table cpu_pll_rates[] __initconst = {
+ PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
+ PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
+ PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
+ PLL_35XX_RATE(26 * MHZ, 949000000U, 219, 3, 1),
+ PLL_35XX_RATE(26 * MHZ, 806000000U, 186, 3, 1),
+ PLL_35XX_RATE(26 * MHZ, 650000000U, 150, 3, 1),
+ PLL_35XX_RATE(26 * MHZ, 546000000U, 252, 3, 2),
+ PLL_35XX_RATE(26 * MHZ, 442000000U, 204, 3, 2),
+ PLL_35XX_RATE(26 * MHZ, 351000000U, 162, 3, 2),
+ PLL_35XX_RATE(26 * MHZ, 247000000U, 114, 3, 2),
+ PLL_35XX_RATE(26 * MHZ, 182000000U, 168, 3, 3),
+ PLL_35XX_RATE(26 * MHZ, 130000000U, 120, 3, 3),
+};
+
+static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst = {
+ PLL(pll_0822x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk",
+ PLL_LOCKTIME_PLL_CPUCL0, PLL_CON3_PLL_CPUCL0, cpu_pll_rates),
+};
+
+static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst = {
+ MUX_F(CLK_MOUT_PLL_CPUCL0, "mout_pll_cpucl0", mout_pll_cpucl0_p,
+ PLL_CON0_PLL_CPUCL0, 4, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+ MUX_F(CLK_MOUT_CPUCL0_SWITCH_USER, "mout_cpucl0_switch_user",
+ mout_cpucl0_switch_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX(CLK_MOUT_CPUCL0_DBG_USER, "mout_cpucl0_dbg_user",
+ mout_cpucl0_dbg_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1),
+ MUX_F(CLK_MOUT_CPUCL0_PLL, "mout_cpucl0_pll", mout_cpucl0_pll_p,
+ CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock cpucl0_div_clks[] __initconst = {
+ DIV_F(CLK_DOUT_CPUCL0_CPU, "dout_cpucl0_cpu", "mout_cpucl0_pll",
+ CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 1,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CPUCL0_CMUREF, "dout_cpucl0_cmuref", "dout_cpucl0_cpu",
+ CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CPUCL0_PCLK, "dout_cpucl0_pclk", "dout_cpucl0_cpu",
+ CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+
+ /* EMBEDDED_CMU_CPUCL0 */
+ DIV_F(CLK_DOUT_CLUSTER0_ACLK, "dout_cluster0_aclk", "gout_cluster0_cpu",
+ CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CLUSTER0_ATCLK, "dout_cluster0_atclk",
+ "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CLUSTER0_PCLKDBG, "dout_cluster0_pclkdbg",
+ "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CLUSTER0_PERIPHCLK, "dout_cluster0_periphclk",
+ "gout_cluster0_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER0_PERIPHCLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+};
+
+static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_CPUCL0_CMU_CPUCL0_PCLK, "gout_cpucl0_cmu_cpucl0_pclk",
+ "dout_cpucl0_pclk",
+ CLK_CON_GAT_CLK_CPUCL0_CMU_CPUCL0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+
+ /* EMBEDDED_CMU_CPUCL0 */
+ GATE(CLK_GOUT_CLUSTER0_CPU, "gout_cluster0_cpu", "dout_cpucl0_cpu",
+ CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER0_SCLK, "gout_cluster0_sclk", "gout_cluster0_cpu",
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_SCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER0_ATCLK, "gout_cluster0_atclk",
+ "dout_cluster0_atclk",
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER0_PERIPHCLK, "gout_cluster0_periphclk",
+ "dout_cluster0_periphclk",
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PERIPHCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER0_PCLK, "gout_cluster0_pclk",
+ "dout_cluster0_pclkdbg",
+ CLK_CON_GAT_CLK_CPUCL0_CLUSTER0_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+/*
+ * Each parameter is going to be written into the corresponding DIV register. So
+ * the actual divider value for each parameter will be 1/(param+1). All these
+ * parameters must be in the range of 0..15, as the divider range for all of
+ * these DIV clocks is 1..16. The default values for these dividers is
+ * (1, 3, 3, 1).
+ */
+#define E850_CPU_DIV0(aclk, atclk, pclkdbg, periphclk) \
+ (((aclk) << 16) | ((atclk) << 12) | ((pclkdbg) << 8) | \
+ ((periphclk) << 4))
+
+static const struct exynos_cpuclk_cfg_data exynos850_cluster_clk_d[] __initconst
+= {
+ { 2210000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 2106000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 2002000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1846000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1742000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1586000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1456000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1300000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1157000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 1053000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 949000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 806000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 650000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 546000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 442000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 351000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 247000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 182000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 130000, E850_CPU_DIV0(1, 3, 3, 1) },
+ { 0 }
+};
+
+static const struct samsung_cpu_clock cpucl0_cpu_clks[] __initconst = {
+ CPU_CLK(CLK_CLUSTER0_SCLK, "cluster0_clk", CLK_MOUT_PLL_CPUCL0,
+ CLK_MOUT_CPUCL0_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL0,
+ exynos850_cluster_clk_d),
+};
+
+static const struct samsung_cmu_info cpucl0_cmu_info __initconst = {
+ .pll_clks = cpucl0_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cpucl0_pll_clks),
+ .mux_clks = cpucl0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cpucl0_mux_clks),
+ .div_clks = cpucl0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cpucl0_div_clks),
+ .gate_clks = cpucl0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cpucl0_gate_clks),
+ .cpu_clks = cpucl0_cpu_clks,
+ .nr_cpu_clks = ARRAY_SIZE(cpucl0_cpu_clks),
+ .nr_clk_ids = CLKS_NR_CPUCL0,
+ .clk_regs = cpucl0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cpucl0_clk_regs),
+ .clk_name = "dout_cpucl0_switch",
+ .manual_plls = true,
+};
+
+static void __init exynos850_cmu_cpucl0_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info);
+}
+
+/* Register CMU_CPUCL0 early, as CPU clocks should be available ASAP */
+CLK_OF_DECLARE(exynos850_cmu_cpucl0, "samsung,exynos850-cmu-cpucl0",
+ exynos850_cmu_cpucl0_init);
+
+/* ---- CMU_CPUCL1 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_CPUCL1 (0x10800000) */
+#define PLL_LOCKTIME_PLL_CPUCL1 0x0000
+#define PLL_CON0_PLL_CPUCL1 0x0100
+#define PLL_CON1_PLL_CPUCL1 0x0104
+#define PLL_CON3_PLL_CPUCL1 0x010c
+#define PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0610
+#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000
+#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800
+#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK 0x1808
+#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG 0x180c
+#define CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK 0x1810
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x1814
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1818
+#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x181c
+#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK 0x2000
+#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK 0x2004
+#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK 0x2008
+#define CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK 0x200c
+#define CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK 0x2010
+#define CLK_CON_GAT_GATE_CLK_CPUCL1_CPU 0x2020
+
+static const unsigned long cpucl1_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_CPUCL1,
+ PLL_CON0_PLL_CPUCL1,
+ PLL_CON1_PLL_CPUCL1,
+ PLL_CON3_PLL_CPUCL1,
+ PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER,
+ PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER,
+ CLK_CON_MUX_MUX_CLK_CPUCL1_PLL,
+ CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK,
+ CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG,
+ CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK,
+ CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF,
+ CLK_CON_DIV_DIV_CLK_CPUCL1_CPU,
+ CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK,
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK,
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK,
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK,
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK,
+ CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK,
+ CLK_CON_GAT_GATE_CLK_CPUCL1_CPU,
+};
+
+/* List of parent clocks for Muxes in CMU_CPUCL0 */
+PNAME(mout_pll_cpucl1_p) = { "oscclk", "fout_cpucl1_pll" };
+PNAME(mout_cpucl1_switch_user_p) = { "oscclk", "dout_cpucl1_switch" };
+PNAME(mout_cpucl1_dbg_user_p) = { "oscclk", "dout_cpucl1_dbg" };
+PNAME(mout_cpucl1_pll_p) = { "mout_pll_cpucl1",
+ "mout_cpucl1_switch_user" };
+
+static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst = {
+ PLL(pll_0822x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk",
+ PLL_LOCKTIME_PLL_CPUCL1, PLL_CON3_PLL_CPUCL1, cpu_pll_rates),
+};
+
+static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst = {
+ MUX_F(CLK_MOUT_PLL_CPUCL1, "mout_pll_cpucl1", mout_pll_cpucl1_p,
+ PLL_CON0_PLL_CPUCL1, 4, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
+ MUX_F(CLK_MOUT_CPUCL1_SWITCH_USER, "mout_cpucl1_switch_user",
+ mout_cpucl1_switch_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
+ MUX(CLK_MOUT_CPUCL1_DBG_USER, "mout_cpucl1_dbg_user",
+ mout_cpucl1_dbg_user_p,
+ PLL_CON0_MUX_CLKCMU_CPUCL1_DBG_USER, 4, 1),
+ MUX_F(CLK_MOUT_CPUCL1_PLL, "mout_cpucl1_pll", mout_cpucl1_pll_p,
+ CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1, CLK_SET_RATE_PARENT, 0),
+};
+
+static const struct samsung_div_clock cpucl1_div_clks[] __initconst = {
+ DIV_F(CLK_DOUT_CPUCL1_CPU, "dout_cpucl1_cpu", "mout_cpucl1_pll",
+ CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0, 1,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CPUCL1_CMUREF, "dout_cpucl1_cmuref", "dout_cpucl1_cpu",
+ CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 3,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CPUCL1_PCLK, "dout_cpucl1_pclk", "dout_cpucl1_cpu",
+ CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+
+ /* EMBEDDED_CMU_CPUCL1 */
+ DIV_F(CLK_DOUT_CLUSTER1_ACLK, "dout_cluster1_aclk", "gout_cluster1_cpu",
+ CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CLUSTER1_ATCLK, "dout_cluster1_atclk",
+ "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CLUSTER1_PCLKDBG, "dout_cluster1_pclkdbg",
+ "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+ DIV_F(CLK_DOUT_CLUSTER1_PERIPHCLK, "dout_cluster1_periphclk",
+ "gout_cluster1_cpu", CLK_CON_DIV_DIV_CLK_CLUSTER1_PERIPHCLK, 0, 4,
+ CLK_GET_RATE_NOCACHE, CLK_DIVIDER_READ_ONLY),
+};
+
+static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_CPUCL1_CMU_CPUCL1_PCLK, "gout_cpucl1_cmu_cpucl1_pclk",
+ "dout_cpucl1_pclk",
+ CLK_CON_GAT_CLK_CPUCL1_CMU_CPUCL1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+
+ /* EMBEDDED_CMU_CPUCL1 */
+ GATE(CLK_GOUT_CLUSTER1_CPU, "gout_cluster1_cpu", "dout_cpucl1_cpu",
+ CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER1_SCLK, "gout_cluster1_sclk", "gout_cluster1_cpu",
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_SCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER1_ATCLK, "gout_cluster1_atclk",
+ "dout_cluster1_atclk",
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_ATCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER1_PERIPHCLK, "gout_cluster1_periphclk",
+ "dout_cluster1_periphclk",
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PERIPHCLK, 21,
+ CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_CLUSTER1_PCLK, "gout_cluster1_pclk",
+ "dout_cluster1_pclkdbg",
+ CLK_CON_GAT_CLK_CPUCL1_CLUSTER1_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cpu_clock cpucl1_cpu_clks[] __initconst = {
+ CPU_CLK(CLK_CLUSTER1_SCLK, "cluster1_clk", CLK_MOUT_PLL_CPUCL1,
+ CLK_MOUT_CPUCL1_SWITCH_USER, 0, 0x0, CPUCLK_LAYOUT_E850_CL1,
+ exynos850_cluster_clk_d),
+};
+
+static const struct samsung_cmu_info cpucl1_cmu_info __initconst = {
+ .pll_clks = cpucl1_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(cpucl1_pll_clks),
+ .mux_clks = cpucl1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cpucl1_mux_clks),
+ .div_clks = cpucl1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cpucl1_div_clks),
+ .gate_clks = cpucl1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cpucl1_gate_clks),
+ .cpu_clks = cpucl1_cpu_clks,
+ .nr_cpu_clks = ARRAY_SIZE(cpucl1_cpu_clks),
+ .nr_clk_ids = CLKS_NR_CPUCL1,
+ .clk_regs = cpucl1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cpucl1_clk_regs),
+ .clk_name = "dout_cpucl1_switch",
+ .manual_plls = true,
+};
+
+static void __init exynos850_cmu_cpucl1_init(struct device_node *np)
+{
+ exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info);
+}
+
+/* Register CMU_CPUCL1 early, as CPU clocks should be available ASAP */
+CLK_OF_DECLARE(exynos850_cmu_cpucl1, "samsung,exynos850-cmu-cpucl1",
+ exynos850_cmu_cpucl1_init);
+
/* ---- CMU_G3D ------------------------------------------------------------- */
/* Register Offset definitions for CMU_G3D (0x11400000) */
--
2.39.2