The ISP supports both CSI and parallel interfaces, where port 0
corresponds to the former and port 1 corresponds to the latter. Since
the i.MX8MP's ISPs are connected by the parallel interface to the CSI
receiver, set them both to port 1.
Signed-off-by: Paul Elder <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index c9a610ba4836..25579d4c58f2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
};
};
+ isp_0: isp@32e10000 {
+ compatible = "fsl,imx8mp-isp";
+ reg = <0x32e10000 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "isp", "aclk", "hclk";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+ fsl,blk-ctrl = <&media_blk_ctrl 0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ isp_1: isp@32e20000 {
+ compatible = "fsl,imx8mp-isp";
+ reg = <0x32e20000 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "isp", "aclk", "hclk";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+ fsl,blk-ctrl = <&media_blk_ctrl 1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
dewarp: dwe@32e30000 {
compatible = "nxp,imx8mp-dw100";
reg = <0x32e30000 0x10000>;
--
2.39.2
Hi Paul,
Am Mittwoch, 29. November 2023, 10:31:12 CET schrieb Paul Elder:
> The ISP supports both CSI and parallel interfaces, where port 0
> corresponds to the former and port 1 corresponds to the latter. Since
> the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> receiver, set them both to port 1.
>
> Signed-off-by: Paul Elder <[email protected]>
Thanks for the patch. I'm running with for a while now.
Reviewed-by: Alexander Stein <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> c9a610ba4836..25579d4c58f2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
> };
> };
>
> + isp_0: isp@32e10000 {
> + compatible = "fsl,imx8mp-isp";
> + reg = <0x32e10000 0x10000>;
> + interrupts = <GIC_SPI 74
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
IMX8MP_CLK_MEDIA_ISP_ROOT>,
> + <&clk
IMX8MP_CLK_MEDIA_AXI_ROOT>,
> + <&clk
IMX8MP_CLK_MEDIA_APB_ROOT>;
> + clock-names = "isp", "aclk", "hclk";
> + assigned-clocks = <&clk
IMX8MP_CLK_MEDIA_ISP>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + power-domains = <&media_blk_ctrl
IMX8MP_MEDIABLK_PD_ISP>;
> + fsl,blk-ctrl = <&media_blk_ctrl 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + isp_1: isp@32e20000 {
> + compatible = "fsl,imx8mp-isp";
> + reg = <0x32e20000 0x10000>;
> + interrupts = <GIC_SPI 75
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk
IMX8MP_CLK_MEDIA_ISP_ROOT>,
> + <&clk
IMX8MP_CLK_MEDIA_AXI_ROOT>,
> + <&clk
IMX8MP_CLK_MEDIA_APB_ROOT>;
> + clock-names = "isp", "aclk", "hclk";
> + assigned-clocks = <&clk
IMX8MP_CLK_MEDIA_ISP>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + power-domains = <&media_blk_ctrl
IMX8MP_MEDIABLK_PD_ISP>;
> + fsl,blk-ctrl = <&media_blk_ctrl 1>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> dewarp: dwe@32e30000 {
> compatible = "nxp,imx8mp-dw100";
> reg = <0x32e30000 0x10000>;
--
TQ-Systems GmbH | M?hlstra?e 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht M?nchen, HRB 105018
Gesch?ftsf?hrer: Detlef Schneider, R?diger Stahl, Stefan Schneider
http://www.tq-group.com/
Hi Paul,
On Wed, Nov 29, 2023 at 6:31 AM Paul Elder <[email protected]> wrote:
> + isp_0: isp@32e10000 {
> + compatible = "fsl,imx8mp-isp";
This compatible string is still not present in today's linux-next.
Will it be merged soon?
On Wed, Nov 29, 2023 at 5:59 AM Fabio Estevam <[email protected]> wrote:
>
> Hi Paul,
>
> On Wed, Nov 29, 2023 at 6:31 AM Paul Elder <[email protected]> wrote:
>
> > + isp_0: isp@32e10000 {
> > + compatible = "fsl,imx8mp-isp";
>
> This compatible string is still not present in today's linux-next.
>
> Will it be merged soon?
Fabio,
Paul posted a series to the media mailing list adding support for the
i.MX8MP ISP:
https://patchwork.linuxtv.org/project/linux-media/list/?series=11776
I am guessing it'll have to go through the review process. I was CC'd
because I did some previous testing before. I have a Sony imx219 that
works in 4-lane mode. I'm likely to review and test tonight or
tomorrow. I am guessing he posted the DTS changes via a different
series since they usually go through Shawn's branch instead of the
media one.
Hopefully that helps.
adam
Hi Adam,
On Wed, Nov 29, 2023 at 10:49 AM Adam Ford <[email protected]> wrote:
> Fabio,
>
> Paul posted a series to the media mailing list adding support for the
> i.MX8MP ISP:
>
> https://patchwork.linuxtv.org/project/linux-media/list/?series=11776
Thanks for the clarification. It's great to see this series.
Cheers
On Wed, Nov 29, 2023 at 07:49:31AM -0600, Adam Ford wrote:
> On Wed, Nov 29, 2023 at 5:59 AM Fabio Estevam <[email protected]> wrote:
> >
> > Hi Paul,
> >
> > On Wed, Nov 29, 2023 at 6:31 AM Paul Elder <[email protected]> wrote:
> >
> > > + isp_0: isp@32e10000 {
> > > + compatible = "fsl,imx8mp-isp";
> >
> > This compatible string is still not present in today's linux-next.
> >
> > Will it be merged soon?
>
> Fabio,
>
> Paul posted a series to the media mailing list adding support for the
> i.MX8MP ISP:
>
> https://patchwork.linuxtv.org/project/linux-media/list/?series=11776
Paul, this is the kind of information that needs to go to the cover
letter, along with anything else that reviewers may need to review the
patches. Otherwise, as Fabio pointed out, it gets confusing. Please
expand the cover letter for the next iterations of the series.
> I am guessing it'll have to go through the review process. I was CC'd
> because I did some previous testing before. I have a Sony imx219 that
> works in 4-lane mode. I'm likely to review and test tonight or
> tomorrow. I am guessing he posted the DTS changes via a different
> series since they usually go through Shawn's branch instead of the
> media one.
>
> Hopefully that helps.
--
Regards,
Laurent Pinchart
On Wed, Nov 29, 2023 at 3:31 AM Paul Elder <paul.elder@ideasonboardcom> wrote:
>
> The ISP supports both CSI and parallel interfaces, where port 0
> corresponds to the former and port 1 corresponds to the latter. Since
> the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> receiver, set them both to port 1.
>
> Signed-off-by: Paul Elder <[email protected]>
Paul, are you able to resend this now that the driver part has been
merged into the main branch?
If you can't, I can resend it on your behalf.
thanks,
adam
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index c9a610ba4836..25579d4c58f2 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
> };
> };
>
> + isp_0: isp@32e10000 {
> + compatible = "fsl,imx8mp-isp";
> + reg = <0x32e10000 0x10000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> + clock-names = "isp", "aclk", "hclk";
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> + fsl,blk-ctrl = <&media_blk_ctrl 0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> + isp_1: isp@32e20000 {
> + compatible = "fsl,imx8mp-isp";
> + reg = <0x32e20000 0x10000>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> + clock-names = "isp", "aclk", "hclk";
> + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> + fsl,blk-ctrl = <&media_blk_ctrl 1>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> dewarp: dwe@32e30000 {
> compatible = "nxp,imx8mp-dw100";
> reg = <0x32e30000 0x10000>;
> --
> 2.39.2
>
On Mon, Mar 25, 2024 at 10:14 AM Laurent Pinchart
<[email protected]> wrote:
>
> Hi Adam,
>
> On Wed, Mar 20, 2024 at 07:35:46AM -0500, Adam Ford wrote:
> > On Wed, Nov 29, 2023 at 3:31 AM Paul Elder wrote:
> > >
> > > The ISP supports both CSI and parallel interfaces, where port 0
> > > corresponds to the former and port 1 corresponds to the latter. Since
> > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > > receiver, set them both to port 1.
> > >
> > > Signed-off-by: Paul Elder <[email protected]>
> >
> > Paul, are you able to resend this now that the driver part has been
> > merged into the main branch?
> >
> > If you can't, I can resend it on your behalf.
>
> I've just sent a v2, you're on CC.
Thanks!
adam
>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++
> > > 1 file changed, 50 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index c9a610ba4836..25579d4c58f2 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
> > > };
> > > };
> > >
> > > + isp_0: isp@32e10000 {
> > > + compatible = "fsl,imx8mp-isp";
> > > + reg = <0x32e10000 0x10000>;
> > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > + clock-names = "isp", "aclk", "hclk";
> > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > > + assigned-clock-rates = <500000000>;
> > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > > + fsl,blk-ctrl = <&media_blk_ctrl 0>;
> > > + status = "disabled";
> > > +
> > > + ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port@1 {
> > > + reg = <1>;
> > > + };
> > > + };
> > > + };
> > > +
> > > + isp_1: isp@32e20000 {
> > > + compatible = "fsl,imx8mp-isp";
> > > + reg = <0x32e20000 0x10000>;
> > > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > + clock-names = "isp", "aclk", "hclk";
> > > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> > > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > > + assigned-clock-rates = <500000000>;
> > > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > > + fsl,blk-ctrl = <&media_blk_ctrl 1>;
> > > + status = "disabled";
> > > +
> > > + ports {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + port@1 {
> > > + reg = <1>;
> > > + };
> > > + };
> > > + };
> > > +
> > > dewarp: dwe@32e30000 {
> > > compatible = "nxp,imx8mp-dw100";
> > > reg = <0x32e30000 0x10000>;
>
> --
> Regards,
>
> Laurent Pinchart
Hi Adam,
On Wed, Mar 20, 2024 at 07:35:46AM -0500, Adam Ford wrote:
> On Wed, Nov 29, 2023 at 3:31 AM Paul Elder wrote:
> >
> > The ISP supports both CSI and parallel interfaces, where port 0
> > corresponds to the former and port 1 corresponds to the latter. Since
> > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > receiver, set them both to port 1.
> >
> > Signed-off-by: Paul Elder <[email protected]>
>
> Paul, are you able to resend this now that the driver part has been
> merged into the main branch?
>
> If you can't, I can resend it on your behalf.
I've just sent a v2, you're on CC.
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++++
> > 1 file changed, 50 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index c9a610ba4836..25579d4c58f2 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
> > };
> > };
> >
> > + isp_0: isp@32e10000 {
> > + compatible = "fsl,imx8mp-isp";
> > + reg = <0x32e10000 0x10000>;
> > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > + clock-names = "isp", "aclk", "hclk";
> > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > + assigned-clock-rates = <500000000>;
> > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > + fsl,blk-ctrl = <&media_blk_ctrl 0>;
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
> > +
> > + isp_1: isp@32e20000 {
> > + compatible = "fsl,imx8mp-isp";
> > + reg = <0x32e20000 0x10000>;
> > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
> > + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > + clock-names = "isp", "aclk", "hclk";
> > + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > + assigned-clock-rates = <500000000>;
> > + power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
> > + fsl,blk-ctrl = <&media_blk_ctrl 1>;
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@1 {
> > + reg = <1>;
> > + };
> > + };
> > + };
> > +
> > dewarp: dwe@32e30000 {
> > compatible = "nxp,imx8mp-dw100";
> > reg = <0x32e30000 0x10000>;
--
Regards,
Laurent Pinchart