Odyssey is a 64 bit ARM based SoC with multiple performance monitor
units for various blocks.
This series of patches introduces support for uncore performance monitor
units (PMUs) on the Marvell Odyssey platform. The PMUs covered in this
series include the DDR PMU and LLC-TAD PMU.
v3->v4:
- Refactored the existing ddr pmu driver to extract the platform data
Gowthami Thiagarajan (3):
perf/marvell: Refactor to extract platform data - no functional change
perf/marvell: perf/marvell: Odyssey DDR Performance monitor support
perf/marvell : Odyssey LLC-TAD performance monitor support
drivers/perf/marvell_cn10k_ddr_pmu.c | 528 +++++++++++++++++++++++----
drivers/perf/marvell_cn10k_tad_pmu.c | 62 +++-
2 files changed, 515 insertions(+), 75 deletions(-)
--
2.25.1
This commit introduces a refactor to the Marvell driver
code, specifically targeting the extraction of platform data
(referred to as "pdata") from the existing driver. The purpose of
this refactor is to prepare for the upcoming support of the next
version of the Performance Monitoring Unit (PMU) in this
driver.
No functional changes are introduced in this refactor. Its sole
purpose is to improve code organization and pave the way for
future enhancements to the driver.
Signed-off-by: Gowthami Thiagarajan <[email protected]>
---
drivers/perf/marvell_cn10k_ddr_pmu.c | 282 ++++++++++++++++++++-------
1 file changed, 210 insertions(+), 72 deletions(-)
diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
index 524ba82bfce2..d6485c4cf30f 100644
--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
@@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
-/* Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver
+/*
+ * Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver
*
- * Copyright (C) 2021 Marvell.
+ * Copyright (C) 2024 Marvell.
*/
#include <linux/init.h>
@@ -14,24 +15,24 @@
#include <linux/platform_device.h>
/* Performance Counters Operating Mode Control Registers */
-#define DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
-#define OP_MODE_CTRL_VAL_MANNUAL 0x1
+#define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
+#define OP_MODE_CTRL_VAL_MANUAL 0x1
/* Performance Counters Start Operation Control Registers */
-#define DDRC_PERF_CNT_START_OP_CTRL 0x8028
+#define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028
#define START_OP_CTRL_VAL_START 0x1ULL
#define START_OP_CTRL_VAL_ACTIVE 0x2
/* Performance Counters End Operation Control Registers */
-#define DDRC_PERF_CNT_END_OP_CTRL 0x8030
+#define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030
#define END_OP_CTRL_VAL_END 0x1ULL
/* Performance Counters End Status Registers */
-#define DDRC_PERF_CNT_END_STATUS 0x8038
+#define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038
#define END_STATUS_VAL_END_TIMER_MODE_END 0x1
/* Performance Counters Configuration Registers */
-#define DDRC_PERF_CFG_BASE 0x8040
+#define CN10K_DDRC_PERF_CFG_BASE 0x8040
/* 8 Generic event counter + 2 fixed event counters */
#define DDRC_PERF_NUM_GEN_COUNTERS 8
@@ -42,17 +43,19 @@
DDRC_PERF_NUM_FIX_COUNTERS)
/* Generic event counter registers */
-#define DDRC_PERF_CFG(n) (DDRC_PERF_CFG_BASE + 8 * (n))
+#define DDRC_PERF_CFG(base, n) ((base) + 8 * (n))
#define EVENT_ENABLE BIT_ULL(63)
/* Two dedicated event counters for DDR reads and writes */
#define EVENT_DDR_READS 101
#define EVENT_DDR_WRITES 100
+#define DDRC_PERF_REG(base, n) ((base) + 8 * (n))
/*
* programmable events IDs in programmable event counters.
* DO NOT change these event-id numbers, they are used to
* program event bitmap in h/w.
+ *
*/
#define EVENT_OP_IS_ZQLATCH 55
#define EVENT_OP_IS_ZQSTART 54
@@ -63,8 +66,8 @@
#define EVENT_VISIBLE_WIN_LIMIT_REACHED_RD 49
#define EVENT_BSM_STARVATION 48
#define EVENT_BSM_ALLOC 47
-#define EVENT_LPR_REQ_WITH_NOCREDIT 46
-#define EVENT_HPR_REQ_WITH_NOCREDIT 45
+#define EVENT_RETRY_FIFO_FULL_OR_LPR_REQ_NOCRED 46
+#define EVENT_DFI_OR_HPR_REQ_NOCRED 45
#define EVENT_OP_IS_ZQCS 44
#define EVENT_OP_IS_ZQCL 43
#define EVENT_OP_IS_LOAD_MODE 42
@@ -102,28 +105,38 @@
#define EVENT_HIF_RD_OR_WR 1
/* Event counter value registers */
-#define DDRC_PERF_CNT_VALUE_BASE 0x8080
-#define DDRC_PERF_CNT_VALUE(n) (DDRC_PERF_CNT_VALUE_BASE + 8 * (n))
+#define CN10K_DDRC_PERF_CNT_VALUE_BASE 0x8080
/* Fixed event counter enable/disable register */
-#define DDRC_PERF_CNT_FREERUN_EN 0x80C0
+#define CN10K_DDRC_PERF_CNT_FREERUN_EN 0x80C0
#define DDRC_PERF_FREERUN_WRITE_EN 0x1
#define DDRC_PERF_FREERUN_READ_EN 0x2
/* Fixed event counter control register */
-#define DDRC_PERF_CNT_FREERUN_CTRL 0x80C8
+#define CN10K_DDRC_PERF_CNT_FREERUN_CTRL 0x80C8
#define DDRC_FREERUN_WRITE_CNT_CLR 0x1
#define DDRC_FREERUN_READ_CNT_CLR 0x2
-/* Fixed event counter value register */
-#define DDRC_PERF_CNT_VALUE_WR_OP 0x80D0
-#define DDRC_PERF_CNT_VALUE_RD_OP 0x80D8
#define DDRC_PERF_CNT_VALUE_OVERFLOW BIT_ULL(48)
#define DDRC_PERF_CNT_MAX_VALUE GENMASK_ULL(48, 0)
+/* Fixed event counter value register */
+#define CN10K_DDRC_PERF_CNT_VALUE_WR_OP 0x80D0
+#define CN10K_DDRC_PERF_CNT_VALUE_RD_OP 0x80D8
+
+enum mrvl_ddr_pmu_version {
+ DDR_PMU_V1 = 1,
+};
+
+struct ddr_pmu_data {
+ int id;
+};
+
struct cn10k_ddr_pmu {
struct pmu pmu;
void __iomem *base;
+ const struct ddr_pmu_platform_data *p_data;
+ int version;
unsigned int cpu;
struct device *dev;
int active_events;
@@ -132,8 +145,35 @@ struct cn10k_ddr_pmu {
struct hlist_node node;
};
+struct ddr_pmu_ops {
+ void (*enable_read_freerun_counter)(struct cn10k_ddr_pmu *pmu,
+ bool enable);
+ void (*enable_write_freerun_counter)(struct cn10k_ddr_pmu *pmu,
+ bool enable);
+ void (*clear_read_freerun_counter)(struct cn10k_ddr_pmu *pmu);
+ void (*clear_write_freerun_counter)(struct cn10k_ddr_pmu *pmu);
+ void (*pmu_overflow_handler)(struct cn10k_ddr_pmu *pmu, int evt_idx);
+};
+
#define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
+struct ddr_pmu_platform_data {
+ u64 counter_overflow_val;
+ u64 counter_max_val;
+ u64 ddrc_perf_cnt_base;
+ u64 ddrc_perf_cfg_base;
+ u64 ddrc_perf_cnt_op_mode_ctrl;
+ u64 ddrc_perf_cnt_start_op_ctrl;
+ u64 ddrc_perf_cnt_end_op_ctrl;
+ u64 ddrc_perf_cnt_end_status;
+ u64 ddrc_perf_cnt_freerun_en;
+ u64 ddrc_perf_cnt_freerun_ctrl;
+ u64 ddrc_perf_cnt_freerun_clr;
+ u64 ddrc_perf_cnt_value_wr_op;
+ u64 ddrc_perf_cnt_value_rd_op;
+ const struct ddr_pmu_ops *ops;
+};
+
static ssize_t cn10k_ddr_pmu_event_show(struct device *dev,
struct device_attribute *attr,
char *page)
@@ -189,9 +229,9 @@ static struct attribute *cn10k_ddr_perf_events_attrs[] = {
CN10K_DDR_PMU_EVENT_ATTR(ddr_zqcl, EVENT_OP_IS_ZQCL),
CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_wr_access, EVENT_OP_IS_ZQCS),
CN10K_DDR_PMU_EVENT_ATTR(ddr_hpr_req_with_nocredit,
- EVENT_HPR_REQ_WITH_NOCREDIT),
+ EVENT_DFI_OR_HPR_REQ_NOCRED),
CN10K_DDR_PMU_EVENT_ATTR(ddr_lpr_req_with_nocredit,
- EVENT_LPR_REQ_WITH_NOCREDIT),
+ EVENT_RETRY_FIFO_FULL_OR_LPR_REQ_NOCRED),
CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_alloc, EVENT_BSM_ALLOC),
CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_starvation, EVENT_BSM_STARVATION),
CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd,
@@ -266,7 +306,8 @@ static ktime_t cn10k_ddr_pmu_timer_period(void)
return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec * USEC_PER_SEC);
}
-static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap)
+static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap,
+ struct cn10k_ddr_pmu *ddr_pmu)
{
switch (eventid) {
case EVENT_HIF_RD_OR_WR ... EVENT_WAW_HAZARD:
@@ -354,6 +395,8 @@ static int cn10k_ddr_perf_event_init(struct perf_event *event)
static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
int counter, bool enable)
{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ const struct ddr_pmu_ops *ops = p_data->ops;
u32 reg;
u64 val;
@@ -363,7 +406,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
}
if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
- reg = DDRC_PERF_CFG(counter);
+ reg = DDRC_PERF_CFG(p_data->ddrc_perf_cfg_base, counter);
val = readq_relaxed(pmu->base + reg);
if (enable)
@@ -373,19 +416,10 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
writeq_relaxed(val, pmu->base + reg);
} else {
- val = readq_relaxed(pmu->base + DDRC_PERF_CNT_FREERUN_EN);
- if (enable) {
- if (counter == DDRC_PERF_READ_COUNTER_IDX)
- val |= DDRC_PERF_FREERUN_READ_EN;
- else
- val |= DDRC_PERF_FREERUN_WRITE_EN;
- } else {
- if (counter == DDRC_PERF_READ_COUNTER_IDX)
- val &= ~DDRC_PERF_FREERUN_READ_EN;
- else
- val &= ~DDRC_PERF_FREERUN_WRITE_EN;
- }
- writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_EN);
+ if (counter == DDRC_PERF_READ_COUNTER_IDX)
+ ops->enable_read_freerun_counter(pmu, enable);
+ else
+ ops->enable_write_freerun_counter(pmu, enable);
}
}
@@ -393,13 +427,18 @@ static u64 cn10k_ddr_perf_read_counter(struct cn10k_ddr_pmu *pmu, int counter)
{
u64 val;
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+
if (counter == DDRC_PERF_READ_COUNTER_IDX)
- return readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE_RD_OP);
+ return readq_relaxed(pmu->base +
+ p_data->ddrc_perf_cnt_value_rd_op);
if (counter == DDRC_PERF_WRITE_COUNTER_IDX)
- return readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE_WR_OP);
+ return readq_relaxed(pmu->base +
+ p_data->ddrc_perf_cnt_value_wr_op);
- val = readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE(counter));
+ val = readq_relaxed(pmu->base +
+ DDRC_PERF_REG(p_data->ddrc_perf_cnt_base, counter));
return val;
}
@@ -407,6 +446,7 @@ static void cn10k_ddr_perf_event_update(struct perf_event *event)
{
struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
struct hw_perf_event *hwc = &event->hw;
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
u64 prev_count, new_count, mask;
do {
@@ -414,7 +454,7 @@ static void cn10k_ddr_perf_event_update(struct perf_event *event)
new_count = cn10k_ddr_perf_read_counter(pmu, hwc->idx);
} while (local64_xchg(&hwc->prev_count, new_count) != prev_count);
- mask = DDRC_PERF_CNT_MAX_VALUE;
+ mask = p_data->counter_max_val;
local64_add((new_count - prev_count) & mask, &event->count);
}
@@ -435,6 +475,8 @@ static void cn10k_ddr_perf_event_start(struct perf_event *event, int flags)
static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
{
struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ const struct ddr_pmu_ops *ops = p_data->ops;
struct hw_perf_event *hwc = &event->hw;
u8 config = event->attr.config;
int counter, ret;
@@ -454,8 +496,8 @@ static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
/* Generic counters, configure event id */
- reg_offset = DDRC_PERF_CFG(counter);
- ret = ddr_perf_get_event_bitmap(config, &val);
+ reg_offset = DDRC_PERF_CFG(p_data->ddrc_perf_cfg_base, counter);
+ ret = ddr_perf_get_event_bitmap(config, &val, pmu);
if (ret)
return ret;
@@ -463,11 +505,9 @@ static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
} else {
/* fixed event counter, clear counter value */
if (counter == DDRC_PERF_READ_COUNTER_IDX)
- val = DDRC_FREERUN_READ_CNT_CLR;
+ ops->clear_read_freerun_counter(pmu);
else
- val = DDRC_FREERUN_WRITE_CNT_CLR;
-
- writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_CTRL);
+ ops->clear_write_freerun_counter(pmu);
}
hwc->state |= PERF_HES_STOPPED;
@@ -512,17 +552,19 @@ static void cn10k_ddr_perf_event_del(struct perf_event *event, int flags)
static void cn10k_ddr_perf_pmu_enable(struct pmu *pmu)
{
struct cn10k_ddr_pmu *ddr_pmu = to_cn10k_ddr_pmu(pmu);
+ const struct ddr_pmu_platform_data *p_data = ddr_pmu->p_data;
writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base +
- DDRC_PERF_CNT_START_OP_CTRL);
+ p_data->ddrc_perf_cnt_start_op_ctrl);
}
static void cn10k_ddr_perf_pmu_disable(struct pmu *pmu)
{
struct cn10k_ddr_pmu *ddr_pmu = to_cn10k_ddr_pmu(pmu);
+ const struct ddr_pmu_platform_data *p_data = ddr_pmu->p_data;
writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base +
- DDRC_PERF_CNT_END_OP_CTRL);
+ p_data->ddrc_perf_cnt_end_op_ctrl);
}
static void cn10k_ddr_perf_event_update_all(struct cn10k_ddr_pmu *pmu)
@@ -547,8 +589,63 @@ static void cn10k_ddr_perf_event_update_all(struct cn10k_ddr_pmu *pmu)
}
}
+static void ddr_pmu_enable_read_freerun(struct cn10k_ddr_pmu *pmu, bool enable)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_en);
+ if (enable)
+ val |= DDRC_PERF_FREERUN_READ_EN;
+ else
+ val &= ~DDRC_PERF_FREERUN_READ_EN;
+
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_en);
+}
+
+static void ddr_pmu_enable_write_freerun(struct cn10k_ddr_pmu *pmu, bool enable)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_en);
+ if (enable)
+ val |= DDRC_PERF_FREERUN_WRITE_EN;
+ else
+ val &= ~DDRC_PERF_FREERUN_WRITE_EN;
+
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_en);
+}
+
+static void ddr_pmu_read_clear_freerun(struct cn10k_ddr_pmu *pmu)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = DDRC_FREERUN_READ_CNT_CLR;
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
+}
+
+static void ddr_pmu_write_clear_freerun(struct cn10k_ddr_pmu *pmu)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = DDRC_FREERUN_WRITE_CNT_CLR;
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
+}
+
+static void ddr_pmu_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt_idx)
+{
+ cn10k_ddr_perf_event_update_all(pmu);
+ cn10k_ddr_perf_pmu_disable(&pmu->pmu);
+ cn10k_ddr_perf_pmu_enable(&pmu->pmu);
+}
+
static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pmu)
{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ const struct ddr_pmu_ops *ops = p_data->ops;
struct perf_event *event;
struct hw_perf_event *hwc;
u64 prev_count, new_count;
@@ -586,11 +683,9 @@ static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pmu)
continue;
value = cn10k_ddr_perf_read_counter(pmu, i);
- if (value == DDRC_PERF_CNT_MAX_VALUE) {
+ if (value == p_data->counter_max_val) {
pr_info("Counter-(%d) reached max value\n", i);
- cn10k_ddr_perf_event_update_all(pmu);
- cn10k_ddr_perf_pmu_disable(&pmu->pmu);
- cn10k_ddr_perf_pmu_enable(&pmu->pmu);
+ ops->pmu_overflow_handler(pmu, i);
}
}
@@ -629,13 +724,44 @@ static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
return 0;
}
+static const struct ddr_pmu_ops ddr_pmu_ops = {
+ .enable_read_freerun_counter = ddr_pmu_enable_read_freerun,
+ .enable_write_freerun_counter = ddr_pmu_enable_write_freerun,
+ .clear_read_freerun_counter = ddr_pmu_read_clear_freerun,
+ .clear_write_freerun_counter = ddr_pmu_write_clear_freerun,
+ .pmu_overflow_handler = ddr_pmu_overflow_hander,
+};
+
+static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata = {
+ .counter_overflow_val = BIT_ULL(48),
+ .counter_max_val = GENMASK_ULL(48, 0),
+ .ddrc_perf_cnt_base = CN10K_DDRC_PERF_CNT_VALUE_BASE,
+ .ddrc_perf_cfg_base = CN10K_DDRC_PERF_CFG_BASE,
+ .ddrc_perf_cnt_op_mode_ctrl = CN10K_DDRC_PERF_CNT_OP_MODE_CTRL,
+ .ddrc_perf_cnt_start_op_ctrl = CN10K_DDRC_PERF_CNT_START_OP_CTRL,
+ .ddrc_perf_cnt_end_op_ctrl = CN10K_DDRC_PERF_CNT_END_OP_CTRL,
+ .ddrc_perf_cnt_end_status = CN10K_DDRC_PERF_CNT_END_STATUS,
+ .ddrc_perf_cnt_freerun_en = CN10K_DDRC_PERF_CNT_FREERUN_EN,
+ .ddrc_perf_cnt_freerun_ctrl = CN10K_DDRC_PERF_CNT_FREERUN_CTRL,
+ .ddrc_perf_cnt_freerun_clr = 0,
+ .ddrc_perf_cnt_value_wr_op = CN10K_DDRC_PERF_CNT_VALUE_WR_OP,
+ .ddrc_perf_cnt_value_rd_op = CN10K_DDRC_PERF_CNT_VALUE_RD_OP,
+ .ops = &ddr_pmu_ops,
+};
+
+static const struct ddr_pmu_data ddr_pmu_data = {
+ .id = DDR_PMU_V1,
+};
+
static int cn10k_ddr_perf_probe(struct platform_device *pdev)
{
+ const struct ddr_pmu_data *dev_data;
struct cn10k_ddr_pmu *ddr_pmu;
struct resource *res;
void __iomem *base;
char *name;
int ret;
+ int version;
ddr_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddr_pmu), GFP_KERNEL);
if (!ddr_pmu)
@@ -644,30 +770,42 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
ddr_pmu->dev = &pdev->dev;
platform_set_drvdata(pdev, ddr_pmu);
+ dev_data = device_get_match_data(&pdev->dev);
+ if (!dev_data) {
+ dev_err(&pdev->dev, "Error: No device match data found\n");
+ return -ENODEV;
+ }
+ version = dev_data->id;
+ ddr_pmu->version = version;
+
base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(base))
return PTR_ERR(base);
ddr_pmu->base = base;
- /* Setup the PMU counter to work in manual mode */
- writeq_relaxed(OP_MODE_CTRL_VAL_MANNUAL, ddr_pmu->base +
- DDRC_PERF_CNT_OP_MODE_CTRL);
-
- ddr_pmu->pmu = (struct pmu) {
- .module = THIS_MODULE,
- .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
- .task_ctx_nr = perf_invalid_context,
- .attr_groups = cn10k_attr_groups,
- .event_init = cn10k_ddr_perf_event_init,
- .add = cn10k_ddr_perf_event_add,
- .del = cn10k_ddr_perf_event_del,
- .start = cn10k_ddr_perf_event_start,
- .stop = cn10k_ddr_perf_event_stop,
- .read = cn10k_ddr_perf_event_update,
- .pmu_enable = cn10k_ddr_perf_pmu_enable,
- .pmu_disable = cn10k_ddr_perf_pmu_disable,
- };
+ if (version == DDR_PMU_V1) {
+ /* Setup the PMU counter to work in manual mode */
+ writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base +
+ (ddr_pmu->p_data->ddrc_perf_cnt_op_mode_ctrl));
+
+ ddr_pmu->pmu = (struct pmu) {
+ .module = THIS_MODULE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = cn10k_attr_groups,
+ .event_init = cn10k_ddr_perf_event_init,
+ .add = cn10k_ddr_perf_event_add,
+ .del = cn10k_ddr_perf_event_del,
+ .start = cn10k_ddr_perf_event_start,
+ .stop = cn10k_ddr_perf_event_stop,
+ .read = cn10k_ddr_perf_event_update,
+ .pmu_enable = cn10k_ddr_perf_pmu_enable,
+ .pmu_disable = cn10k_ddr_perf_pmu_disable,
+ };
+
+ ddr_pmu->p_data = &cn10k_ddr_pmu_pdata;
+ }
/* Choose this cpu to collect perf data */
ddr_pmu->cpu = raw_smp_processor_id();
@@ -688,7 +826,7 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
if (ret)
goto error;
- pr_info("CN10K DDR PMU Driver for ddrc@%llx\n", res->start);
+ pr_info("DDR PMU Driver for ddrc@%llx\n", res->start);
return 0;
error:
cpuhp_state_remove_instance_nocalls(
@@ -711,7 +849,7 @@ static int cn10k_ddr_perf_remove(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id cn10k_ddr_pmu_of_match[] = {
- { .compatible = "marvell,cn10k-ddr-pmu", },
+ { .compatible = "marvell,cn10k-ddr-pmu", .data = &ddr_pmu_data},
{ },
};
MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
@@ -719,7 +857,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] = {
- {"MRVL000A", 0},
+ {"MRVL000A", (kernel_ulong_t)&ddr_pmu_data},
{},
};
MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match);
--
2.25.1
Odyssey DRAM Subsystem supports eight counters for monitoring performance
and software can program those counters to monitor any of the defined
performance events. Supported performance events include those counted
at the interface between the DDR controller and the PHY, interface between
the DDR Controller and the CHI interconnect, or within the DDR Controller.
Additionally DSS also supports two fixed performance event counters, one
for ddr reads and the other for ddr writes.
Signed-off-by: Gowthami Thiagarajan <[email protected]>
---
drivers/perf/marvell_cn10k_ddr_pmu.c | 246 +++++++++++++++++++++++++++
1 file changed, 246 insertions(+)
diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
index d6485c4cf30f..1fd619262d45 100644
--- a/drivers/perf/marvell_cn10k_ddr_pmu.c
+++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
@@ -16,23 +16,28 @@
/* Performance Counters Operating Mode Control Registers */
#define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
+#define ODY_DDRC_PERF_CNT_OP_MODE_CTRL 0x20020
#define OP_MODE_CTRL_VAL_MANUAL 0x1
/* Performance Counters Start Operation Control Registers */
#define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028
+#define ODY_DDRC_PERF_CNT_START_OP_CTRL 0x200A0
#define START_OP_CTRL_VAL_START 0x1ULL
#define START_OP_CTRL_VAL_ACTIVE 0x2
/* Performance Counters End Operation Control Registers */
#define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030
+#define ODY_DDRC_PERF_CNT_END_OP_CTRL 0x200E0
#define END_OP_CTRL_VAL_END 0x1ULL
/* Performance Counters End Status Registers */
#define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038
+#define ODY_DDRC_PERF_CNT_END_STATUS 0x20120
#define END_STATUS_VAL_END_TIMER_MODE_END 0x1
/* Performance Counters Configuration Registers */
#define CN10K_DDRC_PERF_CFG_BASE 0x8040
+#define ODY_DDRC_PERF_CFG_BASE 0x20160
/* 8 Generic event counter + 2 fixed event counters */
#define DDRC_PERF_NUM_GEN_COUNTERS 8
@@ -57,6 +62,13 @@
* program event bitmap in h/w.
*
*/
+#define EVENT_DFI_CMD_IS_RETRY 61
+#define EVENT_RD_UC_ECC_ERROR 60
+#define EVENT_RD_CRC_ERROR 59
+#define EVENT_CAPAR_ERROR 58
+#define EVENT_WR_CRC_ERROR 57
+#define EVENT_DFI_PARITY_POISON 56
+
#define EVENT_OP_IS_ZQLATCH 55
#define EVENT_OP_IS_ZQSTART 54
#define EVENT_OP_IS_TCR_MRR 53
@@ -106,6 +118,7 @@
/* Event counter value registers */
#define CN10K_DDRC_PERF_CNT_VALUE_BASE 0x8080
+#define ODY_DDRC_PERF_CNT_VALUE_BASE 0x201C0
/* Fixed event counter enable/disable register */
#define CN10K_DDRC_PERF_CNT_FREERUN_EN 0x80C0
@@ -114,18 +127,25 @@
/* Fixed event counter control register */
#define CN10K_DDRC_PERF_CNT_FREERUN_CTRL 0x80C8
+#define ODY_DDRC_PERF_CNT_FREERUN_CTRL 0x20240
#define DDRC_FREERUN_WRITE_CNT_CLR 0x1
#define DDRC_FREERUN_READ_CNT_CLR 0x2
+/* Fixed event counter clear register, defined only for Odyssey */
+#define ODY_DDRC_PERF_CNT_FREERUN_CLR 0x20248
+
#define DDRC_PERF_CNT_VALUE_OVERFLOW BIT_ULL(48)
#define DDRC_PERF_CNT_MAX_VALUE GENMASK_ULL(48, 0)
/* Fixed event counter value register */
#define CN10K_DDRC_PERF_CNT_VALUE_WR_OP 0x80D0
#define CN10K_DDRC_PERF_CNT_VALUE_RD_OP 0x80D8
+#define ODY_DDRC_PERF_CNT_VALUE_WR_OP 0x20250
+#define ODY_DDRC_PERF_CNT_VALUE_RD_OP 0x20258
enum mrvl_ddr_pmu_version {
DDR_PMU_V1 = 1,
+ DDR_PMU_V2,
};
struct ddr_pmu_data {
@@ -249,6 +269,85 @@ static struct attribute *cn10k_ddr_perf_events_attrs[] = {
NULL
};
+static struct attribute *odyssey_ddr_perf_events_attrs[] = {
+ /* Programmable */
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_or_wr_access, EVENT_HIF_RD_OR_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_wr_access, EVENT_HIF_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rd_access, EVENT_HIF_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_rmw_access, EVENT_HIF_RMW),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hif_pri_rdaccess, EVENT_HIF_HI_PRI_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_bypass_access, EVENT_READ_BYPASS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_act_bypass_access, EVENT_ACT_BYPASS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_wr_data_access,
+ EVENT_DFI_WR_DATA_CYCLES),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_rd_data_access,
+ EVENT_DFI_RD_DATA_CYCLES),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_hpri_sched_rd_crit_access,
+ EVENT_HPR_XACT_WHEN_CRITICAL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_lpri_sched_rd_crit_access,
+ EVENT_LPR_XACT_WHEN_CRITICAL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_trxn_crit_access,
+ EVENT_WR_XACT_WHEN_CRITICAL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_active_access, EVENT_OP_IS_ACTIVATE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_or_wr_access,
+ EVENT_OP_IS_RD_OR_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_rd_active_access,
+ EVENT_OP_IS_RD_ACTIVATE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_read, EVENT_OP_IS_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_write, EVENT_OP_IS_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_mwr, EVENT_OP_IS_MWR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge, EVENT_OP_IS_PRECHARGE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_rdwr,
+ EVENT_PRECHARGE_FOR_RDWR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_precharge_for_other,
+ EVENT_PRECHARGE_FOR_OTHER),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rdwr_transitions, EVENT_RDWR_TRANSITIONS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_write_combine, EVENT_WRITE_COMBINE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_war_hazard, EVENT_WAR_HAZARD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_raw_hazard, EVENT_RAW_HAZARD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_waw_hazard, EVENT_WAW_HAZARD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_selfref, EVENT_OP_IS_ENTER_SELFREF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_powerdown,
+ EVENT_OP_IS_ENTER_POWERDOWN),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_enter_mpsm, EVENT_OP_IS_ENTER_MPSM),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_refresh, EVENT_OP_IS_REFRESH),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_crit_ref, EVENT_OP_IS_CRIT_REF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_spec_ref, EVENT_OP_IS_SPEC_REF),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_load_mode, EVENT_OP_IS_LOAD_MODE),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_zqcl, EVENT_OP_IS_ZQCL),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_wr_access, EVENT_OP_IS_ZQCS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cycles, EVENT_DFI_OR_HPR_REQ_NOCRED),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_retry_fifo_full,
+ EVENT_RETRY_FIFO_FULL_OR_LPR_REQ_NOCRED),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_alloc, EVENT_BSM_ALLOC),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_starvation, EVENT_BSM_STARVATION),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd,
+ EVENT_VISIBLE_WIN_LIMIT_REACHED_RD),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_wr,
+ EVENT_VISIBLE_WIN_LIMIT_REACHED_WR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mpc, EVENT_OP_IS_DQSOSC_MPC),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dqsosc_mrr, EVENT_OP_IS_DQSOSC_MRR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_tcr_mrr, EVENT_OP_IS_TCR_MRR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_zqstart, EVENT_OP_IS_ZQSTART),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_zqlatch, EVENT_OP_IS_ZQLATCH),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_parity_poison,
+ EVENT_DFI_PARITY_POISON),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_wr_crc_error, EVENT_WR_CRC_ERROR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_capar_error, EVENT_CAPAR_ERROR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_crc_error, EVENT_RD_CRC_ERROR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_rd_uc_ecc_error, EVENT_RD_UC_ECC_ERROR),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_dfi_cmd_is_retry, EVENT_DFI_CMD_IS_RETRY),
+ /* Free run event counters */
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_reads, EVENT_DDR_READS),
+ CN10K_DDR_PMU_EVENT_ATTR(ddr_ddr_writes, EVENT_DDR_WRITES),
+ NULL
+};
+
+static struct attribute_group odyssey_ddr_perf_events_attr_group = {
+ .name = "events",
+ .attrs = odyssey_ddr_perf_events_attrs,
+};
+
static struct attribute_group cn10k_ddr_perf_events_attr_group = {
.name = "events",
.attrs = cn10k_ddr_perf_events_attrs,
@@ -294,6 +393,13 @@ static const struct attribute_group *cn10k_attr_groups[] = {
NULL,
};
+static const struct attribute_group *odyssey_attr_groups[] = {
+ &odyssey_ddr_perf_events_attr_group,
+ &cn10k_ddr_perf_format_attr_group,
+ &cn10k_ddr_perf_cpumask_attr_group,
+ NULL
+};
+
/* Default poll timeout is 100 sec, which is very sufficient for
* 48 bit counter incremented max at 5.6 GT/s, which may take many
* hours to overflow.
@@ -314,6 +420,14 @@ static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap,
case EVENT_OP_IS_REFRESH ... EVENT_OP_IS_ZQLATCH:
*event_bitmap = (1ULL << (eventid - 1));
break;
+ case EVENT_DFI_PARITY_POISON ...EVENT_DFI_CMD_IS_RETRY:
+ if (ddr_pmu->version == DDR_PMU_V2) {
+ *event_bitmap = (1ULL << (eventid - 1));
+ } else {
+ pr_err("%s Invalid eventid %d\n", __func__, eventid);
+ return -EINVAL;
+ }
+ break;
case EVENT_OP_IS_ENTER_SELFREF:
case EVENT_OP_IS_ENTER_POWERDOWN:
case EVENT_OP_IS_ENTER_MPSM:
@@ -439,6 +553,7 @@ static u64 cn10k_ddr_perf_read_counter(struct cn10k_ddr_pmu *pmu, int counter)
val = readq_relaxed(pmu->base +
DDRC_PERF_REG(p_data->ddrc_perf_cnt_base, counter));
+
return val;
}
@@ -459,15 +574,43 @@ static void cn10k_ddr_perf_event_update(struct perf_event *event)
local64_add((new_count - prev_count) & mask, &event->count);
}
+static void cn10k_ddr_perf_counter_start(struct cn10k_ddr_pmu *ddr_pmu,
+ int counter)
+{
+ const struct ddr_pmu_platform_data *p_data = ddr_pmu->p_data;
+ u64 ctrl_reg = p_data->ddrc_perf_cnt_start_op_ctrl;
+
+ writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base +
+ DDRC_PERF_REG(ctrl_reg, counter));
+}
+
+static void cn10k_ddr_perf_counter_stop(struct cn10k_ddr_pmu *ddr_pmu,
+ int counter)
+{
+ const struct ddr_pmu_platform_data *p_data = ddr_pmu->p_data;
+ u64 ctrl_reg = p_data->ddrc_perf_cnt_end_op_ctrl;
+
+ writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base +
+ DDRC_PERF_REG(ctrl_reg, counter));
+}
+
static void cn10k_ddr_perf_event_start(struct perf_event *event, int flags)
{
struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
+ u64 ctrl_reg = pmu->p_data->ddrc_perf_cnt_op_mode_ctrl;
struct hw_perf_event *hwc = &event->hw;
int counter = hwc->idx;
local64_set(&hwc->prev_count, 0);
cn10k_ddr_perf_counter_enable(pmu, counter, true);
+ if (pmu->version == DDR_PMU_V2) {
+ /* Setup the PMU counter to work in manual mode */
+ writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, pmu->base +
+ DDRC_PERF_REG(ctrl_reg, counter));
+
+ cn10k_ddr_perf_counter_start(pmu, counter);
+ }
hwc->state = 0;
}
@@ -526,6 +669,9 @@ static void cn10k_ddr_perf_event_stop(struct perf_event *event, int flags)
cn10k_ddr_perf_counter_enable(pmu, counter, false);
+ if (pmu->version == DDR_PMU_V2)
+ cn10k_ddr_perf_counter_stop(pmu, counter);
+
if (flags & PERF_EF_UPDATE)
cn10k_ddr_perf_event_update(event);
@@ -642,6 +788,61 @@ static void ddr_pmu_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt_idx)
cn10k_ddr_perf_pmu_enable(&pmu->pmu);
}
+static void ddr_pmu_v2_enable_read_freerun(struct cn10k_ddr_pmu *pmu,
+ bool enable)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
+ if (enable)
+ val |= DDRC_PERF_FREERUN_READ_EN;
+ else
+ val &= ~DDRC_PERF_FREERUN_READ_EN;
+
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
+}
+
+static void ddr_pmu_v2_enable_write_freerun(struct cn10k_ddr_pmu *pmu,
+ bool enable)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
+ if (enable)
+ val |= DDRC_PERF_FREERUN_WRITE_EN;
+ else
+ val &= ~DDRC_PERF_FREERUN_WRITE_EN;
+
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
+}
+
+static void ddr_pmu_v2_read_clear_freerun(struct cn10k_ddr_pmu *pmu)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = DDRC_FREERUN_READ_CNT_CLR;
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_clr);
+}
+
+static void ddr_pmu_v2_write_clear_freerun(struct cn10k_ddr_pmu *pmu)
+{
+ const struct ddr_pmu_platform_data *p_data = pmu->p_data;
+ u64 val;
+
+ val = DDRC_FREERUN_WRITE_CNT_CLR;
+ writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_clr);
+}
+
+static void ddr_pmu_v2_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt_idx)
+{
+ cn10k_ddr_perf_event_update(pmu->events[evt_idx]);
+ cn10k_ddr_perf_counter_stop(pmu, evt_idx);
+ cn10k_ddr_perf_counter_start(pmu, evt_idx);
+}
+
static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pmu)
{
const struct ddr_pmu_platform_data *p_data = pmu->p_data;
@@ -753,6 +954,35 @@ static const struct ddr_pmu_data ddr_pmu_data = {
.id = DDR_PMU_V1,
};
+static const struct ddr_pmu_ops ddr_pmu_v2_ops = {
+ .enable_read_freerun_counter = ddr_pmu_v2_enable_read_freerun,
+ .enable_write_freerun_counter = ddr_pmu_v2_enable_write_freerun,
+ .clear_read_freerun_counter = ddr_pmu_v2_read_clear_freerun,
+ .clear_write_freerun_counter = ddr_pmu_v2_write_clear_freerun,
+ .pmu_overflow_handler = ddr_pmu_v2_overflow_hander,
+};
+
+static const struct ddr_pmu_platform_data odyssey_ddr_pmu_pdata = {
+ .counter_overflow_val = 0,
+ .counter_max_val = GENMASK_ULL(63, 0),
+ .ddrc_perf_cnt_base = ODY_DDRC_PERF_CNT_VALUE_BASE,
+ .ddrc_perf_cfg_base = ODY_DDRC_PERF_CFG_BASE,
+ .ddrc_perf_cnt_op_mode_ctrl = ODY_DDRC_PERF_CNT_OP_MODE_CTRL,
+ .ddrc_perf_cnt_start_op_ctrl = ODY_DDRC_PERF_CNT_START_OP_CTRL,
+ .ddrc_perf_cnt_end_op_ctrl = ODY_DDRC_PERF_CNT_END_OP_CTRL,
+ .ddrc_perf_cnt_end_status = ODY_DDRC_PERF_CNT_END_STATUS,
+ .ddrc_perf_cnt_freerun_en = 0,
+ .ddrc_perf_cnt_freerun_ctrl = ODY_DDRC_PERF_CNT_FREERUN_CTRL,
+ .ddrc_perf_cnt_freerun_clr = ODY_DDRC_PERF_CNT_FREERUN_CLR,
+ .ddrc_perf_cnt_value_wr_op = ODY_DDRC_PERF_CNT_VALUE_WR_OP,
+ .ddrc_perf_cnt_value_rd_op = ODY_DDRC_PERF_CNT_VALUE_RD_OP,
+ .ops = &ddr_pmu_v2_ops,
+};
+
+static const struct ddr_pmu_data ddr_pmu_v2_data = {
+ .id = DDR_PMU_V2,
+};
+
static int cn10k_ddr_perf_probe(struct platform_device *pdev)
{
const struct ddr_pmu_data *dev_data;
@@ -805,6 +1035,21 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
};
ddr_pmu->p_data = &cn10k_ddr_pmu_pdata;
+ } else {
+ ddr_pmu->pmu = (struct pmu) {
+ .module = THIS_MODULE,
+ .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
+ .task_ctx_nr = perf_invalid_context,
+ .attr_groups = odyssey_attr_groups,
+ .event_init = cn10k_ddr_perf_event_init,
+ .add = cn10k_ddr_perf_event_add,
+ .del = cn10k_ddr_perf_event_del,
+ .start = cn10k_ddr_perf_event_start,
+ .stop = cn10k_ddr_perf_event_stop,
+ .read = cn10k_ddr_perf_event_update,
+ };
+
+ ddr_pmu->p_data = &odyssey_ddr_pmu_pdata;
}
/* Choose this cpu to collect perf data */
@@ -858,6 +1103,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
#ifdef CONFIG_ACPI
static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] = {
{"MRVL000A", (kernel_ulong_t)&ddr_pmu_data},
+ {"MRVL000C", (kernel_ulong_t)&ddr_pmu_v2_data},
{},
};
MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match);
--
2.25.1
Each TAD provides eight 64-bit counters for monitoring
cache behavior.The driver always configures the same counter for
all the TADs. The user would end up effectively reserving one of
eight counters in every TAD to look across all TADs.
The occurrences of events are aggregated and presented to the user
at the end of running the workload. The driver does not provide a
way for the user to partition TADs so that different TADs are used for
different applications.
The performance events reflect various internal or interface activities.
By combining the values from multiple performance counters, cache
performance can be measured in terms such as: cache miss rate, cache
allocations, interface retry rate, internal resource occupancy, etc.
Each supported counter's event and formatting information is exposed
to sysfs at /sys/devices/tad/. Use perf tool stat command to measure
the pmu events. For instance:
perf stat -e tad_hit_ltg,tad_hit_dtg <workload>
Signed-off-by: Gowthami Thiagarajan <[email protected]>
---
drivers/perf/marvell_cn10k_tad_pmu.c | 62 ++++++++++++++++++++++++++--
1 file changed, 59 insertions(+), 3 deletions(-)
diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn10k_tad_pmu.c
index fec8e82edb95..df6569f7a06f 100644
--- a/drivers/perf/marvell_cn10k_tad_pmu.c
+++ b/drivers/perf/marvell_cn10k_tad_pmu.c
@@ -37,6 +37,15 @@ struct tad_pmu {
DECLARE_BITMAP(counters_map, TAD_MAX_COUNTERS);
};
+enum mrvl_tad_pmu_version {
+ TAD_PMU_V1 = 1,
+ TAD_PMU_V2,
+};
+
+struct tad_pmu_data {
+ int id;
+};
+
static int tad_pmu_cpuhp_state;
static void tad_pmu_event_counter_read(struct perf_event *event)
@@ -214,6 +223,24 @@ static const struct attribute_group tad_pmu_events_attr_group = {
.attrs = tad_pmu_event_attrs,
};
+static struct attribute *ody_tad_pmu_event_attrs[] = {
+ TAD_PMU_EVENT_ATTR(tad_req_msh_in_exlmn, 0x3),
+ TAD_PMU_EVENT_ATTR(tad_alloc_dtg, 0x1a),
+ TAD_PMU_EVENT_ATTR(tad_alloc_ltg, 0x1b),
+ TAD_PMU_EVENT_ATTR(tad_alloc_any, 0x1c),
+ TAD_PMU_EVENT_ATTR(tad_hit_dtg, 0x1d),
+ TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e),
+ TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f),
+ TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20),
+ TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xFF),
+ NULL
+};
+
+static const struct attribute_group ody_tad_pmu_events_attr_group = {
+ .name = "events",
+ .attrs = ody_tad_pmu_event_attrs,
+};
+
PMU_FORMAT_ATTR(event, "config:0-7");
static struct attribute *tad_pmu_format_attrs[] = {
@@ -252,8 +279,16 @@ static const struct attribute_group *tad_pmu_attr_groups[] = {
NULL
};
+static const struct attribute_group *ody_tad_pmu_attr_groups[] = {
+ &ody_tad_pmu_events_attr_group,
+ &tad_pmu_format_attr_group,
+ &tad_pmu_cpumask_attr_group,
+ NULL
+};
+
static int tad_pmu_probe(struct platform_device *pdev)
{
+ const struct tad_pmu_data *dev_data;
struct device *dev = &pdev->dev;
struct tad_region *regions;
struct tad_pmu *tad_pmu;
@@ -261,6 +296,7 @@ static int tad_pmu_probe(struct platform_device *pdev)
u32 tad_pmu_page_size;
u32 tad_page_size;
u32 tad_cnt;
+ int version;
int i, ret;
char *name;
@@ -270,6 +306,13 @@ static int tad_pmu_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, tad_pmu);
+ dev_data = device_get_match_data(&pdev->dev);
+ if (!dev_data) {
+ dev_err(&pdev->dev, "Error: No device match data found\n");
+ return -ENODEV;
+ }
+ version = dev_data->id;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Mem resource not found\n");
@@ -319,7 +362,6 @@ static int tad_pmu_probe(struct platform_device *pdev)
tad_pmu->pmu = (struct pmu) {
.module = THIS_MODULE,
- .attr_groups = tad_pmu_attr_groups,
.capabilities = PERF_PMU_CAP_NO_EXCLUDE |
PERF_PMU_CAP_NO_INTERRUPT,
.task_ctx_nr = perf_invalid_context,
@@ -332,6 +374,11 @@ static int tad_pmu_probe(struct platform_device *pdev)
.read = tad_pmu_event_counter_read,
};
+ if (version == TAD_PMU_V1)
+ tad_pmu->pmu.attr_groups = tad_pmu_attr_groups;
+ else
+ tad_pmu->pmu.attr_groups = ody_tad_pmu_attr_groups;
+
tad_pmu->cpu = raw_smp_processor_id();
/* Register pmu instance for cpu hotplug */
@@ -362,16 +409,25 @@ static int tad_pmu_remove(struct platform_device *pdev)
return 0;
}
+static const struct tad_pmu_data tad_pmu_data = {
+ .id = TAD_PMU_V1,
+};
+
+static const struct tad_pmu_data tad_pmu_v2_data = {
+ .id = TAD_PMU_V2,
+};
+
#ifdef CONFIG_OF
static const struct of_device_id tad_pmu_of_match[] = {
- { .compatible = "marvell,cn10k-tad-pmu", },
+ { .compatible = "marvell,cn10k-tad-pmu", .data = &tad_pmu_data },
{},
};
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id tad_pmu_acpi_match[] = {
- {"MRVL000B", 0},
+ {"MRVL000B", (kernel_ulong_t)&tad_pmu_data},
+ {"MRVL000D", (kernel_ulong_t)&tad_pmu_v2_data},
{},
};
MODULE_DEVICE_TABLE(acpi, tad_pmu_acpi_match);
--
2.25.1
Hi Gowthami,
kernel test robot noticed the following build warnings:
[auto build test WARNING on soc/for-next]
[also build test WARNING on linus/master v6.9-rc1 next-20240327]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Gowthami-Thiagarajan/perf-marvell-Refactor-to-extract-platform-data/20240327-152242
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link: https://lore.kernel.org/r/20240327071832.1556576-3-gthiagarajan%40marvell.com
patch subject: [RESEND PATCH v4 2/3] perf/marvell: perf/marvell: Odyssey DDR Performance
config: sparc-allmodconfig (https://download.01.org/0day-ci/archive/20240328/[email protected]/config)
compiler: sparc64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240328/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
>> drivers/perf/marvell_cn10k_ddr_pmu.c:982:34: warning: 'ddr_pmu_v2_data' defined but not used [-Wunused-const-variable=]
982 | static const struct ddr_pmu_data ddr_pmu_v2_data = {
| ^~~~~~~~~~~~~~~
vim +/ddr_pmu_v2_data +982 drivers/perf/marvell_cn10k_ddr_pmu.c
981
> 982 static const struct ddr_pmu_data ddr_pmu_v2_data = {
983 .id = DDR_PMU_V2,
984 };
985
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Gowthami,
kernel test robot noticed the following build warnings:
[auto build test WARNING on soc/for-next]
[also build test WARNING on linus/master v6.9-rc1 next-20240328]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Gowthami-Thiagarajan/perf-marvell-Refactor-to-extract-platform-data/20240327-152242
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link: https://lore.kernel.org/r/20240327071832.1556576-4-gthiagarajan%40marvell.com
patch subject: [RESEND PATCH v4 3/3] perf/marvell : Odyssey LLC-TAD performance monitor
config: alpha-randconfig-r071-20240328 (https://download.01.org/0day-ci/archive/20240328/[email protected]/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240328/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All warnings (new ones prefixed by >>):
drivers/perf/marvell_cn10k_tad_pmu.c:416:34: warning: 'tad_pmu_v2_data' defined but not used [-Wunused-const-variable=]
416 | static const struct tad_pmu_data tad_pmu_v2_data = {
| ^~~~~~~~~~~~~~~
>> drivers/perf/marvell_cn10k_tad_pmu.c:412:34: warning: 'tad_pmu_data' defined but not used [-Wunused-const-variable=]
412 | static const struct tad_pmu_data tad_pmu_data = {
| ^~~~~~~~~~~~
vim +/tad_pmu_data +412 drivers/perf/marvell_cn10k_tad_pmu.c
411
> 412 static const struct tad_pmu_data tad_pmu_data = {
413 .id = TAD_PMU_V1,
414 };
415
> 416 static const struct tad_pmu_data tad_pmu_v2_data = {
417 .id = TAD_PMU_V2,
418 };
419
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi,
The patches are updated as per the comments received. Do you have any feedback on this version?
Thanks,
Gowthami
> -----Original Message-----
> From: Gowthami Thiagarajan <[email protected]>
> Sent: Wednesday, March 27, 2024 12:49 PM
> To: [email protected]; [email protected]; [email protected]; linux-
> [email protected]
> Cc: Sunil Kovvuri Goutham <[email protected]>; Bharat Bhushan <[email protected]>; George
> Cherian <[email protected]>; Gowthami Thiagarajan <[email protected]>
> Subject: [RESEND PATCH v4 1/3] perf/marvell: Refactor to extract platform data
>
> This commit introduces a refactor to the Marvell driver
> code, specifically targeting the extraction of platform data
> (referred to as "pdata") from the existing driver. The purpose of
> this refactor is to prepare for the upcoming support of the next
> version of the Performance Monitoring Unit (PMU) in this
> driver.
>
> No functional changes are introduced in this refactor. Its sole
> purpose is to improve code organization and pave the way for
> future enhancements to the driver.
>
> Signed-off-by: Gowthami Thiagarajan <[email protected]>
> ---
> drivers/perf/marvell_cn10k_ddr_pmu.c | 282 ++++++++++++++++++++-------
> 1 file changed, 210 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/perf/marvell_cn10k_ddr_pmu.c b/drivers/perf/marvell_cn10k_ddr_pmu.c
> index 524ba82bfce2..d6485c4cf30f 100644
> --- a/drivers/perf/marvell_cn10k_ddr_pmu.c
> +++ b/drivers/perf/marvell_cn10k_ddr_pmu.c
> @@ -1,7 +1,8 @@
> // SPDX-License-Identifier: GPL-2.0
> -/* Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver
> +/*
> + * Marvell CN10K DRAM Subsystem (DSS) Performance Monitor Driver
> *
> - * Copyright (C) 2021 Marvell.
> + * Copyright (C) 2024 Marvell.
> */
>
> #include <linux/init.h>
> @@ -14,24 +15,24 @@
> #include <linux/platform_device.h>
>
> /* Performance Counters Operating Mode Control Registers */
> -#define DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
> -#define OP_MODE_CTRL_VAL_MANNUAL 0x1
> +#define CN10K_DDRC_PERF_CNT_OP_MODE_CTRL 0x8020
> +#define OP_MODE_CTRL_VAL_MANUAL 0x1
>
> /* Performance Counters Start Operation Control Registers */
> -#define DDRC_PERF_CNT_START_OP_CTRL 0x8028
> +#define CN10K_DDRC_PERF_CNT_START_OP_CTRL 0x8028
> #define START_OP_CTRL_VAL_START 0x1ULL
> #define START_OP_CTRL_VAL_ACTIVE 0x2
>
> /* Performance Counters End Operation Control Registers */
> -#define DDRC_PERF_CNT_END_OP_CTRL 0x8030
> +#define CN10K_DDRC_PERF_CNT_END_OP_CTRL 0x8030
> #define END_OP_CTRL_VAL_END 0x1ULL
>
> /* Performance Counters End Status Registers */
> -#define DDRC_PERF_CNT_END_STATUS 0x8038
> +#define CN10K_DDRC_PERF_CNT_END_STATUS 0x8038
> #define END_STATUS_VAL_END_TIMER_MODE_END 0x1
>
> /* Performance Counters Configuration Registers */
> -#define DDRC_PERF_CFG_BASE 0x8040
> +#define CN10K_DDRC_PERF_CFG_BASE 0x8040
>
> /* 8 Generic event counter + 2 fixed event counters */
> #define DDRC_PERF_NUM_GEN_COUNTERS 8
> @@ -42,17 +43,19 @@
> DDRC_PERF_NUM_FIX_COUNTERS)
>
> /* Generic event counter registers */
> -#define DDRC_PERF_CFG(n) (DDRC_PERF_CFG_BASE + 8 * (n))
> +#define DDRC_PERF_CFG(base, n) ((base) + 8 * (n))
> #define EVENT_ENABLE BIT_ULL(63)
>
> /* Two dedicated event counters for DDR reads and writes */
> #define EVENT_DDR_READS 101
> #define EVENT_DDR_WRITES 100
>
> +#define DDRC_PERF_REG(base, n) ((base) + 8 * (n))
> /*
> * programmable events IDs in programmable event counters.
> * DO NOT change these event-id numbers, they are used to
> * program event bitmap in h/w.
> + *
> */
> #define EVENT_OP_IS_ZQLATCH 55
> #define EVENT_OP_IS_ZQSTART 54
> @@ -63,8 +66,8 @@
> #define EVENT_VISIBLE_WIN_LIMIT_REACHED_RD 49
> #define EVENT_BSM_STARVATION 48
> #define EVENT_BSM_ALLOC 47
> -#define EVENT_LPR_REQ_WITH_NOCREDIT 46
> -#define EVENT_HPR_REQ_WITH_NOCREDIT 45
> +#define EVENT_RETRY_FIFO_FULL_OR_LPR_REQ_NOCRED 46
> +#define EVENT_DFI_OR_HPR_REQ_NOCRED 45
> #define EVENT_OP_IS_ZQCS 44
> #define EVENT_OP_IS_ZQCL 43
> #define EVENT_OP_IS_LOAD_MODE 42
> @@ -102,28 +105,38 @@
> #define EVENT_HIF_RD_OR_WR 1
>
> /* Event counter value registers */
> -#define DDRC_PERF_CNT_VALUE_BASE 0x8080
> -#define DDRC_PERF_CNT_VALUE(n) (DDRC_PERF_CNT_VALUE_BASE + 8 * (n))
> +#define CN10K_DDRC_PERF_CNT_VALUE_BASE 0x8080
>
> /* Fixed event counter enable/disable register */
> -#define DDRC_PERF_CNT_FREERUN_EN 0x80C0
> +#define CN10K_DDRC_PERF_CNT_FREERUN_EN 0x80C0
> #define DDRC_PERF_FREERUN_WRITE_EN 0x1
> #define DDRC_PERF_FREERUN_READ_EN 0x2
>
> /* Fixed event counter control register */
> -#define DDRC_PERF_CNT_FREERUN_CTRL 0x80C8
> +#define CN10K_DDRC_PERF_CNT_FREERUN_CTRL 0x80C8
> #define DDRC_FREERUN_WRITE_CNT_CLR 0x1
> #define DDRC_FREERUN_READ_CNT_CLR 0x2
>
> -/* Fixed event counter value register */
> -#define DDRC_PERF_CNT_VALUE_WR_OP 0x80D0
> -#define DDRC_PERF_CNT_VALUE_RD_OP 0x80D8
> #define DDRC_PERF_CNT_VALUE_OVERFLOW BIT_ULL(48)
> #define DDRC_PERF_CNT_MAX_VALUE GENMASK_ULL(48, 0)
>
> +/* Fixed event counter value register */
> +#define CN10K_DDRC_PERF_CNT_VALUE_WR_OP 0x80D0
> +#define CN10K_DDRC_PERF_CNT_VALUE_RD_OP 0x80D8
> +
> +enum mrvl_ddr_pmu_version {
> + DDR_PMU_V1 = 1,
> +};
> +
> +struct ddr_pmu_data {
> + int id;
> +};
> +
> struct cn10k_ddr_pmu {
> struct pmu pmu;
> void __iomem *base;
> + const struct ddr_pmu_platform_data *p_data;
> + int version;
> unsigned int cpu;
> struct device *dev;
> int active_events;
> @@ -132,8 +145,35 @@ struct cn10k_ddr_pmu {
> struct hlist_node node;
> };
>
> +struct ddr_pmu_ops {
> + void (*enable_read_freerun_counter)(struct cn10k_ddr_pmu *pmu,
> + bool enable);
> + void (*enable_write_freerun_counter)(struct cn10k_ddr_pmu *pmu,
> + bool enable);
> + void (*clear_read_freerun_counter)(struct cn10k_ddr_pmu *pmu);
> + void (*clear_write_freerun_counter)(struct cn10k_ddr_pmu *pmu);
> + void (*pmu_overflow_handler)(struct cn10k_ddr_pmu *pmu, int evt_idx);
> +};
> +
> #define to_cn10k_ddr_pmu(p) container_of(p, struct cn10k_ddr_pmu, pmu)
>
> +struct ddr_pmu_platform_data {
> + u64 counter_overflow_val;
> + u64 counter_max_val;
> + u64 ddrc_perf_cnt_base;
> + u64 ddrc_perf_cfg_base;
> + u64 ddrc_perf_cnt_op_mode_ctrl;
> + u64 ddrc_perf_cnt_start_op_ctrl;
> + u64 ddrc_perf_cnt_end_op_ctrl;
> + u64 ddrc_perf_cnt_end_status;
> + u64 ddrc_perf_cnt_freerun_en;
> + u64 ddrc_perf_cnt_freerun_ctrl;
> + u64 ddrc_perf_cnt_freerun_clr;
> + u64 ddrc_perf_cnt_value_wr_op;
> + u64 ddrc_perf_cnt_value_rd_op;
> + const struct ddr_pmu_ops *ops;
> +};
> +
> static ssize_t cn10k_ddr_pmu_event_show(struct device *dev,
> struct device_attribute *attr,
> char *page)
> @@ -189,9 +229,9 @@ static struct attribute *cn10k_ddr_perf_events_attrs[] = {
> CN10K_DDR_PMU_EVENT_ATTR(ddr_zqcl, EVENT_OP_IS_ZQCL),
> CN10K_DDR_PMU_EVENT_ATTR(ddr_cam_wr_access, EVENT_OP_IS_ZQCS),
> CN10K_DDR_PMU_EVENT_ATTR(ddr_hpr_req_with_nocredit,
> - EVENT_HPR_REQ_WITH_NOCREDIT),
> + EVENT_DFI_OR_HPR_REQ_NOCRED),
> CN10K_DDR_PMU_EVENT_ATTR(ddr_lpr_req_with_nocredit,
> - EVENT_LPR_REQ_WITH_NOCREDIT),
> + EVENT_RETRY_FIFO_FULL_OR_LPR_REQ_NOCRED),
> CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_alloc, EVENT_BSM_ALLOC),
> CN10K_DDR_PMU_EVENT_ATTR(ddr_bsm_starvation, EVENT_BSM_STARVATION),
> CN10K_DDR_PMU_EVENT_ATTR(ddr_win_limit_reached_rd,
> @@ -266,7 +306,8 @@ static ktime_t cn10k_ddr_pmu_timer_period(void)
> return ms_to_ktime((u64)cn10k_ddr_pmu_poll_period_sec * USEC_PER_SEC);
> }
>
> -static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap)
> +static int ddr_perf_get_event_bitmap(int eventid, u64 *event_bitmap,
> + struct cn10k_ddr_pmu *ddr_pmu)
> {
> switch (eventid) {
> case EVENT_HIF_RD_OR_WR ... EVENT_WAW_HAZARD:
> @@ -354,6 +395,8 @@ static int cn10k_ddr_perf_event_init(struct perf_event *event)
> static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
> int counter, bool enable)
> {
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + const struct ddr_pmu_ops *ops = p_data->ops;
> u32 reg;
> u64 val;
>
> @@ -363,7 +406,7 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
> }
>
> if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
> - reg = DDRC_PERF_CFG(counter);
> + reg = DDRC_PERF_CFG(p_data->ddrc_perf_cfg_base, counter);
> val = readq_relaxed(pmu->base + reg);
>
> if (enable)
> @@ -373,19 +416,10 @@ static void cn10k_ddr_perf_counter_enable(struct cn10k_ddr_pmu *pmu,
>
> writeq_relaxed(val, pmu->base + reg);
> } else {
> - val = readq_relaxed(pmu->base + DDRC_PERF_CNT_FREERUN_EN);
> - if (enable) {
> - if (counter == DDRC_PERF_READ_COUNTER_IDX)
> - val |= DDRC_PERF_FREERUN_READ_EN;
> - else
> - val |= DDRC_PERF_FREERUN_WRITE_EN;
> - } else {
> - if (counter == DDRC_PERF_READ_COUNTER_IDX)
> - val &= ~DDRC_PERF_FREERUN_READ_EN;
> - else
> - val &= ~DDRC_PERF_FREERUN_WRITE_EN;
> - }
> - writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_EN);
> + if (counter == DDRC_PERF_READ_COUNTER_IDX)
> + ops->enable_read_freerun_counter(pmu, enable);
> + else
> + ops->enable_write_freerun_counter(pmu, enable);
> }
> }
>
> @@ -393,13 +427,18 @@ static u64 cn10k_ddr_perf_read_counter(struct cn10k_ddr_pmu *pmu, int counter)
> {
> u64 val;
>
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> +
> if (counter == DDRC_PERF_READ_COUNTER_IDX)
> - return readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE_RD_OP);
> + return readq_relaxed(pmu->base +
> + p_data->ddrc_perf_cnt_value_rd_op);
>
> if (counter == DDRC_PERF_WRITE_COUNTER_IDX)
> - return readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE_WR_OP);
> + return readq_relaxed(pmu->base +
> + p_data->ddrc_perf_cnt_value_wr_op);
>
> - val = readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE(counter));
> + val = readq_relaxed(pmu->base +
> + DDRC_PERF_REG(p_data->ddrc_perf_cnt_base, counter));
> return val;
> }
>
> @@ -407,6 +446,7 @@ static void cn10k_ddr_perf_event_update(struct perf_event *event)
> {
> struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
> struct hw_perf_event *hwc = &event->hw;
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> u64 prev_count, new_count, mask;
>
> do {
> @@ -414,7 +454,7 @@ static void cn10k_ddr_perf_event_update(struct perf_event *event)
> new_count = cn10k_ddr_perf_read_counter(pmu, hwc->idx);
> } while (local64_xchg(&hwc->prev_count, new_count) != prev_count);
>
> - mask = DDRC_PERF_CNT_MAX_VALUE;
> + mask = p_data->counter_max_val;
>
> local64_add((new_count - prev_count) & mask, &event->count);
> }
> @@ -435,6 +475,8 @@ static void cn10k_ddr_perf_event_start(struct perf_event *event, int flags)
> static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
> {
> struct cn10k_ddr_pmu *pmu = to_cn10k_ddr_pmu(event->pmu);
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + const struct ddr_pmu_ops *ops = p_data->ops;
> struct hw_perf_event *hwc = &event->hw;
> u8 config = event->attr.config;
> int counter, ret;
> @@ -454,8 +496,8 @@ static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
>
> if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
> /* Generic counters, configure event id */
> - reg_offset = DDRC_PERF_CFG(counter);
> - ret = ddr_perf_get_event_bitmap(config, &val);
> + reg_offset = DDRC_PERF_CFG(p_data->ddrc_perf_cfg_base, counter);
> + ret = ddr_perf_get_event_bitmap(config, &val, pmu);
> if (ret)
> return ret;
>
> @@ -463,11 +505,9 @@ static int cn10k_ddr_perf_event_add(struct perf_event *event, int flags)
> } else {
> /* fixed event counter, clear counter value */
> if (counter == DDRC_PERF_READ_COUNTER_IDX)
> - val = DDRC_FREERUN_READ_CNT_CLR;
> + ops->clear_read_freerun_counter(pmu);
> else
> - val = DDRC_FREERUN_WRITE_CNT_CLR;
> -
> - writeq_relaxed(val, pmu->base + DDRC_PERF_CNT_FREERUN_CTRL);
> + ops->clear_write_freerun_counter(pmu);
> }
>
> hwc->state |= PERF_HES_STOPPED;
> @@ -512,17 +552,19 @@ static void cn10k_ddr_perf_event_del(struct perf_event *event, int flags)
> static void cn10k_ddr_perf_pmu_enable(struct pmu *pmu)
> {
> struct cn10k_ddr_pmu *ddr_pmu = to_cn10k_ddr_pmu(pmu);
> + const struct ddr_pmu_platform_data *p_data = ddr_pmu->p_data;
>
> writeq_relaxed(START_OP_CTRL_VAL_START, ddr_pmu->base +
> - DDRC_PERF_CNT_START_OP_CTRL);
> + p_data->ddrc_perf_cnt_start_op_ctrl);
> }
>
> static void cn10k_ddr_perf_pmu_disable(struct pmu *pmu)
> {
> struct cn10k_ddr_pmu *ddr_pmu = to_cn10k_ddr_pmu(pmu);
> + const struct ddr_pmu_platform_data *p_data = ddr_pmu->p_data;
>
> writeq_relaxed(END_OP_CTRL_VAL_END, ddr_pmu->base +
> - DDRC_PERF_CNT_END_OP_CTRL);
> + p_data->ddrc_perf_cnt_end_op_ctrl);
> }
>
> static void cn10k_ddr_perf_event_update_all(struct cn10k_ddr_pmu *pmu)
> @@ -547,8 +589,63 @@ static void cn10k_ddr_perf_event_update_all(struct cn10k_ddr_pmu *pmu)
> }
> }
>
> +static void ddr_pmu_enable_read_freerun(struct cn10k_ddr_pmu *pmu, bool enable)
> +{
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + u64 val;
> +
> + val = readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_en);
> + if (enable)
> + val |= DDRC_PERF_FREERUN_READ_EN;
> + else
> + val &= ~DDRC_PERF_FREERUN_READ_EN;
> +
> + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_en);
> +}
> +
> +static void ddr_pmu_enable_write_freerun(struct cn10k_ddr_pmu *pmu, bool enable)
> +{
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + u64 val;
> +
> + val = readq_relaxed(pmu->base + p_data->ddrc_perf_cnt_freerun_en);
> + if (enable)
> + val |= DDRC_PERF_FREERUN_WRITE_EN;
> + else
> + val &= ~DDRC_PERF_FREERUN_WRITE_EN;
> +
> + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_en);
> +}
> +
> +static void ddr_pmu_read_clear_freerun(struct cn10k_ddr_pmu *pmu)
> +{
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + u64 val;
> +
> + val = DDRC_FREERUN_READ_CNT_CLR;
> + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
> +}
> +
> +static void ddr_pmu_write_clear_freerun(struct cn10k_ddr_pmu *pmu)
> +{
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + u64 val;
> +
> + val = DDRC_FREERUN_WRITE_CNT_CLR;
> + writeq_relaxed(val, pmu->base + p_data->ddrc_perf_cnt_freerun_ctrl);
> +}
> +
> +static void ddr_pmu_overflow_hander(struct cn10k_ddr_pmu *pmu, int evt_idx)
> +{
> + cn10k_ddr_perf_event_update_all(pmu);
> + cn10k_ddr_perf_pmu_disable(&pmu->pmu);
> + cn10k_ddr_perf_pmu_enable(&pmu->pmu);
> +}
> +
> static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pmu)
> {
> + const struct ddr_pmu_platform_data *p_data = pmu->p_data;
> + const struct ddr_pmu_ops *ops = p_data->ops;
> struct perf_event *event;
> struct hw_perf_event *hwc;
> u64 prev_count, new_count;
> @@ -586,11 +683,9 @@ static irqreturn_t cn10k_ddr_pmu_overflow_handler(struct cn10k_ddr_pmu *pmu)
> continue;
>
> value = cn10k_ddr_perf_read_counter(pmu, i);
> - if (value == DDRC_PERF_CNT_MAX_VALUE) {
> + if (value == p_data->counter_max_val) {
> pr_info("Counter-(%d) reached max value\n", i);
> - cn10k_ddr_perf_event_update_all(pmu);
> - cn10k_ddr_perf_pmu_disable(&pmu->pmu);
> - cn10k_ddr_perf_pmu_enable(&pmu->pmu);
> + ops->pmu_overflow_handler(pmu, i);
> }
> }
>
> @@ -629,13 +724,44 @@ static int cn10k_ddr_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
> return 0;
> }
>
> +static const struct ddr_pmu_ops ddr_pmu_ops = {
> + .enable_read_freerun_counter = ddr_pmu_enable_read_freerun,
> + .enable_write_freerun_counter = ddr_pmu_enable_write_freerun,
> + .clear_read_freerun_counter = ddr_pmu_read_clear_freerun,
> + .clear_write_freerun_counter = ddr_pmu_write_clear_freerun,
> + .pmu_overflow_handler = ddr_pmu_overflow_hander,
> +};
> +
> +static const struct ddr_pmu_platform_data cn10k_ddr_pmu_pdata = {
> + .counter_overflow_val = BIT_ULL(48),
> + .counter_max_val = GENMASK_ULL(48, 0),
> + .ddrc_perf_cnt_base = CN10K_DDRC_PERF_CNT_VALUE_BASE,
> + .ddrc_perf_cfg_base = CN10K_DDRC_PERF_CFG_BASE,
> + .ddrc_perf_cnt_op_mode_ctrl = CN10K_DDRC_PERF_CNT_OP_MODE_CTRL,
> + .ddrc_perf_cnt_start_op_ctrl = CN10K_DDRC_PERF_CNT_START_OP_CTRL,
> + .ddrc_perf_cnt_end_op_ctrl = CN10K_DDRC_PERF_CNT_END_OP_CTRL,
> + .ddrc_perf_cnt_end_status = CN10K_DDRC_PERF_CNT_END_STATUS,
> + .ddrc_perf_cnt_freerun_en = CN10K_DDRC_PERF_CNT_FREERUN_EN,
> + .ddrc_perf_cnt_freerun_ctrl = CN10K_DDRC_PERF_CNT_FREERUN_CTRL,
> + .ddrc_perf_cnt_freerun_clr = 0,
> + .ddrc_perf_cnt_value_wr_op = CN10K_DDRC_PERF_CNT_VALUE_WR_OP,
> + .ddrc_perf_cnt_value_rd_op = CN10K_DDRC_PERF_CNT_VALUE_RD_OP,
> + .ops = &ddr_pmu_ops,
> +};
> +
> +static const struct ddr_pmu_data ddr_pmu_data = {
> + .id = DDR_PMU_V1,
> +};
> +
> static int cn10k_ddr_perf_probe(struct platform_device *pdev)
> {
> + const struct ddr_pmu_data *dev_data;
> struct cn10k_ddr_pmu *ddr_pmu;
> struct resource *res;
> void __iomem *base;
> char *name;
> int ret;
> + int version;
>
> ddr_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddr_pmu), GFP_KERNEL);
> if (!ddr_pmu)
> @@ -644,30 +770,42 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
> ddr_pmu->dev = &pdev->dev;
> platform_set_drvdata(pdev, ddr_pmu);
>
> + dev_data = device_get_match_data(&pdev->dev);
> + if (!dev_data) {
> + dev_err(&pdev->dev, "Error: No device match data found\n");
> + return -ENODEV;
> + }
> + version = dev_data->id;
> + ddr_pmu->version = version;
> +
> base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> ddr_pmu->base = base;
>
> - /* Setup the PMU counter to work in manual mode */
> - writeq_relaxed(OP_MODE_CTRL_VAL_MANNUAL, ddr_pmu->base +
> - DDRC_PERF_CNT_OP_MODE_CTRL);
> -
> - ddr_pmu->pmu = (struct pmu) {
> - .module = THIS_MODULE,
> - .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
> - .task_ctx_nr = perf_invalid_context,
> - .attr_groups = cn10k_attr_groups,
> - .event_init = cn10k_ddr_perf_event_init,
> - .add = cn10k_ddr_perf_event_add,
> - .del = cn10k_ddr_perf_event_del,
> - .start = cn10k_ddr_perf_event_start,
> - .stop = cn10k_ddr_perf_event_stop,
> - .read = cn10k_ddr_perf_event_update,
> - .pmu_enable = cn10k_ddr_perf_pmu_enable,
> - .pmu_disable = cn10k_ddr_perf_pmu_disable,
> - };
> + if (version == DDR_PMU_V1) {
> + /* Setup the PMU counter to work in manual mode */
> + writeq_relaxed(OP_MODE_CTRL_VAL_MANUAL, ddr_pmu->base +
> + (ddr_pmu->p_data->ddrc_perf_cnt_op_mode_ctrl));
> +
> + ddr_pmu->pmu = (struct pmu) {
> + .module = THIS_MODULE,
> + .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
> + .task_ctx_nr = perf_invalid_context,
> + .attr_groups = cn10k_attr_groups,
> + .event_init = cn10k_ddr_perf_event_init,
> + .add = cn10k_ddr_perf_event_add,
> + .del = cn10k_ddr_perf_event_del,
> + .start = cn10k_ddr_perf_event_start,
> + .stop = cn10k_ddr_perf_event_stop,
> + .read = cn10k_ddr_perf_event_update,
> + .pmu_enable = cn10k_ddr_perf_pmu_enable,
> + .pmu_disable = cn10k_ddr_perf_pmu_disable,
> + };
> +
> + ddr_pmu->p_data = &cn10k_ddr_pmu_pdata;
> + }
>
> /* Choose this cpu to collect perf data */
> ddr_pmu->cpu = raw_smp_processor_id();
> @@ -688,7 +826,7 @@ static int cn10k_ddr_perf_probe(struct platform_device *pdev)
> if (ret)
> goto error;
>
> - pr_info("CN10K DDR PMU Driver for ddrc@%llx\n", res->start);
> + pr_info("DDR PMU Driver for ddrc@%llx\n", res->start);
> return 0;
> error:
> cpuhp_state_remove_instance_nocalls(
> @@ -711,7 +849,7 @@ static int cn10k_ddr_perf_remove(struct platform_device *pdev)
>
> #ifdef CONFIG_OF
> static const struct of_device_id cn10k_ddr_pmu_of_match[] = {
> - { .compatible = "marvell,cn10k-ddr-pmu", },
> + { .compatible = "marvell,cn10k-ddr-pmu", .data = &ddr_pmu_data},
> { },
> };
> MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
> @@ -719,7 +857,7 @@ MODULE_DEVICE_TABLE(of, cn10k_ddr_pmu_of_match);
>
> #ifdef CONFIG_ACPI
> static const struct acpi_device_id cn10k_ddr_pmu_acpi_match[] = {
> - {"MRVL000A", 0},
> + {"MRVL000A", (kernel_ulong_t)&ddr_pmu_data},
> {},
> };
> MODULE_DEVICE_TABLE(acpi, cn10k_ddr_pmu_acpi_match);
> --
> 2.25.1