From: Claudiu Beznea <[email protected]>
Hi,
Series adds support for power domains on rzg2l driver.
RZ/G2L kind of devices support a functionality called MSTOP (module
stop/standby). According to hardware manual the module could be switch
to standby after its clocks are disabled. The reverse order of operation
should be done when enabling a module (get the module out of standby,
enable its clocks etc).
In [1] the MSTOP settings were implemented by adding code in driver
to attach the MSTOP state to the IP clocks. But it has been proposed
to implement it as power domain. The result is this series.
The DT bindings were updated with power domain IDs (plain integers
that matches the DT with driver data structures). The current DT
bindings were updated with module IDs for the modules listed in tables
with name "Registers for Module Standby Mode" (see HW manual) exception
being RZ/G3S where, due to the power down functionality, the DDR,
TZCDDR, OTFDE_DDR were also added.
Domain IDs were added to all SoC specific bindings.
Thank you,
Claudiu Beznea
Changes in v4:
- dropped the pwrdn functionality until it is better understanded
- dropped patch "clk: renesas: rzg2l-cpg: Add suspend/resume
support for power domains" from v3; this will be replaced
by propertly calling device_set_wakup_path() in serial console
driver
- instantiated the watchdog domain in r8a08g045 clock driver; this
allow applying r9a08g045 clock patch w/o affecting watchdog and later,
after all good with watchdog patches series at [2], only patch
"arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>"
will need to be applied
Changes in v3:
- collected tags
- dinamically detect if a SCIF is serial console and populate
pd->suspend_check
- dropped patch 09/10 from v2
Changes in v2:
- addressed review comments
- dropped:
- dt-bindings: clock: r9a09g011-cpg: Add always-on power domain IDs
- clk: renesas: r9a07g043: Add initial support for power domains
- clk: renesas: r9a07g044: Add initial support for power domains
- clk: renesas: r9a09g011: Add initial support for power domains
- clk: renesas: r9a09g011: Add initial support for power domains
- arm64: dts: renesas: r9a07g043: Update #power-domain-cells = <1>
- arm64: dts: renesas: r9a07g044: Update #power-domain-cells = <1>
- arm64: dts: renesas: r9a07g054: Update #power-domain-cells = <1>
- arm64: dts: renesas: r9a09g011: Update #power-domain-cells = <1>
as suggested in the review process
- dropped "arm64: dts: renesas: rzg3s-smarc-som: Guard the ethernet IRQ
GPIOs with proper flags" patch as it was integrated
- added suspend to RAM support
- collected tag
[1] https://lore.kernel.org/all/[email protected]/
[2] https://lore.kernel.org/all/[email protected]/
Claudiu Beznea (8):
dt-bindings: clock: r9a07g043-cpg: Add power domain IDs
dt-bindings: clock: r9a07g044-cpg: Add power domain IDs
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
dt-bindings: clock: r9a08g045-cpg: Add power domain IDs
dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells =
<1> for RZ/G3S
clk: renesas: rzg2l: Extend power domain support
clk: renesas: r9a08g045: Add support for power domains
arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>
.../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +-
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 +-
drivers/clk/renesas/r9a08g045-cpg.c | 41 ++++
drivers/clk/renesas/rzg2l-cpg.c | 199 ++++++++++++++++--
drivers/clk/renesas/rzg2l-cpg.h | 67 ++++++
include/dt-bindings/clock/r9a07g043-cpg.h | 52 +++++
include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++
include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++
include/dt-bindings/clock/r9a08g045-cpg.h | 70 ++++++
9 files changed, 558 insertions(+), 25 deletions(-)
--
2.39.2
From: Claudiu Beznea <[email protected]>
Add power domain IDs for RZ/G2UL (R9A07G043) SoC.
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- added "RZ/G2UL Only" comments to some defines
- added RZ/Five specific defines
include/dt-bindings/clock/r9a07g043-cpg.h | 52 +++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index a64139fec815..131993343777 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -200,5 +200,57 @@
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
+/* Power domain IDs. */
+#define R9A07G043_PD_ALWAYS_ON 0
+#define R9A07G043_PD_GIC 1 /* RZ/G2UL Only */
+#define R9A07G043_PD_IA55 2 /* RZ/G2UL Only */
+#define R9A07G043_PD_MHU 3 /* RZ/G2UL Only */
+#define R9A07G043_PD_CORESIGHT 4 /* RZ/G2UL Only */
+#define R9A07G043_PD_SYC 5 /* RZ/G2UL Only */
+#define R9A07G043_PD_DMAC 6
+#define R9A07G043_PD_GTM0 7
+#define R9A07G043_PD_GTM1 8
+#define R9A07G043_PD_GTM2 9
+#define R9A07G043_PD_MTU 10
+#define R9A07G043_PD_POE3 11
+#define R9A07G043_PD_WDT0 12
+#define R9A07G043_PD_SPI 13
+#define R9A07G043_PD_SDHI0 14
+#define R9A07G043_PD_SDHI1 15
+#define R9A07G043_PD_ISU 16 /* RZ/G2UL Only */
+#define R9A07G043_PD_CRU 17 /* RZ/G2UL Only */
+#define R9A07G043_PD_LCDC 18 /* RZ/G2UL Only */
+#define R9A07G043_PD_SSI0 19
+#define R9A07G043_PD_SSI1 20
+#define R9A07G043_PD_SSI2 21
+#define R9A07G043_PD_SSI3 22
+#define R9A07G043_PD_SRC 23
+#define R9A07G043_PD_USB0 24
+#define R9A07G043_PD_USB1 25
+#define R9A07G043_PD_USB_PHY 26
+#define R9A07G043_PD_ETHER0 27
+#define R9A07G043_PD_ETHER1 28
+#define R9A07G043_PD_I2C0 29
+#define R9A07G043_PD_I2C1 30
+#define R9A07G043_PD_I2C2 31
+#define R9A07G043_PD_I2C3 32
+#define R9A07G043_PD_SCIF0 33
+#define R9A07G043_PD_SCIF1 34
+#define R9A07G043_PD_SCIF2 35
+#define R9A07G043_PD_SCIF3 36
+#define R9A07G043_PD_SCIF4 37
+#define R9A07G043_PD_SCI0 38
+#define R9A07G043_PD_SCI1 39
+#define R9A07G043_PD_IRDA 40
+#define R9A07G043_PD_RSPI0 41
+#define R9A07G043_PD_RSPI1 42
+#define R9A07G043_PD_RSPI2 43
+#define R9A07G043_PD_CANFD 44
+#define R9A07G043_PD_ADC 45
+#define R9A07G043_PD_TSU 46
+#define R9A07G043_PD_PLIC 47 /* RZ/Five Only */
+#define R9A07G043_PD_IAX45 48 /* RZ/Five Only */
+#define R9A07G043_PD_NCEPLDM 49 /* RZ/Five Only */
+#define R9A07G043_PD_NCEPLMT 50 /* RZ/Five Only */
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
--
2.39.2
From: Claudiu Beznea <[email protected]>
Add power domain IDs for RZ/V2L (R9A07G054) SoC.
Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- collected tag
include/dt-bindings/clock/r9a07g054-cpg.h | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
index 43f4dbda872c..2c99f89397c4 100644
--- a/include/dt-bindings/clock/r9a07g054-cpg.h
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -226,4 +226,62 @@
#define R9A07G054_TSU_PRESETN 83
#define R9A07G054_STPAI_ARESETN 84
+/* Power domain IDs. */
+#define R9A07G054_PD_ALWAYS_ON 0
+#define R9A07G054_PD_GIC 1
+#define R9A07G054_PD_IA55 2
+#define R9A07G054_PD_MHU 3
+#define R9A07G054_PD_CORESIGHT 4
+#define R9A07G054_PD_SYC 5
+#define R9A07G054_PD_DMAC 6
+#define R9A07G054_PD_GTM0 7
+#define R9A07G054_PD_GTM1 8
+#define R9A07G054_PD_GTM2 9
+#define R9A07G054_PD_MTU 10
+#define R9A07G054_PD_POE3 11
+#define R9A07G054_PD_GPT 12
+#define R9A07G054_PD_POEGA 13
+#define R9A07G054_PD_POEGB 14
+#define R9A07G054_PD_POEGC 15
+#define R9A07G054_PD_POEGD 16
+#define R9A07G054_PD_WDT0 17
+#define R9A07G054_PD_WDT1 18
+#define R9A07G054_PD_SPI 19
+#define R9A07G054_PD_SDHI0 20
+#define R9A07G054_PD_SDHI1 21
+#define R9A07G054_PD_3DGE 22
+#define R9A07G054_PD_ISU 23
+#define R9A07G054_PD_VCPL4 24
+#define R9A07G054_PD_CRU 25
+#define R9A07G054_PD_MIPI_DSI 26
+#define R9A07G054_PD_LCDC 27
+#define R9A07G054_PD_SSI0 28
+#define R9A07G054_PD_SSI1 29
+#define R9A07G054_PD_SSI2 30
+#define R9A07G054_PD_SSI3 31
+#define R9A07G054_PD_SRC 32
+#define R9A07G054_PD_USB0 33
+#define R9A07G054_PD_USB1 34
+#define R9A07G054_PD_USB_PHY 35
+#define R9A07G054_PD_ETHER0 36
+#define R9A07G054_PD_ETHER1 37
+#define R9A07G054_PD_I2C0 38
+#define R9A07G054_PD_I2C1 39
+#define R9A07G054_PD_I2C2 40
+#define R9A07G054_PD_I2C3 41
+#define R9A07G054_PD_SCIF0 42
+#define R9A07G054_PD_SCIF1 43
+#define R9A07G054_PD_SCIF2 44
+#define R9A07G054_PD_SCIF3 45
+#define R9A07G054_PD_SCIF4 46
+#define R9A07G054_PD_SCI0 47
+#define R9A07G054_PD_SCI1 48
+#define R9A07G054_PD_IRDA 49
+#define R9A07G054_PD_RSPI0 50
+#define R9A07G054_PD_RSPI1 51
+#define R9A07G054_PD_RSPI2 52
+#define R9A07G054_PD_CANFD 53
+#define R9A07G054_PD_ADC 54
+#define R9A07G054_PD_TSU 55
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
--
2.39.2
From: Claudiu Beznea <[email protected]>
The driver will be modified (in the next commits) to be able to specify
individual power domain ID for each IP. The driver will still
support #power-domain-cells = <0>, thus, previous users are not
affected.
The #power-domain-cells = <1> has been instantiated only for RZ/G3S at
the moment as individual platform clock drivers need to be adapted for
this to be supported on the rest of the SoCs.
Also, the description for #power-domain-cells was updated with the links
to per-SoC power domain IDs.
Reviewed-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- updated patch title and description
- kept both 0 and 1 for #power-domain-cells as not all the drivers,
device trees are adpated with this series
- added a reference to dt-bindings/clock/r9a0*-cpg.h for power domain
specifiers
- dropped the changes from examples section
.../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 80a8c7114c31..4e3b0c45124a 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -57,7 +57,8 @@ properties:
can be power-managed through Module Standby should refer to the CPG device
node in their "power-domains" property, as documented by the generic PM
Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
- const: 0
+ The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
+ be used to reference individual CPG power domains.
'#reset-cells':
description:
@@ -76,6 +77,21 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a08g045-cpg
+ then:
+ properties:
+ '#power-domain-cells':
+ const: 1
+ else:
+ properties:
+ '#power-domain-cells':
+ const: 0
+
examples:
- |
cpg: clock-controller@11010000 {
--
2.39.2
From: Claudiu Beznea <[email protected]>
RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
power when clocks are disabled by activating module standby. This is done
through MSTOP-specific registers that are part of CPG. Each individual
module has one or more bits associated with one MSTOP register (see table
"Registers for Module Standby Mode" from HW manuals). Hardware manual
associates modules' clocks with one or more MSTOP bits. There are 3
mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW
manuals):
case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X})
case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, ..., Y})
Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
To cover all three cases, the individual platform drivers will provide to
clock driver MSTOP register offset and associated bits in this register
as a bitmask and the clock driver will apply this bitmask to proper
MSTOP register.
The MSTOP was implemented through power domains. Platform-specific clock
drivers will register an array of type
struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate
properly the power domains.
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v2:
- dropped the pwrdn functionality until it is better understanded;
at the same time kept the code ready for pwrd being added by keeping
struct rzg2l_cpg_pm_domain_conf, DEF_REG_CONF(); please let me know
if you prefer otherwise
- @Geert, @Ulf: I dropped your previous Rb tags due to dropping pwrdn
Changes in v3:
- collected tags
Changes in v2:
- called pm_genpd_init() with proper value for is_off argument
- fixed typos
- used flexible array for struct rzg2l_cpg_pm_domains::domains member
- moved genpd member of struct rzg2l_cpg_pd at the beginning of struct
- didn't initialize the parent variable in rzg2l_cpg_add_pm_domains()
as it is already initialized in the for block from
rzg2l_cpg_add_pm_domains() and that initialization should be enough
- dropped RZG2L_PD_F_PARENT flag
- used datasheet naming for all MSTOP registers
- added all MSTOP registers to rzg2l-cpg.h
- reworked the code that initializes the register offset and bits for domains
- dropped MSTOP*(), PWRDN*() macros and introduced struct rzg2l_cpg_reg_conf
and DEF_REG_CONF() for domain description
- constified the 1st argument of rzg2l_cpg_pm_domain_xlate()
- used dev instead of priv->dev where possible
- dropped RZG2L_PD_F_PARENT
- added RZG2L_PD_F_NONE for better description of domains in platform
specific clock drivers
drivers/clk/renesas/rzg2l-cpg.c | 199 +++++++++++++++++++++++++++++---
drivers/clk/renesas/rzg2l-cpg.h | 67 +++++++++++
2 files changed, 252 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3d2daa4ba2a4..04b78064d4e0 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -139,7 +139,6 @@ struct rzg2l_pll5_mux_dsi_div_param {
* @num_resets: Number of Module Resets in info->resets[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @info: Pointer to platform data
- * @genpd: PM domain
* @mux_dsi_div_params: pll5 mux and dsi div parameters
*/
struct rzg2l_cpg_priv {
@@ -156,8 +155,6 @@ struct rzg2l_cpg_priv {
const struct rzg2l_cpg_info *info;
- struct generic_pm_domain genpd;
-
struct rzg2l_pll5_mux_dsi_div_param mux_dsi_div_params;
};
@@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cpg_priv *priv,
return true;
}
+/**
+ * struct rzg2l_cpg_pm_domains - RZ/G2L PM domains data structure
+ * @onecell_data: cell data
+ * @domains: generic PM domains
+ */
+struct rzg2l_cpg_pm_domains {
+ struct genpd_onecell_data onecell_data;
+ struct generic_pm_domain *domains[];
+};
+
+/**
+ * struct rzg2l_cpg_pd - RZ/G2L power domain data structure
+ * @genpd: generic PM domain
+ * @priv: pointer to CPG private data structure
+ * @conf: CPG PM domain configuration info
+ * @id: RZ/G2L power domain ID
+ */
+struct rzg2l_cpg_pd {
+ struct generic_pm_domain genpd;
+ struct rzg2l_cpg_priv *priv;
+ struct rzg2l_cpg_pm_domain_conf conf;
+ u16 id;
+};
+
static int rzg2l_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
{
- struct rzg2l_cpg_priv *priv = container_of(domain, struct rzg2l_cpg_priv, genpd);
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_priv *priv = pd->priv;
struct device_node *np = dev->of_node;
struct of_phandle_args clkspec;
bool once = true;
@@ -1617,31 +1639,180 @@ static void rzg2l_cpg_detach_dev(struct generic_pm_domain *unused, struct device
}
static void rzg2l_cpg_genpd_remove(void *data)
+{
+ struct genpd_onecell_data *celldata = data;
+
+ for (unsigned int i = 0; i < celldata->num_domains; i++)
+ pm_genpd_remove(celldata->domains[i]);
+}
+
+static void rzg2l_cpg_genpd_remove_simple(void *data)
{
pm_genpd_remove(data);
}
+static int rzg2l_cpg_power_on(struct generic_pm_domain *domain)
+{
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
+ struct rzg2l_cpg_priv *priv = pd->priv;
+
+ /* Set MSTOP. */
+ if (mstop.mask)
+ writel(mstop.mask << 16, priv->base + mstop.off);
+
+ return 0;
+}
+
+static int rzg2l_cpg_power_off(struct generic_pm_domain *domain)
+{
+ struct rzg2l_cpg_pd *pd = container_of(domain, struct rzg2l_cpg_pd, genpd);
+ struct rzg2l_cpg_reg_conf mstop = pd->conf.mstop;
+ struct rzg2l_cpg_priv *priv = pd->priv;
+
+ /* Set MSTOP. */
+ if (mstop.mask)
+ writel(mstop.mask | (mstop.mask << 16), priv->base + mstop.off);
+
+ return 0;
+}
+
+static int __init rzg2l_cpg_pd_setup(struct rzg2l_cpg_pd *pd, bool always_on)
+{
+ struct dev_power_governor *governor;
+
+ pd->genpd.flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+ pd->genpd.attach_dev = rzg2l_cpg_attach_dev;
+ pd->genpd.detach_dev = rzg2l_cpg_detach_dev;
+ if (always_on) {
+ pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON;
+ governor = &pm_domain_always_on_gov;
+ } else {
+ pd->genpd.power_on = rzg2l_cpg_power_on;
+ pd->genpd.power_off = rzg2l_cpg_power_off;
+ governor = &simple_qos_governor;
+ }
+
+ return pm_genpd_init(&pd->genpd, governor, !always_on);
+}
+
static int __init rzg2l_cpg_add_clk_domain(struct rzg2l_cpg_priv *priv)
{
struct device *dev = priv->dev;
struct device_node *np = dev->of_node;
- struct generic_pm_domain *genpd = &priv->genpd;
+ struct rzg2l_cpg_pd *pd;
+ int ret;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = np->name;
+ pd->priv = priv;
+ ret = rzg2l_cpg_pd_setup(pd, true);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove_simple, &pd->genpd);
+ if (ret)
+ return ret;
+
+ return of_genpd_add_provider_simple(np, &pd->genpd);
+}
+
+static struct generic_pm_domain *
+rzg2l_cpg_pm_domain_xlate(const struct of_phandle_args *spec, void *data)
+{
+ struct generic_pm_domain *domain = ERR_PTR(-ENOENT);
+ struct genpd_onecell_data *genpd = data;
+
+ if (spec->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ for (unsigned int i = 0; i < genpd->num_domains; i++) {
+ struct rzg2l_cpg_pd *pd = container_of(genpd->domains[i], struct rzg2l_cpg_pd,
+ genpd);
+
+ if (pd->id == spec->args[0]) {
+ domain = &pd->genpd;
+ break;
+ }
+ }
+
+ return domain;
+}
+
+static int __init rzg2l_cpg_add_pm_domains(struct rzg2l_cpg_priv *priv)
+{
+ const struct rzg2l_cpg_info *info = priv->info;
+ struct device *dev = priv->dev;
+ struct device_node *np = dev->of_node;
+ struct rzg2l_cpg_pm_domains *domains;
+ struct generic_pm_domain *parent;
+ u32 ncells;
int ret;
- genpd->name = np->name;
- genpd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_ALWAYS_ON |
- GENPD_FLAG_ACTIVE_WAKEUP;
- genpd->attach_dev = rzg2l_cpg_attach_dev;
- genpd->detach_dev = rzg2l_cpg_detach_dev;
- ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ ret = of_property_read_u32(np, "#power-domain-cells", &ncells);
+ if (ret)
+ return ret;
+
+ /* For backward compatibility. */
+ if (!ncells)
+ return rzg2l_cpg_add_clk_domain(priv);
+
+ domains = devm_kzalloc(dev, struct_size(domains, domains, info->num_pm_domains),
+ GFP_KERNEL);
+ if (!domains)
+ return -ENOMEM;
+
+ domains->onecell_data.domains = domains->domains;
+ domains->onecell_data.num_domains = info->num_pm_domains;
+ domains->onecell_data.xlate = rzg2l_cpg_pm_domain_xlate;
+
+ ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, &domains->onecell_data);
if (ret)
return ret;
- ret = devm_add_action_or_reset(dev, rzg2l_cpg_genpd_remove, genpd);
+ for (unsigned int i = 0; i < info->num_pm_domains; i++) {
+ bool always_on = !!(info->pm_domains[i].flags & RZG2L_PD_F_ALWAYS_ON);
+ struct rzg2l_cpg_pd *pd;
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->genpd.name = info->pm_domains[i].name;
+ pd->conf = info->pm_domains[i].conf;
+ pd->id = info->pm_domains[i].id;
+ pd->priv = priv;
+
+ ret = rzg2l_cpg_pd_setup(pd, always_on);
+ if (ret)
+ return ret;
+
+ if (always_on) {
+ ret = rzg2l_cpg_power_on(&pd->genpd);
+ if (ret)
+ return ret;
+ }
+
+ domains->domains[i] = &pd->genpd;
+ /* Parent should be on the very first entry of info->pm_domains[]. */
+ if (!i) {
+ parent = &pd->genpd;
+ continue;
+ }
+
+ ret = pm_genpd_add_subdomain(parent, &pd->genpd);
+ if (ret)
+ return ret;
+ }
+
+ ret = of_genpd_add_provider_onecell(np, &domains->onecell_data);
if (ret)
return ret;
- return of_genpd_add_provider_simple(np, genpd);
+ return 0;
}
static int __init rzg2l_cpg_probe(struct platform_device *pdev)
@@ -1697,7 +1868,7 @@ static int __init rzg2l_cpg_probe(struct platform_device *pdev)
if (error)
return error;
- error = rzg2l_cpg_add_clk_domain(priv);
+ error = rzg2l_cpg_add_pm_domains(priv);
if (error)
return error;
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 6e38c8fc888c..ecfe7e7ea8a1 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -27,6 +27,18 @@
#define CPG_PL6_ETH_SSEL (0x418)
#define CPG_PL5_SDIV (0x420)
#define CPG_RST_MON (0x680)
+#define CPG_BUS_ACPU_MSTOP (0xB60)
+#define CPG_BUS_MCPU1_MSTOP (0xB64)
+#define CPG_BUS_MCPU2_MSTOP (0xB68)
+#define CPG_BUS_PERI_COM_MSTOP (0xB6C)
+#define CPG_BUS_PERI_CPU_MSTOP (0xB70)
+#define CPG_BUS_PERI_DDR_MSTOP (0xB74)
+#define CPG_BUS_REG0_MSTOP (0xB7C)
+#define CPG_BUS_REG1_MSTOP (0xB80)
+#define CPG_BUS_TZCDDR_MSTOP (0xB84)
+#define CPG_MHU_MSTOP (0xB88)
+#define CPG_BUS_MCPU3_MSTOP (0xB90)
+#define CPG_BUS_PERI_CPU2_MSTOP (0xB94)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
@@ -234,6 +246,55 @@ struct rzg2l_reset {
#define DEF_RST(_id, _off, _bit) \
DEF_RST_MON(_id, _off, _bit, -1)
+/**
+ * struct rzg2l_cpg_reg_conf - RZ/G2L register configuration data structure
+ * @off: register offset
+ * @mask: register mask
+ */
+struct rzg2l_cpg_reg_conf {
+ u16 off;
+ u16 mask;
+};
+
+#define DEF_REG_CONF(_off, _mask) ((struct rzg2l_cpg_reg_conf) { .off = (_off), .mask = (_mask) })
+
+/**
+ * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data structure
+ * @mstop: MSTOP register configuration
+ */
+struct rzg2l_cpg_pm_domain_conf {
+ struct rzg2l_cpg_reg_conf mstop;
+};
+
+/**
+ * struct rzg2l_cpg_pm_domain_init_data - PM domain init data
+ * @name: PM domain name
+ * @conf: PM domain configuration
+ * @flags: RZG2L PM domain flags (see RZG2L_PD_F_*)
+ * @id: PM domain ID (similar to the ones defined in
+ * include/dt-bindings/clock/<soc-id>-cpg.h)
+ */
+struct rzg2l_cpg_pm_domain_init_data {
+ const char * const name;
+ struct rzg2l_cpg_pm_domain_conf conf;
+ u32 flags;
+ u16 id;
+};
+
+#define DEF_PD(_name, _id, _mstop_conf, _flags) \
+ { \
+ .name = (_name), \
+ .id = (_id), \
+ .conf = { \
+ .mstop = (_mstop_conf), \
+ }, \
+ .flags = (_flags), \
+ }
+
+/* Power domain flags. */
+#define RZG2L_PD_F_ALWAYS_ON BIT(0)
+#define RZG2L_PD_F_NONE (0)
+
/**
* struct rzg2l_cpg_info - SoC-specific CPG Description
*
@@ -252,6 +313,8 @@ struct rzg2l_reset {
* @crit_mod_clks: Array with Module Clock IDs of critical clocks that
* should not be disabled without a knowledgeable driver
* @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @pm_domains: PM domains init data array
+ * @num_pm_domains: Number of PM domains
* @has_clk_mon_regs: Flag indicating whether the SoC has CLK_MON registers
*/
struct rzg2l_cpg_info {
@@ -278,6 +341,10 @@ struct rzg2l_cpg_info {
const unsigned int *crit_mod_clks;
unsigned int num_crit_mod_clks;
+ /* Power domain. */
+ const struct rzg2l_cpg_pm_domain_init_data *pm_domains;
+ unsigned int num_pm_domains;
+
bool has_clk_mon_regs;
};
--
2.39.2
From: Claudiu Beznea <[email protected]>
Update CPG #power-domain-cells = <1> and move all the IPs to be part of the
IP specific power domain as the driver has been modified to support
multiple power domains.
Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- used proper domain ID for IA55 interrupt controller
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index f5f3f4f4c8d6..bdd4f9376fc0 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -67,7 +67,7 @@ scif0: serial@1004b800 {
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
clock-names = "fck";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SCIF0>;
resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
status = "disabled";
};
@@ -79,7 +79,7 @@ cpg: clock-controller@11010000 {
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
- #power-domain-cells = <0>;
+ #power-domain-cells = <1>;
};
sysc: system-controller@11020000 {
@@ -104,7 +104,7 @@ pinctrl: pinctrl@11030000 {
interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ALWAYS_ON>;
resets = <&cpg R9A08G045_GPIO_RSTN>,
<&cpg R9A08G045_GPIO_PORT_RESETN>,
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
@@ -177,7 +177,7 @@ irqc: interrupt-controller@11050000 {
clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
clock-names = "clk", "pclk";
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_IA55>;
resets = <&cpg R9A08G045_IA55_RESETN>;
};
@@ -192,7 +192,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI0_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI0>;
status = "disabled";
};
@@ -207,7 +207,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI1_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI1>;
status = "disabled";
};
@@ -222,7 +222,7 @@ sdhi2: mmc@11c20000 {
<&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
resets = <&cpg R9A08G045_SDHI2_IXRST>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_SDHI2>;
status = "disabled";
};
@@ -239,7 +239,7 @@ eth0: ethernet@11c30000 {
<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -258,7 +258,7 @@ eth1: ethernet@11c40000 {
<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
clock-names = "axi", "chi", "refclk";
resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_ETHER1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -284,7 +284,7 @@ wdt0: watchdog@12800800 {
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G045_WDT0_PRESETN>;
- power-domains = <&cpg>;
+ power-domains = <&cpg R9A08G045_PD_WDT0>;
status = "disabled";
};
};
--
2.39.2
From: Claudiu Beznea <[email protected]>
Add power domain IDs for RZ/G2L (R9A07G044) SoC.
Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- collected tag
include/dt-bindings/clock/r9a07g044-cpg.h | 58 +++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0bb17ff1a01a..e209f96f92b7 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -217,4 +217,62 @@
#define R9A07G044_ADC_ADRST_N 82
#define R9A07G044_TSU_PRESETN 83
+/* Power domain IDs. */
+#define R9A07G044_PD_ALWAYS_ON 0
+#define R9A07G044_PD_GIC 1
+#define R9A07G044_PD_IA55 2
+#define R9A07G044_PD_MHU 3
+#define R9A07G044_PD_CORESIGHT 4
+#define R9A07G044_PD_SYC 5
+#define R9A07G044_PD_DMAC 6
+#define R9A07G044_PD_GTM0 7
+#define R9A07G044_PD_GTM1 8
+#define R9A07G044_PD_GTM2 9
+#define R9A07G044_PD_MTU 10
+#define R9A07G044_PD_POE3 11
+#define R9A07G044_PD_GPT 12
+#define R9A07G044_PD_POEGA 13
+#define R9A07G044_PD_POEGB 14
+#define R9A07G044_PD_POEGC 15
+#define R9A07G044_PD_POEGD 16
+#define R9A07G044_PD_WDT0 17
+#define R9A07G044_PD_WDT1 18
+#define R9A07G044_PD_SPI 19
+#define R9A07G044_PD_SDHI0 20
+#define R9A07G044_PD_SDHI1 21
+#define R9A07G044_PD_3DGE 22
+#define R9A07G044_PD_ISU 23
+#define R9A07G044_PD_VCPL4 24
+#define R9A07G044_PD_CRU 25
+#define R9A07G044_PD_MIPI_DSI 26
+#define R9A07G044_PD_LCDC 27
+#define R9A07G044_PD_SSI0 28
+#define R9A07G044_PD_SSI1 29
+#define R9A07G044_PD_SSI2 30
+#define R9A07G044_PD_SSI3 31
+#define R9A07G044_PD_SRC 32
+#define R9A07G044_PD_USB0 33
+#define R9A07G044_PD_USB1 34
+#define R9A07G044_PD_USB_PHY 35
+#define R9A07G044_PD_ETHER0 36
+#define R9A07G044_PD_ETHER1 37
+#define R9A07G044_PD_I2C0 38
+#define R9A07G044_PD_I2C1 39
+#define R9A07G044_PD_I2C2 40
+#define R9A07G044_PD_I2C3 41
+#define R9A07G044_PD_SCIF0 42
+#define R9A07G044_PD_SCIF1 43
+#define R9A07G044_PD_SCIF2 44
+#define R9A07G044_PD_SCIF3 45
+#define R9A07G044_PD_SCIF4 46
+#define R9A07G044_PD_SCI0 47
+#define R9A07G044_PD_SCI1 48
+#define R9A07G044_PD_IRDA 49
+#define R9A07G044_PD_RSPI0 50
+#define R9A07G044_PD_RSPI1 51
+#define R9A07G044_PD_RSPI2 52
+#define R9A07G044_PD_CANFD 53
+#define R9A07G044_PD_ADC 54
+#define R9A07G044_PD_TSU 55
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
--
2.39.2
From: Claudiu Beznea <[email protected]>
Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- dropped DEF_REG_CONF() specific to pwrdn functionality
- dropped ddr, tzcddr, oftde_ddr domains as these were there due to
the pwrdn functionality
- added wdt0 domain; this will not impact currently integrated
watchdog support
- @Geert: I dropped your previous Rb tag due to the changes in v4
Changes in v3:
- collected tags
Change in v2:
- used DEF_REG_CONF() to describe register offests and bits
- updated MSTOP bitmask for ddr domain
- updated MSTOP config for oftde_ddr
- kept the same description for gic as the CPG_BUS_ACPU_MSTOP register
documentation in the latest HW manual version is wrong and it will be
fixed; proper description for GIC is located in "Registers for Module
Standby Mode" table
- haven't added watchdog domain (was missing in v1, too, by mistake) as
the watchdog restart handler will fail w/o patch [1]; with this pm domain
support the watchdog will fail to probe; not sure what is the best
option until [1] will be integrated
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]
drivers/clk/renesas/r9a08g045-cpg.c | 41 +++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index c3e6da2de197..b068733b145f 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -240,6 +240,43 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
};
+static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
+ /* Keep always-on domain on the first position for proper domains registration. */
+ DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON,
+ DEF_REG_CONF(0, 0),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("gic", R9A08G045_PD_GIC,
+ DEF_REG_CONF(CPG_BUS_ACPU_MSTOP, BIT(3)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("ia55", R9A08G045_PD_IA55,
+ DEF_REG_CONF(CPG_BUS_PERI_CPU_MSTOP, BIT(13)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("dmac", R9A08G045_PD_DMAC,
+ DEF_REG_CONF(CPG_BUS_REG1_MSTOP, GENMASK(3, 0)),
+ RZG2L_PD_F_ALWAYS_ON),
+ DEF_PD("wdt0", R9A08G045_PD_WDT0,
+ DEF_REG_CONF(CPG_BUS_REG0_MSTOP, BIT(0)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi0", R9A08G045_PD_SDHI0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(0)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi1", R9A08G045_PD_SDHI1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(1)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("sdhi2", R9A08G045_PD_SDHI2,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(11)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth0", R9A08G045_PD_ETHER0,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(2)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("eth1", R9A08G045_PD_ETHER1,
+ DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
+ RZG2L_PD_F_NONE),
+ DEF_PD("scif0", R9A08G045_PD_SCIF0,
+ DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
+ RZG2L_PD_F_NONE),
+};
+
const struct rzg2l_cpg_info r9a08g045_cpg_info = {
/* Core Clocks */
.core_clks = r9a08g045_core_clks,
@@ -260,5 +297,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
.resets = r9a08g045_resets,
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
+ /* Power domains */
+ .pm_domains = r9a08g045_pm_domains,
+ .num_pm_domains = ARRAY_SIZE(r9a08g045_pm_domains),
+
.has_clk_mon_regs = true,
};
--
2.39.2
From: Claudiu Beznea <[email protected]>
Add power domain IDs for RZ/G3S (R9A08G045) SoC.
Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
---
Changes in v4:
- none
Changes in v3:
- collected tags
Changes in v2:
- collected tag
include/dt-bindings/clock/r9a08g045-cpg.h | 70 +++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h
index 410725b778a8..8281e9caf3a9 100644
--- a/include/dt-bindings/clock/r9a08g045-cpg.h
+++ b/include/dt-bindings/clock/r9a08g045-cpg.h
@@ -239,4 +239,74 @@
#define R9A08G045_I3C_PRESETN 92
#define R9A08G045_VBAT_BRESETN 93
+/* Power domain IDs. */
+#define R9A08G045_PD_ALWAYS_ON 0
+#define R9A08G045_PD_GIC 1
+#define R9A08G045_PD_IA55 2
+#define R9A08G045_PD_MHU 3
+#define R9A08G045_PD_CORESIGHT 4
+#define R9A08G045_PD_SYC 5
+#define R9A08G045_PD_DMAC 6
+#define R9A08G045_PD_GTM0 7
+#define R9A08G045_PD_GTM1 8
+#define R9A08G045_PD_GTM2 9
+#define R9A08G045_PD_GTM3 10
+#define R9A08G045_PD_GTM4 11
+#define R9A08G045_PD_GTM5 12
+#define R9A08G045_PD_GTM6 13
+#define R9A08G045_PD_GTM7 14
+#define R9A08G045_PD_MTU 15
+#define R9A08G045_PD_POE3 16
+#define R9A08G045_PD_GPT 17
+#define R9A08G045_PD_POEGA 18
+#define R9A08G045_PD_POEGB 19
+#define R9A08G045_PD_POEGC 20
+#define R9A08G045_PD_POEGD 21
+#define R9A08G045_PD_WDT0 22
+#define R9A08G045_PD_XSPI 23
+#define R9A08G045_PD_SDHI0 24
+#define R9A08G045_PD_SDHI1 25
+#define R9A08G045_PD_SDHI2 26
+#define R9A08G045_PD_SSI0 27
+#define R9A08G045_PD_SSI1 28
+#define R9A08G045_PD_SSI2 29
+#define R9A08G045_PD_SSI3 30
+#define R9A08G045_PD_SRC 31
+#define R9A08G045_PD_USB0 32
+#define R9A08G045_PD_USB1 33
+#define R9A08G045_PD_USB_PHY 34
+#define R9A08G045_PD_ETHER0 35
+#define R9A08G045_PD_ETHER1 36
+#define R9A08G045_PD_I2C0 37
+#define R9A08G045_PD_I2C1 38
+#define R9A08G045_PD_I2C2 39
+#define R9A08G045_PD_I2C3 40
+#define R9A08G045_PD_SCIF0 41
+#define R9A08G045_PD_SCIF1 42
+#define R9A08G045_PD_SCIF2 43
+#define R9A08G045_PD_SCIF3 44
+#define R9A08G045_PD_SCIF4 45
+#define R9A08G045_PD_SCIF5 46
+#define R9A08G045_PD_SCI0 47
+#define R9A08G045_PD_SCI1 48
+#define R9A08G045_PD_IRDA 49
+#define R9A08G045_PD_RSPI0 50
+#define R9A08G045_PD_RSPI1 51
+#define R9A08G045_PD_RSPI2 52
+#define R9A08G045_PD_RSPI3 53
+#define R9A08G045_PD_RSPI4 54
+#define R9A08G045_PD_CANFD 55
+#define R9A08G045_PD_ADC 56
+#define R9A08G045_PD_TSU 57
+#define R9A08G045_PD_OCTA 58
+#define R9A08G045_PD_PDM 59
+#define R9A08G045_PD_PCI 60
+#define R9A08G045_PD_SPDIF 61
+#define R9A08G045_PD_I3C 62
+#define R9A08G045_PD_VBAT 63
+
+#define R9A08G045_PD_DDR 64
+#define R9A08G045_PD_TZCDDR 65
+#define R9A08G045_PD_OTFDE_DDR 66
+
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
--
2.39.2
On Mon, Apr 22, 2024 at 12:54 PM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra
> power when clocks are disabled by activating module standby. This is done
> through MSTOP-specific registers that are part of CPG. Each individual
> module has one or more bits associated with one MSTOP register (see table
> "Registers for Module Standby Mode" from HW manuals). Hardware manual
> associates modules' clocks with one or more MSTOP bits. There are 3
> mappings available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW
> manuals):
>
> case 1: N clocks mapped to N MSTOP bits (with N={0, ..., X})
> case 2: N clocks mapped to 1 MSTOP bit (with N={0, ..., X})
> case 3: N clocks mapped to M MSTOP bits (with N={0, ..., X}, M={0, .., Y})
>
> Case 3 has been currently identified on RZ/V2L for the VCPL4 module.
>
> To cover all three cases, the individual platform drivers will provide to
> clock driver MSTOP register offset and associated bits in this register
> as a bitmask and the clock driver will apply this bitmask to proper
> MSTOP register.
>
> The MSTOP was implemented through power domains. Platform-specific clock
> drivers will register an array of type
> struct rzg2l_cpg_pm_domain_init_data, which will be used to instantiate
> properly the power domains.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
> ---
>
> Changes in v2:
s/v2/v4/
> - dropped the pwrdn functionality until it is better understanded;
> at the same time kept the code ready for pwrd being added by keeping
> struct rzg2l_cpg_pm_domain_conf, DEF_REG_CONF(); please let me know
> if you prefer otherwise
> - @Geert, @Ulf: I dropped your previous Rb tags due to dropping pwrdn
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Apr 22, 2024 at 12:54 PM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Instantiate power domains for the currently enabled IPs of R9A08G045 SoC.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
> ---
>
> Changes in v4:
> - dropped DEF_REG_CONF() specific to pwrdn functionality
> - dropped ddr, tzcddr, oftde_ddr domains as these were there due to
> the pwrdn functionality
> - added wdt0 domain; this will not impact currently integrated
> watchdog support
> - @Geert: I dropped your previous Rb tag due to the changes in v4
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Ulf,
On Mon, Apr 22, 2024 at 12:54 PM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Series adds support for power domains on rzg2l driver.
>
> RZ/G2L kind of devices support a functionality called MSTOP (module
> stop/standby). According to hardware manual the module could be switch
> to standby after its clocks are disabled. The reverse order of operation
> should be done when enabling a module (get the module out of standby,
> enable its clocks etc).
>
> In [1] the MSTOP settings were implemented by adding code in driver
> to attach the MSTOP state to the IP clocks. But it has been proposed
> to implement it as power domain. The result is this series.
>
> The DT bindings were updated with power domain IDs (plain integers
> that matches the DT with driver data structures). The current DT
> bindings were updated with module IDs for the modules listed in tables
> with name "Registers for Module Standby Mode" (see HW manual) exception
> being RZ/G3S where, due to the power down functionality, the DDR,
> TZCDDR, OTFDE_DDR were also added.
>
> Domain IDs were added to all SoC specific bindings.
>
> Thank you,
> Claudiu Beznea
>
> Changes in v4:
> - dropped the pwrdn functionality until it is better understanded
> - dropped patch "clk: renesas: rzg2l-cpg: Add suspend/resume
> support for power domains" from v3; this will be replaced
> by propertly calling device_set_wakup_path() in serial console
> driver
> - instantiated the watchdog domain in r8a08g045 clock driver; this
> allow applying r9a08g045 clock patch w/o affecting watchdog and later,
> after all good with watchdog patches series at [2], only patch
> "arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>"
> will need to be applied
Are you happy with this series? I would like to queue patches 1-7 in
renesas-clk for v6.10 (i.e. this week).
Thank you!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68korg
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Wed, 24 Apr 2024 at 16:34, Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Ulf,
>
> On Mon, Apr 22, 2024 at 12:54 PM Claudiu <[email protected]> wrote:
> > From: Claudiu Beznea <[email protected]>
> >
> > Series adds support for power domains on rzg2l driver.
> >
> > RZ/G2L kind of devices support a functionality called MSTOP (module
> > stop/standby). According to hardware manual the module could be switch
> > to standby after its clocks are disabled. The reverse order of operation
> > should be done when enabling a module (get the module out of standby,
> > enable its clocks etc).
> >
> > In [1] the MSTOP settings were implemented by adding code in driver
> > to attach the MSTOP state to the IP clocks. But it has been proposed
> > to implement it as power domain. The result is this series.
> >
> > The DT bindings were updated with power domain IDs (plain integers
> > that matches the DT with driver data structures). The current DT
> > bindings were updated with module IDs for the modules listed in tables
> > with name "Registers for Module Standby Mode" (see HW manual) exception
> > being RZ/G3S where, due to the power down functionality, the DDR,
> > TZCDDR, OTFDE_DDR were also added.
> >
> > Domain IDs were added to all SoC specific bindings.
> >
> > Thank you,
> > Claudiu Beznea
> >
> > Changes in v4:
> > - dropped the pwrdn functionality until it is better understanded
> > - dropped patch "clk: renesas: rzg2l-cpg: Add suspend/resume
> > support for power domains" from v3; this will be replaced
> > by propertly calling device_set_wakup_path() in serial console
> > driver
> > - instantiated the watchdog domain in r8a08g045 clock driver; this
> > allow applying r9a08g045 clock patch w/o affecting watchdog and later,
> > after all good with watchdog patches series at [2], only patch
> > "arm64: dts: renesas: r9a08g045: Update #power-domain-cells = <1>"
> > will need to be applied
>
> Are you happy with this series? I would like to queue patches 1-7 in
> renesas-clk for v6.10 (i.e. this week).
Yes, the series looks good to me! For the series, feel free to add:
Reviewed-by: Ulf Hansson <[email protected]>
Kind regards
Uffe