The Google Tensor gs101 SoC embeds a DWC3 USB 3.1 DRD controller.
This patch series enables the existing dwc3-exynos glue layer to work on
this SoC.
Signed-off-by: André Draszik <[email protected]>
---
André Draszik (2):
dt-bindings: usb: samsung,exynos-dwc3: add gs101 compatible
usb: dwc3: exynos: add support for Google Tensor gs101
.../devicetree/bindings/usb/samsung,exynos-dwc3.yaml | 18 ++++++++++++++++++
drivers/usb/dwc3/dwc3-exynos.c | 9 +++++++++
2 files changed, 27 insertions(+)
---
base-commit: a59668a9397e7245b26e9be85d23f242ff757ae8
change-id: 20240423-usb-dwc3-gs101-1f5864f06ca9
Best regards,
--
André Draszik <[email protected]>
The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
controller and can reuse the existing Exynos glue. Update the dt schema
to include the google,gs101-dwusb3 compatible for it.
Signed-off-by: André Draszik <[email protected]>
---
.../devicetree/bindings/usb/samsung,exynos-dwc3.yaml | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
index 1ade99e85ba8..2b3430cebe99 100644
--- a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml
@@ -12,6 +12,7 @@ maintainers:
properties:
compatible:
enum:
+ - google,gs101-dwusb3
- samsung,exynos5250-dwusb3
- samsung,exynos5433-dwusb3
- samsung,exynos7-dwusb3
@@ -55,6 +56,23 @@ required:
- vdd33-supply
allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-dwusb3
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ maxItems: 4
+ clock-names:
+ items:
+ - const: bus_early
+ - const: susp_clk
+ - const: link_aclk
+ - const: link_pclk
+
- if:
properties:
compatible:
--
2.44.0.769.g3c40516874-goog
The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
controller and can reuse the existing Exynos glue. Add the
google,gs101-dwusb3 compatible and associated driver data. Four clocks
are required for USB for this SoC:
* bus clock
* suspend clock
* Link interface AXI clock
* Link interface APB clock
Signed-off-by: André Draszik <[email protected]>
---
drivers/usb/dwc3/dwc3-exynos.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 3427522a7c6a..9a6e988d165a 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -169,6 +169,12 @@ static const struct dwc3_exynos_driverdata exynos850_drvdata = {
.suspend_clk_idx = -1,
};
+static const struct dwc3_exynos_driverdata gs101_drvdata = {
+ .clk_names = { "bus_early", "susp_clk", "link_aclk", "link_pclk" },
+ .num_clks = 4,
+ .suspend_clk_idx = 1,
+};
+
static const struct of_device_id exynos_dwc3_match[] = {
{
.compatible = "samsung,exynos5250-dwusb3",
@@ -182,6 +188,9 @@ static const struct of_device_id exynos_dwc3_match[] = {
}, {
.compatible = "samsung,exynos850-dwusb3",
.data = &exynos850_drvdata,
+ }, {
+ .compatible = "google,gs101-dwusb3",
+ .data = &gs101_drvdata,
}, {
}
};
--
2.44.0.769.g3c40516874-goog
On Tue, 23 Apr 2024 21:19:45 +0100, Andr? Draszik wrote:
> The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
> controller and can reuse the existing Exynos glue. Update the dt schema
> to include the google,gs101-dwusb3 compatible for it.
>
> Signed-off-by: Andr? Draszik <[email protected]>
> ---
> .../devicetree/bindings/usb/samsung,exynos-dwc3.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
Reviewed-by: Rob Herring (Arm) <[email protected]>
On Tue, Apr 23, 2024, André Draszik wrote:
> The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
> controller and can reuse the existing Exynos glue. Add the
> google,gs101-dwusb3 compatible and associated driver data. Four clocks
> are required for USB for this SoC:
> * bus clock
> * suspend clock
> * Link interface AXI clock
> * Link interface APB clock
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> drivers/usb/dwc3/dwc3-exynos.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
> index 3427522a7c6a..9a6e988d165a 100644
> --- a/drivers/usb/dwc3/dwc3-exynos.c
> +++ b/drivers/usb/dwc3/dwc3-exynos.c
> @@ -169,6 +169,12 @@ static const struct dwc3_exynos_driverdata exynos850_drvdata = {
> .suspend_clk_idx = -1,
> };
>
> +static const struct dwc3_exynos_driverdata gs101_drvdata = {
> + .clk_names = { "bus_early", "susp_clk", "link_aclk", "link_pclk" },
> + .num_clks = 4,
> + .suspend_clk_idx = 1,
> +};
> +
> static const struct of_device_id exynos_dwc3_match[] = {
> {
> .compatible = "samsung,exynos5250-dwusb3",
> @@ -182,6 +188,9 @@ static const struct of_device_id exynos_dwc3_match[] = {
> }, {
> .compatible = "samsung,exynos850-dwusb3",
> .data = &exynos850_drvdata,
> + }, {
> + .compatible = "google,gs101-dwusb3",
> + .data = &gs101_drvdata,
> }, {
> }
> };
>
> --
> 2.44.0.769.g3c40516874-goog
>
Acked-by: Thinh Nguyen <[email protected]>
Thanks,
Thinh
On 23/04/2024 22:19, André Draszik wrote:
> The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
> controller and can reuse the existing Exynos glue. Add the
> google,gs101-dwusb3 compatible and associated driver data. Four clocks
> are required for USB for this SoC:
> * bus clock
> * suspend clock
> * Link interface AXI clock
> * Link interface APB clock
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> drivers/usb/dwc3/dwc3-exynos.c | 9 +++++++++
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 23/04/2024 22:19, André Draszik wrote:
> The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
> controller and can reuse the existing Exynos glue. Update the dt schema
> to include the google,gs101-dwusb3 compatible for it.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> .../devicetree/bindings/usb/samsung,exynos-dwc3.yaml | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Tue, 23 Apr 2024 at 21:19, André Draszik <[email protected]> wrote:
>
> The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
> controller and can reuse the existing Exynos glue. Add the
> google,gs101-dwusb3 compatible and associated driver data. Four clocks
> are required for USB for this SoC:
> * bus clock
> * suspend clock
> * Link interface AXI clock
> * Link interface APB clock
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Peter Griffin <[email protected]>
regards,
Peter
On Tue, 23 Apr 2024 at 21:19, André Draszik <[email protected]> wrote:
>
> The Exynos-based Google Tensor gs101 SoC has a DWC3 compatible USB
> controller and can reuse the existing Exynos glue. Update the dt schema
> to include the google,gs101-dwusb3 compatible for it.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Peter Griffin <[email protected]>
regards,
Peter