Hello all,
this patchset adds support for i.Core MX93 EDIMM 2.0 Starter Kit,
a SoM + Evaluation Board combination from Engicam.
The number of patch has diminished to 3, for I dropped the
patch introducing a change in nxp,pca9450 binding which has
been already submitted in regulator tree.
(Dropped also regulator tree maintainers as recipients for
they aren't anymore involved in this patchset)
This patchset introduces just basic functionality for board.
Thanks in advance,
fabio
---
v7 ---> v8:
- fixed tag name in commit message
v6 ---> v7:
- removed max-frequency property in wifi node
- removed pinctrl-{1,2} in usdhc3 node
v5 ---> v6:
- added property in lpuart5 node
- removed unused sai1 node
v4 ---> v5:
- done some property reorder, indentation fixes,
node rename, drop/add new-lines
- fixed line wrap in 2nd patch commit log
- added Reviewed-by tag
v3 ---> v4:
- drop wl_reg_on regulator in favor of
mmc-pwrseq-simple
v2 ---> v3:
- fixed dtschema warnings
- added Acked/Reviewed-by tags
- removed regulator-always-on on
bt_reg_on
- fixed clock rate assignment on
sgtl5000 node
- added wdog_b-warm-reset; property in pmic
- fixed indentation issue
v1 ---> v2:
- dropped patch updating nxp,pca9450 binding
- fixed indentation issue
- fixed missing space issue
- improved naming of regulator nodes
- removed unneeded include
- fixed email recipients
Fabio Aiuto (3):
dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
arm64: dts: imx93: add Engicam i.Core MX93 SoM
arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
.../devicetree/bindings/arm/fsl.yaml | 7 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-icore-mx93-edimm2.dts | 321 ++++++++++++++++++
.../boot/dts/freescale/imx93-icore-mx93.dtsi | 269 +++++++++++++++
4 files changed, 598 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
--
2.34.1
i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
EDIMM 2.0 Starter Kit is an EDIMM 2.0 Form Factor Capacitive
Evaluation Board by Engicam.
i.Core MX93 needs to be mounted on top of EDIMM 2.0 Starter Kit
to get the full i.Core MX93 EDIMM 2.0 Starter Kit board.
Add bindings for this board.
Cc: Matteo Lisi <[email protected]>
Cc: Mirko Ardinghi <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Fabio Aiuto <[email protected]>
---
v7 ---> v8:
- fixed tag in commit message
v3 ---> v7:
- no changes
v2 ---> v3:
- added {Reviewed,Acked}-by tags
v1 ---> v2:
- no changes
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0027201e19f8..b497a01c7418 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1265,6 +1265,13 @@ properties:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- const: fsl,imx93
+ - description: Engicam i.Core MX93 based Boards
+ items:
+ - enum:
+ - engicam,icore-mx93-edimm2 # i.MX93 Engicam i.Core MX93 EDIMM 2.0 Starter Kit
+ - const: engicam,icore-mx93 # i.MX93 Engicam i.Core MX93 Som
+ - const: fsl,imx93
+
- description: i.MXRT1050 based Boards
items:
- enum:
--
2.34.1
i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
Main features:
CPU: NXP i.MX 93
MEMORY: Up to 2GB LPDDR4
NETWORKING: 2x Gb Ethernet
USB: USB OTG 2.0, USB HOST 2.0
STORAGE: eMMC starting from 4GB
PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO
The i.Core MX93 needs to be mounted on top of
Engicam baseboards to work.
Add devicetree include file.
Cc: Matteo Lisi <[email protected]>
Cc: Mirko Ardinghi <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Fabio Aiuto <[email protected]>
---
v5 ---> v8:
- no changes
v4 ---> v5:
- added Reviewed-by tag
- fixed line wrapping in commit msg
- fixed indentation, dropped newlines, reordered property
v3 ---> v4:
- no changes
v2 ---> v3:
- added wdog_b-warm-reset property in pmic
v1 ---> v2:
- remove unneeded include
.../boot/dts/freescale/imx93-icore-mx93.dtsi | 269 ++++++++++++++++++
1 file changed, 269 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
new file mode 100644
index 000000000000..9c97b620ccfc
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2024 Engicam s.r.l.
+ */
+
+/dts-v1/;
+
+#include "imx93.dtsi"
+
+/ {
+ model = "Engicam i.Core MX93 SoM";
+ compatible = "engicam,icore-mx93", "fsl,imx93";
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy2>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy2: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+ };
+};
+
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ nxp,wdog_b-warm-reset;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {/*SD Card*/
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ no-1-8-v;
+ max-frequency = <25000000>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e
+ MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e
+ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e
+ MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e
+ MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e
+ MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e
+ MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e
+ MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e
+ MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e
+ MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e
+ MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e
+ MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e
+ MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e
+ MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e
+ >;
+ };
+
+ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
+ MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
+ MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
+ MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
+ MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
+ MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
+ MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
+ MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
+ MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
+ MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
+ MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
+ MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
+ MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
+ MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e
+ MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e
+ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e
+ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e
+ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e
+ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
+ >;
+ };
+};
--
2.34.1
i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which needs to be
mounted on top of Engicam baseboards.
Add support for EDIMM 2.0 Starter Kit hosting i.Core MX93.
Starter Kit main features:
2x LVDS interfaces
HDMI output
Audio out
Mic in
Micro SD card slot
USB 3.0 A port
3x USB 2.0 A port
Gb Ethernet
2x CAN bus, 3x UART interfaces
SIM card slot
M.2 KEY_B slot
Cc: Matteo Lisi <[email protected]>
Cc: Mirko Ardinghi <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Signed-off-by: Fabio Aiuto <[email protected]>
---
v7 ---> v8:
- no changes
v6 ---> v7:
- removed max-frequency property in wifi node
- removed pinctrl-{1,2} in usdhc3 node
v5 ---> v6:
- added property in lpuart5 node
- removed unused sai1 node
- move Cc tag to Reviewed-by tag
v4 ---> v5:
- done some property reorder, indentation fixes, node rename,
drop/add new lines
- added Reviewed-by tag
v3 ---> v4:
- drop wl_reg_on regulator in favor of mmc-pwrseq-simple
- add Cc tag
v2 ---> v3:
- fixed dtschema warnings
- removed regulator-always-on on bt_reg_on
- fixed clock rate assignment on sgtl5000 node
- fixed indentation issue
v1 ---> v2:
- fixed indentation issue
- fixed missing space issue
- improved naming of regulator nodes
- removed unneeded include
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx93-icore-mx93-edimm2.dts | 321 ++++++++++++++++++
2 files changed, 322 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 045250d0a040..d26c0a458a44 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
new file mode 100644
index 000000000000..c22d71cdf7cb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 NXP
+ * Copyright 2024 Engicam s.r.l.
+ */
+
+/dts-v1/;
+
+#include "imx93-icore-mx93.dtsi"
+
+/ {
+ model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
+ compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
+ "fsl,imx93";
+
+ aliases {
+ rtc1 = &bbnsm_rtc;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ bt_reg_on: regulator-btregon {
+ compatible = "regulator-gpio";
+ regulator-name = "BT_REG_ON";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3300000>;
+ states = <3300000 0x1>, <100000 0x0>;
+ gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_1v8_sgtl: regulator-1v8-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8_sgtl";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_avdd_sgtl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_3v3_sgtl: regulator-3v3-sgtl {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_sgtl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0 0x80000000 0 0x40000000>;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+
+ rsc_table: rsc-table@2021f000 {
+ reg = <0 0x2021f000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@a4020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0xa4020000 0 0x100000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@a4000000 {
+ reg = <0 0xa4000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@a4008000 {
+ reg = <0 0xa4008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@a4000000 {
+ reg = <0 0xa4010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@a4018000 {
+ reg = <0 0xa4018000 0 0x8000>;
+ no-map;
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "imx93-sgtl5000";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ /*simple-audio-card,mclk-fs = <1>;*/
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ clocks = <&clk IMX93_CLK_SAI3_IPG>;
+ };
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3_pwrseq>;
+ reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cm33 {
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu1 0 1>,
+ <&mu1 1 1>,
+ <&mu1 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ status = "okay";
+};
+
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
+ status = "okay";
+};
+
+&lpi2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-1 = <&pinctrl_lpi2c1>;
+ status = "okay";
+
+ sgtl5000: audio-codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&clk IMX93_CLK_SAI3_GATE>;
+ VDDA-supply = <®_3v3_avdd_sgtl>;
+ VDDIO-supply = <®_3v3_sgtl>;
+ VDDD-supply = <®_1v8_sgtl>;
+ status = "okay";
+ };
+
+ pcf8523: rtc@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&lpuart5 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&lpuart8 { /* RS232 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ status = "okay";
+};
+
+&micfil {
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clk IMX93_CLK_PDM>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <196608000>;
+ status = "okay";
+};
+
+&mu1 {
+ status = "okay";
+};
+
+&mu2 {
+ status = "okay";
+};
+
+&sai3 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&clk IMX93_CLK_SAI3>;
+ assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+ assigned-clock-rates = <24576000>;
+ fsl,sai-mclk-direction-output;
+ status = "okay";
+};
+
+&usdhc3 { /* WiFi */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+
+ brcmf: bcrmf@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ };
+};
+
+&wdog3 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_bluetooth: bluetoothgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e /* BT_REG_ON */
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX93_PAD_PDM_CLK__CAN1_TX 0x139e
+ MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
+ MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
+ MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
+ MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
+ MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
+ MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
+ MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
+ MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
+ MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
+ MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
+ MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
+ MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
+ MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
+ MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
+ >;
+ };
+
+ pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp {
+ fsl,pins = <
+ MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* WL_REG_ON */
+ >;
+ };
+};
--
2.34.1
Hello all,
any news here?
kr,
fabio
Il Mon, Apr 29, 2024 at 11:31:13AM +0200, Fabio Aiuto ha scritto:
> Hello all,
>
> this patchset adds support for i.Core MX93 EDIMM 2.0 Starter Kit,
> a SoM + Evaluation Board combination from Engicam.
>
> The number of patch has diminished to 3, for I dropped the
> patch introducing a change in nxp,pca9450 binding which has
> been already submitted in regulator tree.
>
> (Dropped also regulator tree maintainers as recipients for
> they aren't anymore involved in this patchset)
>
> This patchset introduces just basic functionality for board.
>
> Thanks in advance,
>
> fabio
> ---
> v7 ---> v8:
> - fixed tag name in commit message
> v6 ---> v7:
> - removed max-frequency property in wifi node
> - removed pinctrl-{1,2} in usdhc3 node
> v5 ---> v6:
> - added property in lpuart5 node
> - removed unused sai1 node
> v4 ---> v5:
> - done some property reorder, indentation fixes,
> node rename, drop/add new-lines
> - fixed line wrap in 2nd patch commit log
> - added Reviewed-by tag
> v3 ---> v4:
> - drop wl_reg_on regulator in favor of
> mmc-pwrseq-simple
> v2 ---> v3:
> - fixed dtschema warnings
> - added Acked/Reviewed-by tags
> - removed regulator-always-on on
> bt_reg_on
> - fixed clock rate assignment on
> sgtl5000 node
> - added wdog_b-warm-reset; property in pmic
> - fixed indentation issue
> v1 ---> v2:
> - dropped patch updating nxp,pca9450 binding
> - fixed indentation issue
> - fixed missing space issue
> - improved naming of regulator nodes
> - removed unneeded include
> - fixed email recipients
>
> Fabio Aiuto (3):
> dt-bindings: arm: fsl: add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
> arm64: dts: imx93: add Engicam i.Core MX93 SoM
> arm64: dts: imx93: Add Engicam i.Core MX93 EDIMM 2.0 Starter Kit
>
> .../devicetree/bindings/arm/fsl.yaml | 7 +
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx93-icore-mx93-edimm2.dts | 321 ++++++++++++++++++
> .../boot/dts/freescale/imx93-icore-mx93.dtsi | 269 +++++++++++++++
> 4 files changed, 598 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
>
> --
> 2.34.1
>
On Mon, Apr 29, 2024 at 11:31:15AM +0200, Fabio Aiuto wrote:
> i.Core MX93 is a NXP i.MX93 based EDIMM SoM by Engicam.
>
> Main features:
>
> CPU: NXP i.MX 93
> MEMORY: Up to 2GB LPDDR4
> NETWORKING: 2x Gb Ethernet
> USB: USB OTG 2.0, USB HOST 2.0
> STORAGE: eMMC starting from 4GB
> PERIPHERALS: UART, I2C, SPI, CAN, SDIO, GPIO
>
> The i.Core MX93 needs to be mounted on top of
> Engicam baseboards to work.
>
> Add devicetree include file.
>
> Cc: Matteo Lisi <[email protected]>
> Cc: Mirko Ardinghi <[email protected]>
> Reviewed-by: Peng Fan <[email protected]>
> Signed-off-by: Fabio Aiuto <[email protected]>
> ---
> v5 ---> v8:
> - no changes
> v4 ---> v5:
> - added Reviewed-by tag
> - fixed line wrapping in commit msg
> - fixed indentation, dropped newlines, reordered property
> v3 ---> v4:
> - no changes
> v2 ---> v3:
> - added wdog_b-warm-reset property in pmic
> v1 ---> v2:
> - remove unneeded include
>
> .../boot/dts/freescale/imx93-icore-mx93.dtsi | 269 ++++++++++++++++++
> 1 file changed, 269 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
> new file mode 100644
> index 000000000000..9c97b620ccfc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93.dtsi
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 NXP
> + * Copyright 2024 Engicam s.r.l.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx93.dtsi"
> +
> +/ {
> + model = "Engicam i.Core MX93 SoM";
> + compatible = "engicam,icore-mx93", "fsl,imx93";
> +
> + reg_vref_1v8: regulator-adc-vref {
> + compatible = "regulator-fixed";
> + regulator-name = "vref_1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +};
> +
> +&adc1 {
> + vref-supply = <®_vref_1v8>;
> + status = "okay";
> +};
> +
> +&eqos {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_eqos>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy1>;
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@7 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy2>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy2: ethernet-phy@7 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> + };
> +};
> +
> +&lpi2c2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <400000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_lpi2c2>;
> + pinctrl-1 = <&pinctrl_lpi2c2>;
Why do you have two identical pinctrl state for default and sleep?
> + status = "okay";
> +
> + pmic@25 {
> + compatible = "nxp,pca9451a";
> + reg = <0x25>;
> + interrupt-parent = <&gpio2>;
> + interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
> + nxp,wdog_b-warm-reset;
> +
> + regulators {
> + buck1: BUCK1 {
> + regulator-name = "BUCK1";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + buck2: BUCK2 {
> + regulator-name = "BUCK2";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <2187500>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <3125>;
> + };
> +
> + buck4: BUCK4{
> + regulator-name = "BUCK4";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck5: BUCK5{
> + regulator-name = "BUCK5";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck6: BUCK6 {
> + regulator-name = "BUCK6";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo1: LDO1 {
> + regulator-name = "LDO1";
> + regulator-min-microvolt = <1600000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo2: LDO2 {
> + regulator-name = "LDO2";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1150000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo3: LDO3 {
> + regulator-name = "LDO3";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo4: LDO4 {
> + regulator-name = "LDO4";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo5: LDO5 {
> + regulator-name = "LDO5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1>;
> + pinctrl-2 = <&pinctrl_usdhc1>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&usdhc2 {/*SD Card*/
Nit: &usdhc2 { /* SD Card */
Shawn
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + no-1-8-v;
> + max-frequency = <25000000>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_eqos: eqosgrp {
> + fsl,pins = <
> + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x53e
> + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x53e
> + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x53e
> + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x53e
> + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x53e
> + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x53e
> + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x53e
> + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x53e
> + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x53e
> + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x53e
> + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x53e
> + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x53e
> + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x53e
> + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x53e
> + >;
> + };
> +
> + pinctrl_fec: fecgrp {
> + fsl,pins = <
> + MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
> + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
> + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
> + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
> + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
> + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
> + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
> + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
> + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
> + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
> + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
> + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
> + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe
> + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
> + >;
> + };
> +
> + pinctrl_lpi2c2: lpi2c2grp {
> + fsl,pins = <
> + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
> + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX93_PAD_SD2_CLK__USDHC2_CLK 0x170e
> + MX93_PAD_SD2_CMD__USDHC2_CMD 0x130e
> + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x130e
> + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x130e
> + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x130e
> + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x130e
> + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> + fsl,pins = <
> + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
> + >;
> + };
> +};
> --
> 2.34.1
>
On Mon, Apr 29, 2024 at 11:31:16AM +0200, Fabio Aiuto wrote:
> i.Core MX93 is a NXP i.MX93 based SoM by Enigcam which needs to be
> mounted on top of Engicam baseboards.
>
> Add support for EDIMM 2.0 Starter Kit hosting i.Core MX93.
>
> Starter Kit main features:
>
> 2x LVDS interfaces
> HDMI output
> Audio out
> Mic in
> Micro SD card slot
> USB 3.0 A port
> 3x USB 2.0 A port
> Gb Ethernet
> 2x CAN bus, 3x UART interfaces
> SIM card slot
> M.2 KEY_B slot
>
> Cc: Matteo Lisi <[email protected]>
> Cc: Mirko Ardinghi <[email protected]>
> Reviewed-by: Peng Fan <[email protected]>
> Reviewed-by: Michael Trimarchi <[email protected]>
> Signed-off-by: Fabio Aiuto <[email protected]>
> ---
> v7 ---> v8:
> - no changes
> v6 ---> v7:
> - removed max-frequency property in wifi node
> - removed pinctrl-{1,2} in usdhc3 node
> v5 ---> v6:
> - added property in lpuart5 node
> - removed unused sai1 node
> - move Cc tag to Reviewed-by tag
> v4 ---> v5:
> - done some property reorder, indentation fixes, node rename,
> drop/add new lines
> - added Reviewed-by tag
> v3 ---> v4:
> - drop wl_reg_on regulator in favor of mmc-pwrseq-simple
> - add Cc tag
> v2 ---> v3:
> - fixed dtschema warnings
> - removed regulator-always-on on bt_reg_on
> - fixed clock rate assignment on sgtl5000 node
> - fixed indentation issue
> v1 ---> v2:
> - fixed indentation issue
> - fixed missing space issue
> - improved naming of regulator nodes
> - removed unneeded include
>
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../dts/freescale/imx93-icore-mx93-edimm2.dts | 321 ++++++++++++++++++
> 2 files changed, 322 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 045250d0a040..d26c0a458a44 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -226,6 +226,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx93-icore-mx93-edimm2.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> new file mode 100644
> index 000000000000..c22d71cdf7cb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx93-icore-mx93-edimm2.dts
> @@ -0,0 +1,321 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2022 NXP
> + * Copyright 2024 Engicam s.r.l.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx93-icore-mx93.dtsi"
> +
> +/ {
> + model = "Engicam i.Core MX93 - EDIMM 2 Starterkit";
> + compatible = "engicam,icore-mx93-edimm2", "engicam,icore-mx93",
> + "fsl,imx93";
> +
> + aliases {
> + rtc1 = &bbnsm_rtc;
> + };
> +
> + chosen {
> + stdout-path = &lpuart1;
> + };
> +
> + bt_reg_on: regulator-btregon {
> + compatible = "regulator-gpio";
> + regulator-name = "BT_REG_ON";
> + regulator-min-microvolt = <100000>;
> + regulator-max-microvolt = <3300000>;
> + states = <3300000 0x1>, <100000 0x0>;
> + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + };
> +
> + reg_1v8_sgtl: regulator-1v8-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "1v8_sgtl";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + reg_3v3_avdd_sgtl: regulator-3v3-avdd-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_avdd_sgtl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_3v3_sgtl: regulator-3v3-sgtl {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_sgtl";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + linux,cma {
> + compatible = "shared-dma-pool";
> + reusable;
> + alloc-ranges = <0 0x80000000 0 0x40000000>;
> + size = <0 0x10000000>;
> + linux,cma-default;
> + };
> +
> + rsc_table: rsc-table@2021f000 {
> + reg = <0 0x2021f000 0 0x1000>;
> + no-map;
> + };
> +
> + vdevbuffer: vdevbuffer@a4020000 {
> + compatible = "shared-dma-pool";
> + reg = <0 0xa4020000 0 0x100000>;
> + no-map;
> + };
> +
> + vdev0vring0: vdev0vring0@a4000000 {
> + reg = <0 0xa4000000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev0vring1: vdev0vring1@a4008000 {
> + reg = <0 0xa4008000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev1vring0: vdev1vring0@a4000000 {
> + reg = <0 0xa4010000 0 0x8000>;
> + no-map;
> + };
> +
> + vdev1vring1: vdev1vring1@a4018000 {
> + reg = <0 0xa4018000 0 0x8000>;
> + no-map;
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "imx93-sgtl5000";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&dailink_master>;
> + simple-audio-card,frame-master = <&dailink_master>;
> + /*simple-audio-card,mclk-fs = <1>;*/
Could you just drop the line?
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai3>;
> + };
> +
> + dailink_master: simple-audio-card,codec {
> + sound-dai = <&sgtl5000>;
> + clocks = <&clk IMX93_CLK_SAI3_IPG>;
> + };
> + };
> +
> + usdhc3_pwrseq: usdhc3-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>;
> + reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&cm33 {
> + mbox-names = "tx", "rx", "rxdb";
> + mboxes = <&mu1 0 1>,
> + <&mu1 1 1>,
> + <&mu1 3 1>;
> + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> + status = "okay";
> +};
> +
> +&flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> + status = "okay";
> +};
> +
> +&flexcan2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + fsl,stop-mode = <&aonmix_ns_gpr 0x10 4>;
> + status = "okay";
> +};
> +
> +&lpi2c1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-frequency = <400000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&pinctrl_lpi2c1>;
> + pinctrl-1 = <&pinctrl_lpi2c1>;
Same comment as patch 2/3.
Shawn
> + status = "okay";
> +
> + sgtl5000: audio-codec@a {
> + compatible = "fsl,sgtl5000";
> + reg = <0x0a>;
> + #sound-dai-cells = <0>;
> + clocks = <&clk IMX93_CLK_SAI3_GATE>;
> + VDDA-supply = <®_3v3_avdd_sgtl>;
> + VDDIO-supply = <®_3v3_sgtl>;
> + VDDD-supply = <®_1v8_sgtl>;
> + status = "okay";
> + };
> +
> + pcf8523: rtc@68 {
> + compatible = "nxp,pcf8523";
> + reg = <0x68>;
> + };
> +};
> +
> +&lpuart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&lpuart5 { /* RS485 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&lpuart8 { /* RS232 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart8>;
> + status = "okay";
> +};
> +
> +&micfil {
> + #sound-dai-cells = <0>;
> + assigned-clocks = <&clk IMX93_CLK_PDM>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <196608000>;
> + status = "okay";
> +};
> +
> +&mu1 {
> + status = "okay";
> +};
> +
> +&mu2 {
> + status = "okay";
> +};
> +
> +&sai3 {
> + #sound-dai-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai3>;
> + assigned-clocks = <&clk IMX93_CLK_SAI3>;
> + assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> + assigned-clock-rates = <24576000>;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&usdhc3 { /* WiFi */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc3>;
> + mmc-pwrseq = <&usdhc3_pwrseq>;
> + bus-width = <4>;
> + no-1-8-v;
> + non-removable;
> + status = "okay";
> +
> + brcmf: bcrmf@1 {
> + compatible = "brcm,bcm4329-fmac";
> + reg = <1>;
> + };
> +};
> +
> +&wdog3 {
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_bluetooth: bluetoothgrp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO19__GPIO2_IO19 0x31e /* BT_REG_ON */
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX93_PAD_PDM_CLK__CAN1_TX 0x139e
> + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
> + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
> + >;
> + };
> +
> + pinctrl_lpi2c1: lpi2c1grp {
> + fsl,pins = <
> + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
> + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
> + >;
> + };
> +
> + pinctrl_sai3: sai3grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
> + MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
> + MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
> + MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x31e
> + MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
> + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO01__LPUART5_RX 0x31e
> + MX93_PAD_GPIO_IO00__LPUART5_TX 0x31e
> + MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
> + >;
> + };
> +
> + pinctrl_uart8: uart8grp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
> + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
> + >;
> + };
> +
> + pinctrl_usdhc3: usdhc3grp {
> + fsl,pins = <
> + MX93_PAD_SD3_CLK__USDHC3_CLK 0x17fe
> + MX93_PAD_SD3_CMD__USDHC3_CMD 0x13fe
> + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
> + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
> + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
> + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
> + >;
> + };
> +
> + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp {
> + fsl,pins = <
> + MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e /* WL_REG_ON */
> + >;
> + };
> +};
> --
> 2.34.1
>