J784S4 has one USB sub system.
This series adds and enables support for USB 3.0 for
J784S4 EVM.
Matt Ranostay (2):
arm64: dts: ti: k3-j784s4-main: Add support for USB
arm64: dts: ti: k3-j784s4-evm: Enable USB3 support
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 39 ++++++++++++++++++++
2 files changed, 80 insertions(+)
base-commit: f68868ba718e30594165879cc3020607165b0761
--
2.17.1
From: Matt Ranostay <[email protected]>
Add support for the USB 3.0 controller
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 6a4554c6c9c1..51cdd0b56a6f 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -75,6 +75,13 @@
<J784S4_SERDES4_LANE2_EDP_LANE2>,
<J784S4_SERDES4_LANE3_EDP_LANE3>;
};
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "reg-mux";
+ reg = <0x4000 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */
+ };
};
gic500: interrupt-controller@1800000 {
@@ -568,6 +575,38 @@
status = "disabled";
};
+ usbss0: cdns-usb@4104000 {
+ bootph-all;
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x4104000 0x00 0x100>;
+ dma-coherent;
+ power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 398 21>, <&k3_clks 398 2>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled"; /* Needs lane config */
+
+ usb0: usb@6000000 {
+ bootph-all;
+ compatible = "cdns,usb3";
+ reg = <0x00 0x6000000 0x00 0x10000>,
+ <0x00 0x6010000 0x00 0x10000>,
+ <0x00 0x6020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ };
+ };
+
main_i2c0: i2c@2000000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x02000000 0x00 0x100>;
--
2.17.1
From: Matt Ranostay <[email protected]>
The board uses SERDES0 Lane 3 for USB3 IP. So update the
SerDes lane info for USB. Add the pin mux data and
enable USB3 support.
Signed-off-by: Matt Ranostay <[email protected]>
Signed-off-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index d511b25d62e3..bee73dab803d 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -336,6 +336,13 @@
J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
>;
};
+
+ main_usbss0_pins_default: main-usbss0-pins-default {
+ bootph-all;
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
+ >;
+ };
};
&wkup_pmx2 {
@@ -1041,6 +1048,40 @@
<&k3_clks 218 22>;
};
+&serdes0 {
+ status = "okay";
+
+ serdes0_usb_link: phy@3 {
+ reg = <3>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 4>;
+ };
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&usb_serdes_mux {
+ idle-states = <0>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+ status = "okay";
+ pinctrl-0 = <&main_usbss0_pins_default>;
+ pinctrl-names = "default";
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&serdes_wiz4 {
status = "okay";
};
--
2.17.1
On Thu, 02 May 2024 11:06:13 +0530, Ravi Gunasekaran wrote:
> J784S4 has one USB sub system.
> This series adds and enables support for USB 3.0 for
> J784S4 EVM.
>
> Matt Ranostay (2):
> arm64: dts: ti: k3-j784s4-main: Add support for USB
> arm64: dts: ti: k3-j784s4-evm: Enable USB3 support
>
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 39 ++++++++++++++++++++
> 2 files changed, 80 insertions(+)
>
>
> base-commit: f68868ba718e30594165879cc3020607165b0761
> --
> 2.17.1
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y ti/k3-j784s4-evm.dtb' for [email protected]:
arch/arm64/boot/dts/ti/k3-j784s4-evm.dtb: pinctrl@11c000: 'main-usbss0-pins-default' does not match any of the regexes: '-pins(-[0-9]+)?$|-pin$', 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
On 02/05/2024 08:36, Ravi Gunasekaran wrote:
> From: Matt Ranostay <[email protected]>
>
> The board uses SERDES0 Lane 3 for USB3 IP. So update the
> SerDes lane info for USB. Add the pin mux data and
> enable USB3 support.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> Signed-off-by: Ravi Gunasekaran <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index d511b25d62e3..bee73dab803d 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -336,6 +336,13 @@
> J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
> >;
> };
> +
> + main_usbss0_pins_default: main-usbss0-pins-default {
Should be main-usbss0-default-pins
This should fix the checkpatch warning.
> + bootph-all;
> + pinctrl-single,pins = <
> + J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */
> + >;
> + };
> };
>
> &wkup_pmx2 {
> @@ -1041,6 +1048,40 @@
> <&k3_clks 218 22>;
> };
>
> +&serdes0 {
> + status = "okay";
> +
> + serdes0_usb_link: phy@3 {
> + reg = <3>;
> + cdns,num-lanes = <1>;
> + #phy-cells = <0>;
> + cdns,phy-type = <PHY_TYPE_USB3>;
> + resets = <&serdes_wiz0 4>;
> + };
> +};
> +
> +&serdes_wiz0 {
> + status = "okay";
> +};
> +
> +&usb_serdes_mux {
> + idle-states = <0>; /* USB0 to SERDES lane 3 */
> +};
> +
> +&usbss0 {
> + status = "okay";
> + pinctrl-0 = <&main_usbss0_pins_default>;
> + pinctrl-names = "default";
> + ti,vbus-divider;
> +};
> +
> +&usb0 {
> + dr_mode = "otg";
> + maximum-speed = "super-speed";
> + phys = <&serdes0_usb_link>;
> + phy-names = "cdns3,usb3-phy";
> +};
> +
> &serdes_wiz4 {
> status = "okay";
> };
--
cheers,
-roger
Roger, Rob
On 5/3/24 12:18 PM, Roger Quadros wrote:
>
>
> On 02/05/2024 08:36, Ravi Gunasekaran wrote:
>> From: Matt Ranostay <[email protected]>
>>
>> The board uses SERDES0 Lane 3 for USB3 IP. So update the
>> SerDes lane info for USB. Add the pin mux data and
>> enable USB3 support.
>>
>> Signed-off-by: Matt Ranostay <[email protected]>
>> Signed-off-by: Ravi Gunasekaran <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 41 ++++++++++++++++++++++++
>> 1 file changed, 41 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> index d511b25d62e3..bee73dab803d 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> @@ -336,6 +336,13 @@
>> J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
>> >;
>> };
>> +
>> + main_usbss0_pins_default: main-usbss0-pins-default {
>
> Should be main-usbss0-default-pins
>
> This should fix the checkpatch warning.
>
I will fix and send a v2
[...]
--
Regards,
Ravi