Hi,
this simple series improve handling of RAC and CBR address and try to
upstream these simple patch we have in OpenWrt for a while.
The first patch fix a straight kernel panic where some Bootloader might
enable RAC but misconfigure the CBR address. The current logic only
check if RAC is enabled but doesn't verify if the CBR address is usable.
The DMA sync function cause a kernel panic for invalid write. (as CBR is
0 or something like 0xa)
The second is preparation for making the CBR address configurable in DT.
Since this address doesn't change, we can cache it and reference it with
a local variable instead of calling the register to access the value.
The 4th patch make it configurable with 2 DT property, one to actually
set the reg and the other to force set it.
The first property is used when CBR is set to 0. The second property is
to force it if the Bootloader sets it to something wrong.
If the CBR value is not 0 and is not forced with the second property a
WARN is printed and the DT value is ignored.
The 5th patch enable RAC on BMIPS4350 and the 5th patch is a micro
optimization to skip more call on DMA sync to save as resource as
possible on low spec devices. (since DMA sync is called many times for
the Ethernet Switch and we can reference the bool instead of checking
the CPU type everytime)
These has been tested on BCM6358 (HG556a) and BCM6368 (VH4032N) and
reported correct functionality.
Changes v2:
- Prefix brcm vendor in the added property
- Drop last patch (cpu switch from DMA sync)
- Validate CBR addr from DT to be outside DRAM
- Reduce indentation in DT CBR check
- Reduce delta and use local variable for CBR where possible
- Fix and improve typo and spelling mistake
- Use 0xf instead of 0xa for BCM6358 RAC enable
Christian Marangi (4):
mips: bmips: BCM6358: make sure CBR is correctly set
mips: bmips: rework and cache CBR addr handling
dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property
mips: bmips: setup: make CBR address configurable
Daniel González Cabanelas (1):
mips: bmips: enable RAC on BMIPS4350
.../devicetree/bindings/mips/brcm/soc.yaml | 32 ++++++++++++++
arch/mips/bmips/dma.c | 2 +-
arch/mips/bmips/setup.c | 42 ++++++++++++++++++-
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 21 +++++++++-
5 files changed, 93 insertions(+), 5 deletions(-)
--
2.43.0
It was discovered that some device have CBR address set to 0 causing
kernel panic when arch_sync_dma_for_cpu_all is called.
This was notice in situation where the system is booted from TP1 and
BMIPS_GET_CBR() returns 0 instead of a valid address and
!!(read_c0_brcm_cmt_local() & (1 << 31)); not failing.
The current check whether RAC flush should be disabled or not are not
enough hence lets check if CBR is a valid address or not.
Fixes: ab327f8acdf8 ("mips: bmips: BCM6358: disable RAC flush for TP1")
Signed-off-by: Christian Marangi <[email protected]>
---
arch/mips/bmips/setup.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index ec180ab92eaa..66a8ba19c287 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -110,7 +110,8 @@ static void bcm6358_quirks(void)
* RAC flush causes kernel panics on BCM6358 when booting from TP1
* because the bootloader is not initializing it properly.
*/
- bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
+ bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
+ !!BMIPS_GET_CBR();
}
static void bcm6368_quirks(void)
--
2.43.0
Rework the handling of the CBR address and cache it. This address
doesn't change and can be cached instead of reading the register every
time.
This is in preparation of permitting to tweak the CBR address in DT with
broken SoC or bootloader.
Signed-off-by: Christian Marangi <[email protected]>
---
arch/mips/bmips/dma.c | 2 +-
arch/mips/bmips/setup.c | 6 +++++-
arch/mips/include/asm/bmips.h | 1 +
arch/mips/kernel/smp-bmips.c | 4 ++--
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/mips/bmips/dma.c b/arch/mips/bmips/dma.c
index 3779e7855bd7..2bc9c0d4402f 100644
--- a/arch/mips/bmips/dma.c
+++ b/arch/mips/bmips/dma.c
@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable;
void arch_sync_dma_for_cpu_all(void)
{
- void __iomem *cbr = BMIPS_GET_CBR();
+ void __iomem *cbr = bmips_cbr_addr;
u32 cfg;
if (boot_cpu_type() != CPU_BMIPS3300 &&
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 66a8ba19c287..5e024399222f 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -34,6 +34,8 @@
#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
#define BCM6328_TP1_DISABLED BIT(9)
+/* CBR addr doesn't change and we can cache it */
+void __iomem *bmips_cbr_addr __ro_after_init __read_mostly;
extern bool bmips_rac_flush_disable;
static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
@@ -111,7 +113,7 @@ static void bcm6358_quirks(void)
* because the bootloader is not initializing it properly.
*/
bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
- !!BMIPS_GET_CBR();
+ !!bmips_cbr_addr;
}
static void bcm6368_quirks(void)
@@ -144,6 +146,8 @@ static void __init bmips_init_cfe(void)
void __init prom_init(void)
{
+ /* Cache CBR addr before CPU/DMA setup */
+ bmips_cbr_addr = BMIPS_GET_CBR();
bmips_init_cfe();
bmips_cpu_setup();
register_bmips_smp_ops();
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index 581a6a3c66e4..3a1cdfddb987 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -81,6 +81,7 @@ extern char bmips_smp_movevec[];
extern char bmips_smp_int_vec[];
extern char bmips_smp_int_vec_end[];
+extern void __iomem *bmips_cbr_addr;
extern int bmips_smp_enabled;
extern int bmips_cpu_offset;
extern cpumask_t bmips_booted_mask;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index b3dbf9ecb0d6..a4f84667a901 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -518,7 +518,7 @@ static void bmips_set_reset_vec(int cpu, u32 val)
info.val = val;
bmips_set_reset_vec_remote(&info);
} else {
- void __iomem *cbr = BMIPS_GET_CBR();
+ void __iomem *cbr = bmips_cbr_addr;
if (cpu == 0)
__raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
@@ -591,7 +591,7 @@ asmlinkage void __weak plat_wired_tlb_setup(void)
void bmips_cpu_setup(void)
{
- void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
+ void __iomem __maybe_unused *cbr = bmips_cbr_addr;
u32 __maybe_unused cfg;
switch (current_cpu_type()) {
--
2.43.0
Add support to provide CBR address from DT to handle broken
SoC/Bootloader that doesn't correctly init it. This permits to use the
RAC flush even in these condition.
To provide a CBR address from DT, the property "brcm,bmips-cbr-reg"
needs to be set in the "cpus" node. On DT init, this property presence
will be checked and will set the bmips_cbr_addr value accordingly. Also
bmips_rac_flush_disable will be set to false as RAC flush can be
correctly supported.
The CBR address from DT will be applied only if the CBR address from the
registers is 0, if the CBR address from the registers is not 0 and
is not equal to the one set in DT (if provided) a WARN is printed.
Also the DT CBR address is validated on being outside DRAM window.
To ALWAYS overwrite the CBR address the additional property
"brcm,bmips-broken-cbr-reg" needs to be set.
Signed-off-by: Christian Marangi <[email protected]>
---
arch/mips/bmips/setup.c | 37 +++++++++++++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 5e024399222f..bf27b29c7a14 100644
--- a/arch/mips/bmips/setup.c
+++ b/arch/mips/bmips/setup.c
@@ -34,7 +34,11 @@
#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
#define BCM6328_TP1_DISABLED BIT(9)
-/* CBR addr doesn't change and we can cache it */
+/*
+ * CBR addr doesn't change and we can cache it.
+ * For broken SoC/Bootloader CBR addr might also be provided via DT
+ * with "brcm,bmips-cbr-reg" in the "cpus" node.
+ */
void __iomem *bmips_cbr_addr __ro_after_init __read_mostly;
extern bool bmips_rac_flush_disable;
@@ -207,13 +211,42 @@ void __init plat_mem_setup(void)
void __init device_tree_init(void)
{
struct device_node *np;
+ u32 addr;
unflatten_and_copy_device_tree();
/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
np = of_find_node_by_name(NULL, "cpus");
- if (np && of_get_available_child_count(np) <= 1)
+ if (!np)
+ return;
+
+ if (of_get_available_child_count(np) <= 1)
bmips_smp_enabled = 0;
+
+ /* Check if DT provide a CBR address */
+ if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
+ goto exit;
+
+ /* Make sure CBR address is outside DRAM window */
+ if (addr >= (u32)memblock_start_of_DRAM() &&
+ addr < (u32)memblock_end_of_DRAM()) {
+ WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
+ addr);
+ goto exit;
+ }
+
+ if (bmips_cbr_addr && addr != (u32)bmips_cbr_addr &&
+ !of_property_read_bool(np, "brcm,bmips-broken-cbr-reg")) {
+ WARN(1, "register CBR %x differ from DT CBR %x. Ignoring DT CBR.\n",
+ (u32)bmips_cbr_addr, addr);
+ goto exit;
+ }
+
+ bmips_cbr_addr = (void __iomem *)addr;
+ /* Since CBR is provided by DT, enable RAC flush */
+ bmips_rac_flush_disable = false;
+
+exit:
of_node_put(np);
}
--
2.43.0
Document brcm,bmips-cbr-reg and brcm,bmips-broken-cbr-reg property.
Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
if called from TP1. The CBR address is always the same on the SoC
hence it can be provided in DT to handle broken case where bootloader
doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
Usage of this property is to give an address also in these broken
configuration/bootloader.
If the SoC/Bootloader ALWAYS provide a broken CBR address the property
"brcm,bmips-broken-cbr-reg" can be used to ignore any value already set
in the registers for CBR address.
Signed-off-by: Christian Marangi <[email protected]>
---
.../devicetree/bindings/mips/brcm/soc.yaml | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
index 975945ca2888..29af8f0db785 100644
--- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
+++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
@@ -55,6 +55,21 @@ properties:
under the "cpus" node.
$ref: /schemas/types.yaml#/definitions/uint32
+ brcm,bmips-broken-cbr-reg:
+ description: Declare that the Bootloader init a broken
+ CBR address in the registers and the one provided from
+ DT should always be used.
+ type: boolean
+
+ brcm,bmips-cbr-reg:
+ description: Reference address of the CBR.
+ Some SoC suffer from a BUG where read_c0_brcm_cbr() might
+ return 0 if called from TP1. The CBR address is always the
+ same on the SoC hence it can be provided in DT to handle
+ broken case where bootloader doesn't initialise it or SMP
+ where read_c0_brcm_cbr() returns 0 from TP1.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
patternProperties:
"^cpu@[0-9]$":
type: object
@@ -64,6 +79,23 @@ properties:
required:
- mips-hpt-frequency
+dependencies:
+ brcm,bmips-broken-cbr-reg: [ brcm,bmips-cbr-reg ]
+
+if:
+ properties:
+ compatible:
+ contains:
+ anyOf:
+ - const: brcm,bcm6358
+ - const: brcm,bcm6368
+
+then:
+ properties:
+ cpus:
+ required:
+ - brcm,bmips-cbr-reg
+
additionalProperties: true
examples:
--
2.43.0
From: Daniel González Cabanelas <[email protected]>
The data RAC is left disabled by the bootloader in some SoCs, at least in
the core it boots from.
Enabling this feature increases the performance up to +30% depending on the
task.
Signed-off-by: Daniel González Cabanelas <[email protected]>
Signed-off-by: Álvaro Fernández Rojas <[email protected]>
[ rework code and reduce code duplication ]
Signed-off-by: Christian Marangi <[email protected]>
---
arch/mips/kernel/smp-bmips.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index a4f84667a901..0f93963c08e4 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -620,6 +620,23 @@ void bmips_cpu_setup(void)
__raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
break;
+ case CPU_BMIPS4350:
+ u32 rac_addr = BMIPS_RAC_CONFIG_1;
+
+ if (!(read_c0_brcm_cmt_local() & (1 << 31)))
+ rac_addr = BMIPS_RAC_CONFIG;
+
+ /* Enable data RAC */
+ cfg = __raw_readl(bmips_cbr_addr + rac_addr);
+ __raw_writel(cfg | 0xf, bmips_cbr_addr + rac_addr);
+ __raw_readl(bmips_cbr_addr + rac_addr);
+
+ /* Flush stale data out of the readahead cache */
+ cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
+ __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG);
+ __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
+ break;
+
case CPU_BMIPS4380:
/* CBG workaround for early BMIPS4380 CPUs */
switch (read_c0_prid()) {
--
2.43.0
On 5/3/24 14:20, Christian Marangi wrote:
> It was discovered that some device have CBR address set to 0 causing
> kernel panic when arch_sync_dma_for_cpu_all is called.
>
> This was notice in situation where the system is booted from TP1 and
> BMIPS_GET_CBR() returns 0 instead of a valid address and
> !!(read_c0_brcm_cmt_local() & (1 << 31)); not failing.
>
> The current check whether RAC flush should be disabled or not are not
> enough hence lets check if CBR is a valid address or not.
>
> Fixes: ab327f8acdf8 ("mips: bmips: BCM6358: disable RAC flush for TP1")
> Signed-off-by: Christian Marangi <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On 5/3/24 14:20, Christian Marangi wrote:
> Rework the handling of the CBR address and cache it. This address
> doesn't change and can be cached instead of reading the register every
> time.
>
> This is in preparation of permitting to tweak the CBR address in DT with
> broken SoC or bootloader.
>
> Signed-off-by: Christian Marangi <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On 5/3/24 14:21, Christian Marangi wrote:
> From: Daniel González Cabanelas <[email protected]>
>
> The data RAC is left disabled by the bootloader in some SoCs, at least in
> the core it boots from.
> Enabling this feature increases the performance up to +30% depending on the
> task.
>
> Signed-off-by: Daniel González Cabanelas <[email protected]>
> Signed-off-by: Álvaro Fernández Rojas <[email protected]>
> [ rework code and reduce code duplication ]
> Signed-off-by: Christian Marangi <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
--
Florian
On Fri, 03 May 2024 23:20:59 +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg and brcm,bmips-broken-cbr-reg property.
>
> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
> if called from TP1. The CBR address is always the same on the SoC
> hence it can be provided in DT to handle broken case where bootloader
> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
>
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
>
> If the SoC/Bootloader ALWAYS provide a broken CBR address the property
> "brcm,bmips-broken-cbr-reg" can be used to ignore any value already set
> in the registers for CBR address.
>
> Signed-off-by: Christian Marangi <[email protected]>
> ---
> .../devicetree/bindings/mips/brcm/soc.yaml | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
/Documentation/devicetree/bindings/mips/brcm/soc.yaml:83:37: [warning] too few spaces after comma (commas)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On Fri, May 03, 2024 at 11:20:59PM +0200, Christian Marangi wrote:
> Document brcm,bmips-cbr-reg and brcm,bmips-broken-cbr-reg property.
>
> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
> if called from TP1. The CBR address is always the same on the SoC
> hence it can be provided in DT to handle broken case where bootloader
> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
>
> Usage of this property is to give an address also in these broken
> configuration/bootloader.
>
> If the SoC/Bootloader ALWAYS provide a broken CBR address the property
> "brcm,bmips-broken-cbr-reg" can be used to ignore any value already set
> in the registers for CBR address.
Why can't these be implied from an SoC specific compatible?
It's not a great design where you have to update the DT which should be
provided from the bootloader in order to work-around bootloader
issues...
>
> Signed-off-by: Christian Marangi <[email protected]>
> ---
> .../devicetree/bindings/mips/brcm/soc.yaml | 32 +++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> index 975945ca2888..29af8f0db785 100644
> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
> @@ -55,6 +55,21 @@ properties:
> under the "cpus" node.
> $ref: /schemas/types.yaml#/definitions/uint32
>
> + brcm,bmips-broken-cbr-reg:
> + description: Declare that the Bootloader init a broken
> + CBR address in the registers and the one provided from
> + DT should always be used.
Why wouldn't brcm,bmips-cbr-reg being present indicate to use it?
> + type: boolean
> +
> + brcm,bmips-cbr-reg:
> + description: Reference address of the CBR.
> + Some SoC suffer from a BUG where read_c0_brcm_cbr() might
> + return 0 if called from TP1. The CBR address is always the
> + same on the SoC hence it can be provided in DT to handle
> + broken case where bootloader doesn't initialise it or SMP
> + where read_c0_brcm_cbr() returns 0 from TP1.
> + $ref: /schemas/types.yaml#/definitions/uint32
CBR is never defined anywhere in this patch.
> +
> patternProperties:
> "^cpu@[0-9]$":
> type: object
> @@ -64,6 +79,23 @@ properties:
> required:
> - mips-hpt-frequency
>
> +dependencies:
> + brcm,bmips-broken-cbr-reg: [ brcm,bmips-cbr-reg ]
The inline syntax (i.e. []) means you need quotes for commas.
This has no effect because you are applying it to the root node. Needs
to be a the same level as the properties.
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + anyOf:
> + - const: brcm,bcm6358
> + - const: brcm,bcm6368
Replace anyOf+const with enum.
> +
> +then:
> + properties:
> + cpus:
> + required:
> + - brcm,bmips-cbr-reg
> +
> additionalProperties: true
>
> examples:
> --
> 2.43.0
>
On 5/7/24 06:07, Rob Herring wrote:
> On Fri, May 03, 2024 at 11:20:59PM +0200, Christian Marangi wrote:
>> Document brcm,bmips-cbr-reg and brcm,bmips-broken-cbr-reg property.
>>
>> Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0
>> if called from TP1. The CBR address is always the same on the SoC
>> hence it can be provided in DT to handle broken case where bootloader
>> doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1.
>>
>> Usage of this property is to give an address also in these broken
>> configuration/bootloader.
>>
>> If the SoC/Bootloader ALWAYS provide a broken CBR address the property
>> "brcm,bmips-broken-cbr-reg" can be used to ignore any value already set
>> in the registers for CBR address.
>
> Why can't these be implied from an SoC specific compatible?
Because some SoCs with the same compatible have it right, and some
wrong, courtesy of how the various OEMs implemented it.
>
> It's not a great design where you have to update the DT which should be
> provided from the bootloader in order to work-around bootloader
> issues...
The bootloader was designed without DT in mind, and while CFE had a
callback mechanism to query environment variables and whatnot, those
devices were stripped out of it.
>
>>
>> Signed-off-by: Christian Marangi <[email protected]>
>> ---
>> .../devicetree/bindings/mips/brcm/soc.yaml | 32 +++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>> index 975945ca2888..29af8f0db785 100644
>> --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>> +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml
>> @@ -55,6 +55,21 @@ properties:
>> under the "cpus" node.
>> $ref: /schemas/types.yaml#/definitions/uint32
>>
>> + brcm,bmips-broken-cbr-reg:
>> + description: Declare that the Bootloader init a broken
>> + CBR address in the registers and the one provided from
>> + DT should always be used.
>
> Why wouldn't brcm,bmips-cbr-reg being present indicate to use it?
>
>> + type: boolean
>> +
>> + brcm,bmips-cbr-reg:
>> + description: Reference address of the CBR.
>> + Some SoC suffer from a BUG where read_c0_brcm_cbr() might
>> + return 0 if called from TP1. The CBR address is always the
>> + same on the SoC hence it can be provided in DT to handle
>> + broken case where bootloader doesn't initialise it or SMP
>> + where read_c0_brcm_cbr() returns 0 from TP1.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>
> CBR is never defined anywhere in this patch.
The very presence of "brcm,bmips-cbr-reg" property should be enough to
indicate to the kernel that it should the value provided, rather than
the value returned from read_c0_brcm_cbr(). That is, I don't think there
is a need to indicate to the kernel that the CBR value is broken, if you
provide a new value that is enough of a clue to tel you that.
--
Florian
Hi Christian,
kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.9-rc7 next-20240508]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/mips-bmips-BCM6358-make-sure-CBR-is-correctly-set/20240504-052513
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240503212139.5811-3-ansuelsmth%40gmail.com
patch subject: [PATCH v2 2/5] mips: bmips: rework and cache CBR addr handling
config: mips-bcm63xx_defconfig (https://download.01.org/0day-ci/archive/20240509/[email protected]/config)
compiler: mips-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240509/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
mips-linux-ld: arch/mips/kernel/smp-bmips.o: in function `bmips_ebase_setup':
>> smp-bmips.c:(.text+0x114): undefined reference to `bmips_cbr_addr'
>> mips-linux-ld: smp-bmips.c:(.text+0x118): undefined reference to `bmips_cbr_addr'
mips-linux-ld: arch/mips/kernel/smp-bmips.o: in function `bmips_cpu_setup':
smp-bmips.c:(.text+0x1a4): undefined reference to `bmips_cbr_addr'
mips-linux-ld: smp-bmips.c:(.text+0x1b4): undefined reference to `bmips_cbr_addr'
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
On Thu, May 09, 2024 at 07:13:16AM +0800, kernel test robot wrote:
> Hi Christian,
>
> kernel test robot noticed the following build errors:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on linus/master v6.9-rc7 next-20240508]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Christian-Marangi/mips-bmips-BCM6358-make-sure-CBR-is-correctly-set/20240504-052513
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> patch link: https://lore.kernel.org/r/20240503212139.5811-3-ansuelsmth%40gmail.com
> patch subject: [PATCH v2 2/5] mips: bmips: rework and cache CBR addr handling
> config: mips-bcm63xx_defconfig (https://download.01.org/0day-ci/archive/20240509/[email protected]/config)
> compiler: mips-linux-gcc (GCC) 13.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240509/[email protected]/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <[email protected]>
> | Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
>
> All errors (new ones prefixed by >>):
>
> mips-linux-ld: arch/mips/kernel/smp-bmips.o: in function `bmips_ebase_setup':
> >> smp-bmips.c:(.text+0x114): undefined reference to `bmips_cbr_addr'
> >> mips-linux-ld: smp-bmips.c:(.text+0x118): undefined reference to `bmips_cbr_addr'
> mips-linux-ld: arch/mips/kernel/smp-bmips.o: in function `bmips_cpu_setup':
> smp-bmips.c:(.text+0x1a4): undefined reference to `bmips_cbr_addr'
> mips-linux-ld: smp-bmips.c:(.text+0x1b4): undefined reference to `bmips_cbr_addr'
>
This is caused by legacy brcm47xx and brcm63xx target. v4 will have this
fixed (and I will drop the ACK since I moved code around)
--
Ansuel