This is a request for comments on high level design of Tegra config settings.
NVIDIA Tegra SoCs have various I/O controllers and these controllers require
specific register configurations based on:
- Functional mode (eg. speed)
- Interface properties (eg. signal timings)
- Manufacturing characteristics (eg. process/package)
- Thermal characteristics
- Board characteristics
Some of the configurations can be provided by device specific standard DT
properties like speed of interface in I2C, rising/falling timing etc. However,
there are more device specific configurations required to tune the interface
based on execution mode or other runtime parameters. All such configurations are
defined as 'config' settings of the device. This configures a device to operate
with the optimal settings for a particular mode to improve performance,
stability or reduce power.
Add the mechanism to provide the configuration parameters from the device tree
called "config setting via Device Tree".
This series capture the device tree details, common parser code for Tegra SOC
and the usage in I/O controllers I2C, SPI.
Patch 01: Documentation about the device tree binding for common config framework.
Patch 02: Common parser of the device tree config setting node for Tegra SoC.
Patch 03: Device tree binding documentation for config setting.
Patch 04: Device tree binding documentation for the I2C config setting.
Patch 05: Avoid config settings child node to be treated as I2C device.
Patch 06: Move clock initialization code into new methods
Patch 07: Using config settings in Tegra I2C driver for interface timing registers.
Patch 08: Add Tegra234 I2C config settings in DT.
Patch 09: Device tree binding documentation for the SDHCI config setting.
Patch 10: Using config settings in Tegra SDHCI driver for tuning iteration.
Patch 11: Add Tegra234 SDHCI config settings in DT.
Known Issues:
- DTC warning for config 'missing or empty reg property for I2C nodes'
Krishna Yarlagadda (11):
Documentation: Introduce config settings framework
soc: tegra: Add config setting framework
soc: tegra: config settings binding document
i2c: dt-bindings: configuration settings
i2c: core: Avoid config node enumeration
i2c: tegra: split clock initialization code
i2c: tegra: config settings for interface timings
arm64: tegra: I2C interface timings
sdhci: dt-bindings: configuration settings
mmc: host: tegra: config settings for timing
arm64: tegra: SDHCI timing settings
.../bindings/i2c/nvidia,tegra20-i2c.yaml | 104 ++++
.../misc/nvidia,tegra-config-settings.yaml | 50 ++
.../bindings/mmc/nvidia,tegra20-sdhci.yaml | 36 ++
Documentation/misc-devices/tegra-cfg.rst | 128 +++++
MAINTAINERS | 10 +
arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 478 ++++++++++++++++++
.../dts/nvidia/tegra234-p3701-0000-cfg.dtsi | 123 +++++
.../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 +
drivers/i2c/busses/i2c-tegra.c | 257 ++++++++--
drivers/i2c/i2c-core-of.c | 3 +
drivers/mmc/host/sdhci-tegra.c | 84 +++
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/tegra-cfg.c | 147 ++++++
include/soc/tegra/tegra-cfg.h | 87 ++++
14 files changed, 1456 insertions(+), 53 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml
create mode 100644 Documentation/misc-devices/tegra-cfg.rst
create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-cfg.dtsi
create mode 100644 drivers/soc/tegra/tegra-cfg.c
create mode 100644 include/soc/tegra/tegra-cfg.h
--
2.43.2
Add new methods for setting clock parameters and setting
clock divisor.
Signed-off-by: Krishna Yarlagadda <[email protected]>
---
drivers/i2c/busses/i2c-tegra.c | 127 ++++++++++++++++++++-------------
1 file changed, 77 insertions(+), 50 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 85b31edc558d..b3dc2603db35 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -604,12 +604,83 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
return 0;
}
+static void tegra_i2c_set_clk_params(struct tegra_i2c_dev *i2c_dev)
+{
+ u32 val, clk_divisor, tsu_thd, tlow, thigh, non_hs_mode;
+
+ switch (i2c_dev->timings.bus_freq_hz) {
+ case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
+ default:
+ tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
+ thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
+
+ if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
+ else
+ non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
+ break;
+
+ case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
+ tlow = i2c_dev->hw->tlow_std_mode;
+ thigh = i2c_dev->hw->thigh_std_mode;
+ tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
+ non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
+ break;
+ }
+
+ /* make sure clock divisor programmed correctly */
+ clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
+ i2c_dev->hw->clk_divisor_hs_mode) |
+ FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
+ i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
+
+ if (i2c_dev->hw->has_interface_timing_reg) {
+ val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
+ FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
+ i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
+ }
+
+ /*
+ * Configure setup and hold times only when tsu_thd is non-zero.
+ * Otherwise, preserve the chip default values.
+ */
+ if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
+ i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
+}
+
+static int tegra_i2c_set_div_clk(struct tegra_i2c_dev *i2c_dev)
+{
+ u32 clk_multiplier, tlow, thigh, non_hs_mode;
+ u32 timing, clk_divisor;
+ int err;
+
+ timing = i2c_readl(i2c_dev, I2C_INTERFACE_TIMING_0);
+
+ tlow = FIELD_GET(I2C_INTERFACE_TIMING_TLOW, timing);
+ thigh = FIELD_GET(I2C_INTERFACE_TIMING_THIGH, timing);
+
+ clk_divisor = i2c_readl(i2c_dev, I2C_CLK_DIVISOR);
+
+ non_hs_mode = FIELD_GET(I2C_CLK_DIVISOR_STD_FAST_MODE, clk_divisor);
+
+ clk_multiplier = (thigh + tlow + 2) * (non_hs_mode + 1);
+
+ err = clk_set_rate(i2c_dev->div_clk,
+ i2c_dev->timings.bus_freq_hz * clk_multiplier);
+ if (err) {
+ dev_err(i2c_dev->dev, "failed to set div_clk rate: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
{
- u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
+ u32 val;
+ int err;
acpi_handle handle = ACPI_HANDLE(i2c_dev->dev);
- struct i2c_timings *t = &i2c_dev->timings;
- int err;
/*
* The reset shouldn't ever fail in practice. The failure will be a
@@ -641,54 +712,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (IS_VI(i2c_dev))
tegra_i2c_vi_init(i2c_dev);
- switch (t->bus_freq_hz) {
- case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
- default:
- tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
- thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
- tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
-
- if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
- non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
- else
- non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
- break;
-
- case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
- tlow = i2c_dev->hw->tlow_std_mode;
- thigh = i2c_dev->hw->thigh_std_mode;
- tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
- non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
- break;
- }
-
- /* make sure clock divisor programmed correctly */
- clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
- i2c_dev->hw->clk_divisor_hs_mode) |
- FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
- i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
-
- if (i2c_dev->hw->has_interface_timing_reg) {
- val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
- FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
- i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
- }
-
- /*
- * Configure setup and hold times only when tsu_thd is non-zero.
- * Otherwise, preserve the chip default values.
- */
- if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
- i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
-
- clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
-
- err = clk_set_rate(i2c_dev->div_clk,
- t->bus_freq_hz * clk_multiplier);
- if (err) {
- dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
+ tegra_i2c_set_clk_params(i2c_dev);
+ err = tegra_i2c_set_div_clk(i2c_dev);
+ if (err)
return err;
- }
if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
--
2.43.2
Use config settings framework to initialize Tegra I2C interface
timing registers and clock divisor based on I2C speed modes.
Each speed mode uses predefined configuration for interface timing
and clock registers.
Signed-off-by: Akhil R <[email protected]>
Signed-off-by: Laxman Dewangan <[email protected]>
Signed-off-by: Krishna Yarlagadda <[email protected]>
---
drivers/i2c/busses/i2c-tegra.c | 134 +++++++++++++++++++++++++++++++--
1 file changed, 129 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index b3dc2603db35..263fd64e440f 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -28,6 +28,8 @@
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include <soc/tegra/tegra-cfg.h>
+
#define BYTES_PER_FIFO_WORD 4
#define I2C_CNFG 0x000
@@ -108,8 +110,9 @@
#define I2C_MST_CORE_CLKEN_OVR BIT(0)
#define I2C_INTERFACE_TIMING_0 0x094
-#define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
-#define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
+#define I2C_INTERFACE_TIMING_THIGH GENMASK(15, 8)
+#define I2C_INTERFACE_TIMING_TLOW GENMASK(7, 0)
+
#define I2C_INTERFACE_TIMING_1 0x098
#define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
#define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
@@ -117,8 +120,9 @@
#define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
#define I2C_HS_INTERFACE_TIMING_0 0x09c
-#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
-#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
+#define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(15, 8)
+#define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(7, 0)
+
#define I2C_HS_INTERFACE_TIMING_1 0x0a0
#define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
#define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
@@ -226,6 +230,49 @@ struct tegra_i2c_hw_feature {
bool has_interface_timing_reg;
};
+/**
+ * I2C register config fields.
+ */
+static const struct tegra_cfg_field_desc i2c_cfg_fields[] = {
+ TEGRA_CFG_FIELD("nvidia,i2c-clk-divisor-fs-mode",
+ I2C_CLK_DIVISOR, I2C_CLK_DIVISOR_STD_FAST_MODE),
+ TEGRA_CFG_FIELD("nvidia,i2c-clk-divisor-hs-mode",
+ I2C_CLK_DIVISOR, I2C_CLK_DIVISOR_HSMODE),
+ TEGRA_CFG_FIELD("nvidia,i2c-hs-sclk-high-period",
+ I2C_HS_INTERFACE_TIMING_0,
+ I2C_HS_INTERFACE_TIMING_THIGH),
+ TEGRA_CFG_FIELD("nvidia,i2c-hs-sclk-low-period",
+ I2C_HS_INTERFACE_TIMING_0,
+ I2C_HS_INTERFACE_TIMING_TLOW),
+ TEGRA_CFG_FIELD("nvidia,i2c-hs-stop-setup-time",
+ I2C_HS_INTERFACE_TIMING_1,
+ I2C_HS_INTERFACE_TIMING_TSU_STO),
+ TEGRA_CFG_FIELD("nvidia,i2c-hs-start-hold-time",
+ I2C_HS_INTERFACE_TIMING_1,
+ I2C_HS_INTERFACE_TIMING_THD_STA),
+ TEGRA_CFG_FIELD("nvidia,i2c-hs-start-setup-time",
+ I2C_HS_INTERFACE_TIMING_1,
+ I2C_HS_INTERFACE_TIMING_TSU_STA),
+ TEGRA_CFG_FIELD("nvidia,i2c-sclk-high-period",
+ I2C_INTERFACE_TIMING_0, I2C_INTERFACE_TIMING_THIGH),
+ TEGRA_CFG_FIELD("nvidia,i2c-sclk-low-period",
+ I2C_INTERFACE_TIMING_0, I2C_INTERFACE_TIMING_TLOW),
+ TEGRA_CFG_FIELD("nvidia,i2c-bus-free-time",
+ I2C_INTERFACE_TIMING_1, I2C_INTERFACE_TIMING_TBUF),
+ TEGRA_CFG_FIELD("nvidia,i2c-stop-setup-time",
+ I2C_INTERFACE_TIMING_1, I2C_INTERFACE_TIMING_TSU_STO),
+ TEGRA_CFG_FIELD("nvidia,i2c-start-hold-time",
+ I2C_INTERFACE_TIMING_1, I2C_INTERFACE_TIMING_THD_STA),
+ TEGRA_CFG_FIELD("nvidia,i2c-start-setup-time",
+ I2C_INTERFACE_TIMING_1, I2C_INTERFACE_TIMING_TSU_STA),
+};
+
+static struct tegra_cfg_desc i2c_cfg_desc = {
+ .num_regs = 0,
+ .num_fields = ARRAY_SIZE(i2c_cfg_fields),
+ .fields = i2c_cfg_fields,
+};
+
/**
* struct tegra_i2c_dev - per device I2C context
* @dev: device reference for power management
@@ -288,6 +335,8 @@ struct tegra_i2c_dev {
dma_addr_t dma_phys;
void *dma_buf;
+ struct tegra_cfg_list *list;
+
bool multimaster_mode;
bool atomic_mode;
bool dma_mode;
@@ -340,6 +389,16 @@ static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
}
+static void i2c_update(struct tegra_i2c_dev *i2c_dev, u32 mask,
+ u32 val, unsigned int reg)
+{
+ u32 rval;
+
+ rval = i2c_readl(i2c_dev, reg);
+ rval = (rval & ~mask) | val;
+ i2c_writel(i2c_dev, rval, reg);
+}
+
static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
unsigned int reg, unsigned int len)
{
@@ -604,6 +663,48 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
return 0;
}
+static void tegra_i2c_write_cfg_settings(struct tegra_i2c_dev *i2c_dev,
+ const char *name)
+{
+ struct tegra_cfg_reg *regs;
+ struct tegra_cfg *cfg;
+ unsigned int i;
+
+ cfg = tegra_cfg_get_by_name(i2c_dev->dev, i2c_dev->list, name);
+ if (!cfg)
+ return;
+
+ regs = cfg->regs;
+ for (i = 0; i < cfg->num_regs; i++) {
+ i2c_update(i2c_dev, regs[i].mask, regs[i].value,
+ regs[i].offset);
+ }
+}
+
+static void tegra_i2c_config_cfg_settings(struct tegra_i2c_dev *i2c_dev)
+{
+ const char *name;
+
+ switch (i2c_dev->timings.bus_freq_hz) {
+ case I2C_MAX_FAST_MODE_PLUS_FREQ + 1 ... I2C_MAX_HIGH_SPEED_MODE_FREQ:
+ name = "high";
+ break;
+ case I2C_MAX_FAST_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
+ name = "fastplus";
+ break;
+ case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_FREQ:
+ name = "fast";
+ break;
+ case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
+ default:
+ name = "standard";
+ break;
+ }
+
+ tegra_i2c_write_cfg_settings(i2c_dev, "common");
+ tegra_i2c_write_cfg_settings(i2c_dev, name);
+}
+
static void tegra_i2c_set_clk_params(struct tegra_i2c_dev *i2c_dev)
{
u32 val, clk_divisor, tsu_thd, tlow, thigh, non_hs_mode;
@@ -712,7 +813,11 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
if (IS_VI(i2c_dev))
tegra_i2c_vi_init(i2c_dev);
- tegra_i2c_set_clk_params(i2c_dev);
+ if (i2c_dev->list)
+ tegra_i2c_config_cfg_settings(i2c_dev);
+ else
+ tegra_i2c_set_clk_params(i2c_dev);
+
err = tegra_i2c_set_div_clk(i2c_dev);
if (err)
return err;
@@ -1772,6 +1877,8 @@ static int tegra_i2c_probe(struct platform_device *pdev)
struct tegra_i2c_dev *i2c_dev;
struct resource *res;
int err;
+ const struct tegra_cfg_field_desc *fields;
+ unsigned int count = 0, i, j;
i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
if (!i2c_dev)
@@ -1808,6 +1915,23 @@ static int tegra_i2c_probe(struct platform_device *pdev)
if (err)
return err;
+ fields = i2c_cfg_fields;
+
+ for (i = 0; i < i2c_cfg_desc.num_fields; i++) {
+ for (j = 0; j < i; j++)
+ if (fields[i].offset == fields[j].offset)
+ break;
+ if (i == j)
+ count++;
+ }
+ i2c_cfg_desc.num_regs = count;
+
+ i2c_dev->list = tegra_cfg_get(i2c_dev->dev, NULL, &i2c_cfg_desc);
+ if (IS_ERR_OR_NULL(i2c_dev->list)) {
+ dev_dbg(&pdev->dev, "Config setting not available\n");
+ i2c_dev->list = NULL;
+ }
+
tegra_i2c_parse_dt(i2c_dev);
err = tegra_i2c_init_reset(i2c_dev);
--
2.43.2
Set I2C interface timing registers through config settings for
Tegra234 chip and P3701 board.
Signed-off-by: Krishna Yarlagadda <[email protected]>
---
MAINTAINERS | 1 +
arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 446 ++++++++++++++++++
.../dts/nvidia/tegra234-p3701-0000-cfg.dtsi | 123 +++++
.../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 1 +
4 files changed, 571 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-cfg.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index a8c0cfd1d5a6..27ca5bd9203e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21996,6 +21996,7 @@ M: Thierry Reding <[email protected]>
R: Laxman Dewangan <[email protected]>
R: Krishna Yarlagadda <[email protected]>
S: Supported
+F: arch/arm64/boot/dts/nvidia/tegra234*cfg.dtsi
F: Documentation/devicetree/bindings/misc/nvidia,tegra-config-settings.yaml
F: Documentation/misc-devices/tegra-cfg.rst
F: drivers/soc/tegra/tegra-cfg.c
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
new file mode 100644
index 000000000000..832538e45797
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+/ {
+ bus@0 {
+ i2c@3160000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@3180000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@3190000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@31b0000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@31c0000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@31e0000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@c240000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ i2c@c250000 {
+ config {
+
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+
+ high {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-clk-divisor-hs-mode = <0x02>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ nvidia,i2c-hs-stop-setup-time = <0x09>;
+ nvidia,i2c-hs-start-hold-time = <0x09>;
+ nvidia,i2c-hs-start-setup-time = <0x09>;
+ };
+
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+
+ };
+ };
+
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-cfg.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-cfg.dtsi
new file mode 100644
index 000000000000..3eb13c06d34d
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000-cfg.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "tegra234-cfg.dtsi"
+
+/ {
+ bus@0 {
+ i2c@3160000 {
+ config {
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ };
+ };
+
+ i2c@3180000 {
+ config {
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ standard {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ nvidia,i2c-sclk-low-period = <0x08>;
+ nvidia,i2c-bus-free-time = <0x08>;
+ nvidia,i2c-stop-setup-time = <0x08>;
+ nvidia,i2c-start-hold-time = <0x08>;
+ nvidia,i2c-start-setup-time = <0x08>;
+ };
+ };
+ };
+
+ i2c@3190000 {
+ config {
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ };
+ };
+
+ i2c@31c0000 {
+ config {
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ };
+ };
+
+ i2c@31e0000 {
+ config {
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ };
+ };
+
+ i2c@c240000 {
+ config {
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ };
+ };
+
+ i2c@c250000 {
+ config {
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x16>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ nvidia,i2c-sclk-low-period = <0x02>;
+ nvidia,i2c-bus-free-time = <0x02>;
+ nvidia,i2c-stop-setup-time = <0x02>;
+ nvidia,i2c-start-hold-time = <0x02>;
+ nvidia,i2c-start-setup-time = <0x02>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
index cb792041fc62..71506c51a5ea 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
@@ -2,6 +2,7 @@
#include "tegra234.dtsi"
#include "tegra234-p3701.dtsi"
+#include "tegra234-p3701-0000-cfg.dtsi"
/ {
model = "NVIDIA Jetson AGX Orin";
--
2.43.2
SDHCI vendor tuning registers are configured using config setting
framework. Document available config for Tegra SDHCI controllers.
Signed-off-by: Krishna Yarlagadda <[email protected]>
---
.../bindings/mmc/nvidia,tegra20-sdhci.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
index 72987f0326a1..002bc1ffc156 100644
--- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
@@ -177,6 +177,37 @@ properties:
operates at a 1.8 V fixed I/O voltage.
$ref: /schemas/types.yaml#/definitions/flag
+ config:
+ description: Config settings for SDHCI devices.
+ Config setting is the configuration based on chip/board/system
+ characterization on interface/controller settings. This is needed for
+ - making the controller internal configuration to better perform
+ - making the interface to work proper by setting drive strength, slew
+ rates etc
+ - making the low power leakage.
+ SDHCI has configuration based on device speed modes.
+ - common is set on all speeds and can be overridden by speed mode.
+ - List of speed modes and their config name
+ "default", /* MMC_TIMING_LEGACY */
+ "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */
+ "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */
+ "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */
+ "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */
+ "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */
+ "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */
+ "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */
+ "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */
+ "mmc-hs200", /* MMC_TIMING_MMC_HS200 */
+ "mmc-hs400", /* MMC_TIMING_MMC_HS400 */
+ type: object
+ unevaluatedProperties: true
+ properties:
+ nvidia,num-tuning-iter:
+ description: Specify DQS trim value for HS400 timing.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+
required:
- compatible
- reg
@@ -278,6 +309,11 @@ examples:
wp-gpios = <&gpio 57 0>; /* gpio PH1 */
power-gpios = <&gpio 155 0>; /* gpio PT3 */
bus-width = <8>;
+ config {
+ mmc-hs200 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+ };
};
- |
--
2.43.2
I2C interface timing registers are configured using config setting
framework. Document available properties for Tegra I2C controllers.
Signed-off-by: Krishna Yarlagadda <[email protected]>
---
.../bindings/i2c/nvidia,tegra20-i2c.yaml | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
index 424a4fc218b6..3b22e75e5aa0 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
@@ -119,6 +119,96 @@ properties:
- const: rx
- const: tx
+ config:
+ description: Config settings for I2C devices enlisted with I2C controller.
+ Config setting is the configuration based on chip/board/system
+ characterization on interface/controller settings. This is needed for
+ - making the controller internal configuration to better perform
+ - making the interface to work proper by setting drive strength, slew
+ rates etc
+ - making the low power leakage.
+ There are two types of recommended configuration settings
+ - Controller register specific for internal operation of controller.
+ - Pad control/Pinmux/pincontrol registers for interfacing.
+ These configurations can further be categorized as static and dynamic.
+ - Static config does not change until a controller is reset.
+ - Dynamic config changes based on mode or condition, controller is
+ operating in.
+ I2C has configuration based on clock speed and has below modes.
+ - common is set on all speeds and can be overridden by speed mode.
+ - high is set when clock mode is high speed.
+ - fastplus is set when clock mode is fast plus.
+ - fast is set when clock mode is fast mode.
+ - standard is set when clock mode is standard mode.
+ $ref: /schemas/misc/nvidia,tegra-config-settings.yaml
+ unevaluatedProperties: false
+ properties:
+ nvidia,i2c-clk-divisor-hs-mode:
+ description: I2C clock divisor for HS mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-clk-divisor-fs-mode:
+ description: I2C clock divisor for FS mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-hs-sclk-high-period:
+ description: I2C high speed sclk high period.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-hs-sclk-low-period:
+ description: I2C high speed sclk low period.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-hs-stop-setup-time:
+ description: I2C high speed stop setup time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-hs-start-hold-time:
+ description: I2C high speed start hold time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-hs-start-setup-time:
+ description: I2C high speed start setup time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-sclk-high-period:
+ description: I2C sclk high period.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-sclk-low-period:
+ description: I2C sclk low period.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-bus-free-time:
+ description: I2C bus free time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-stop-setup-time:
+ description: I2C stop setup time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-start-hold-time:
+ description: I2C start hold time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+ nvidia,i2c-start-setup-time:
+ description: I2C start setup time.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 0xffff
+
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml
- if:
@@ -189,4 +279,18 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
+ config {
+ common {
+ nvidia,i2c-hs-sclk-high-period = <0x03>;
+ nvidia,i2c-hs-sclk-low-period = <0x08>;
+ };
+ fast {
+ nvidia,i2c-clk-divisor-fs-mode = <0x3c>;
+ nvidia,i2c-sclk-high-period = <0x02>;
+ };
+ fastplus {
+ nvidia,i2c-clk-divisor-fs-mode = <0x4f>;
+ nvidia,i2c-sclk-high-period = <0x07>;
+ };
+ };
};
--
2.43.2
Set SDHCI timing registers through config settings for
Tegra234 chip and P3701 board.
Signed-off-by: Krishna Yarlagadda <[email protected]>
---
arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi | 32 ++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
index 832538e45797..f9a92853b04a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-cfg.dtsi
@@ -442,5 +442,37 @@ standard {
};
};
+ mmc@3400000 {
+ config {
+
+ mmc-hs200 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ uhs-sdr104 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ uhs-sdr50 {
+ nvidia,num-tuning-iter = <0x4>;
+ };
+
+ };
+ };
+
+ mmc@3460000 {
+ config {
+
+ mmc-hs200 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ mmc-hs400 {
+ nvidia,num-tuning-iter = <0x2>;
+ };
+
+ };
+ };
+
};
};
--
2.43.2
Use config settings framework to initialize Tegra SDHCI
timing registers
Signed-off-by: Krishna Yarlagadda <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
---
drivers/mmc/host/sdhci-tegra.c | 84 ++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 1ad0a6b3a2eb..87fe85991617 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -28,6 +28,7 @@
#include <linux/reset.h>
#include <soc/tegra/common.h>
+#include <soc/tegra/tegra-cfg.h>
#include "sdhci-cqhci.h"
#include "sdhci-pltfm.h"
@@ -64,6 +65,7 @@
#define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31)
#define SDHCI_VNDR_TUN_CTRL0_0 0x1c0
+#define SDHCI_VNDR_TUN_CTRL0_CMD_CRC_ERR_EN BIT(28)
#define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000
#define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000
#define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18
@@ -74,6 +76,7 @@
#define TRIES_128 2
#define TRIES_256 4
#define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7
+#define SDHCI_VNDR_TUN_CTRL0_DIV_N_MASK GENMASK(5, 3)
#define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4
#define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8
@@ -134,6 +137,20 @@
SDHCI_TRNS_BLK_CNT_EN | \
SDHCI_TRNS_DMA)
+static const char * const cfg_device_states[] = {
+ "default", /* MMC_TIMING_LEGACY */
+ "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */
+ "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */
+ "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */
+ "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */
+ "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */
+ "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */
+ "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */
+ "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */
+ "mmc-hs200", /* MMC_TIMING_MMC_HS200 */
+ "mmc-hs400", /* MMC_TIMING_MMC_HS400 */
+};
+
struct sdhci_tegra_soc_data {
const struct sdhci_pltfm_data *pdata;
u64 dma_mask;
@@ -158,6 +175,18 @@ struct sdhci_tegra_autocal_offsets {
u32 pull_down_hs400;
};
+static const struct tegra_cfg_field_desc sdhci_cfg_fields[] = {
+ TEGRA_CFG_FIELD("nvidia,num-tuning-iter",
+ SDHCI_VNDR_TUN_CTRL0_0,
+ SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK),
+};
+
+static struct tegra_cfg_desc sdhci_cfg_desc = {
+ .num_regs = 0,
+ .num_fields = ARRAY_SIZE(sdhci_cfg_fields),
+ .fields = sdhci_cfg_fields,
+};
+
struct sdhci_tegra {
const struct sdhci_tegra_soc_data *soc_data;
struct gpio_desc *power_gpio;
@@ -183,6 +212,7 @@ struct sdhci_tegra {
unsigned long curr_clk_rate;
u8 tuned_tap_delay;
u32 stream_id;
+ struct tegra_cfg_list *list;
};
static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
@@ -362,6 +392,30 @@ static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
}
}
+static void tegra_sdhci_write_cfg_settings(struct sdhci_host *host,
+ const char *name)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
+ struct tegra_cfg_reg *regs;
+ struct tegra_cfg *cfg;
+ unsigned int i;
+ u32 val;
+
+ cfg = tegra_cfg_get_by_name(mmc_dev(host->mmc),
+ tegra_host->list, name);
+ if (!cfg)
+ return;
+
+ regs = cfg->regs;
+ for (i = 0; i < cfg->num_regs; ++i) {
+ val = sdhci_readl(host, regs[i].offset);
+ val &= ~regs[i].mask;
+ val |= regs[i].value;
+ sdhci_writel(host, val, regs[i].offset);
+ }
+}
+
static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -374,6 +428,8 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
if (!(mask & SDHCI_RESET_ALL))
return;
+ tegra_sdhci_write_cfg_settings(host, "common");
+
tegra_sdhci_set_tap(host, tegra_host->default_tap);
misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
@@ -1011,6 +1067,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
bool set_default_tap = false;
bool set_dqs_trim = false;
bool do_hs400_dll_cal = false;
+ bool set_config = false;
u8 iter = TRIES_256;
u32 val;
@@ -1027,6 +1084,7 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
set_dqs_trim = true;
do_hs400_dll_cal = true;
iter = TRIES_128;
+ set_config = true;
break;
case MMC_TIMING_MMC_DDR52:
case MMC_TIMING_UHS_DDR50:
@@ -1059,6 +1117,9 @@ static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
else
tegra_sdhci_set_tap(host, tegra_host->default_tap);
+ if (set_config)
+ tegra_sdhci_write_cfg_settings(host,
+ cfg_device_states[timing]);
if (set_dqs_trim)
tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
@@ -1129,6 +1190,29 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
static int tegra_sdhci_init_pinctrl_info(struct device *dev,
struct sdhci_tegra *tegra_host)
{
+ unsigned int i, j, count;
+ const struct tegra_cfg_field_desc *fields;
+
+ count = 0;
+ fields = sdhci_cfg_fields;
+
+ for (i = 0; i < sdhci_cfg_desc.num_fields; i++) {
+ for (j = 0; j < i; j++)
+ if (fields[i].offset == fields[j].offset)
+ break;
+
+ if (i == j)
+ count++;
+ }
+
+ sdhci_cfg_desc.num_regs = count;
+ tegra_host->list = tegra_cfg_get(dev, NULL, &sdhci_cfg_desc);
+ if (IS_ERR(tegra_host->list)) {
+ dev_dbg(dev, "Config setting not available, err: %ld\n",
+ PTR_ERR(tegra_host->list));
+ tegra_host->list = NULL;
+ }
+
tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
dev_dbg(dev, "No pinctrl info, err: %ld\n",
--
2.43.2
On 07/05/2024 00:51, Krishna Yarlagadda wrote:
> I2C interface timing registers are configured using config setting
> framework. Document available properties for Tegra I2C controllers.
>
> Signed-off-by: Krishna Yarlagadda <[email protected]>
> ---
> .../bindings/i2c/nvidia,tegra20-i2c.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
You called it RFC, so not ready for review, thus just few remarks.
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> index 424a4fc218b6..3b22e75e5aa0 100644
> --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> @@ -119,6 +119,96 @@ properties:
> - const: rx
> - const: tx
>
> + config:
> + description: Config settings for I2C devices enlisted with I2C controller.
> + Config setting is the configuration based on chip/board/system
> + characterization on interface/controller settings. This is needed for
> + - making the controller internal configuration to better perform
> + - making the interface to work proper by setting drive strength, slew
> + rates etc
> + - making the low power leakage.
> + There are two types of recommended configuration settings
> + - Controller register specific for internal operation of controller.
> + - Pad control/Pinmux/pincontrol registers for interfacing.
> + These configurations can further be categorized as static and dynamic.
> + - Static config does not change until a controller is reset.
> + - Dynamic config changes based on mode or condition, controller is
> + operating in.
> + I2C has configuration based on clock speed and has below modes.
> + - common is set on all speeds and can be overridden by speed mode.
> + - high is set when clock mode is high speed.
> + - fastplus is set when clock mode is fast plus.
> + - fast is set when clock mode is fast mode.
> + - standard is set when clock mode is standard mode.
> + $ref: /schemas/misc/nvidia,tegra-config-settings.yaml
> + unevaluatedProperties: false
> + properties:
> + nvidia,i2c-clk-divisor-hs-mode:
> + description: I2C clock divisor for HS mode.
So you decided to implement clocks in DT? No.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 0xffff
Anyway divisors, clock rates and everything is human-readable so in
decimal, not hex.
There are also several issues further, like using wrong units (time has
a unit), but since this is RFC, I will just NAK.
Best regards,
Krzysztof
On 07/05/2024 00:51, Krishna Yarlagadda wrote:
> SDHCI vendor tuning registers are configured using config setting
> framework. Document available config for Tegra SDHCI controllers.
>
> Signed-off-by: Krishna Yarlagadda <[email protected]>
> ---
> .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
> index 72987f0326a1..002bc1ffc156 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml
> @@ -177,6 +177,37 @@ properties:
> operates at a 1.8 V fixed I/O voltage.
> $ref: /schemas/types.yaml#/definitions/flag
>
> + config:
No. This node does not re
> + description: Config settings for SDHCI devices.
> + Config setting is the configuration based on chip/board/system
> + characterization on interface/controller settings. This is needed for
> + - making the controller internal configuration to better perform
> + - making the interface to work proper by setting drive strength, slew
> + rates etc
> + - making the low power leakage.
> + SDHCI has configuration based on device speed modes.
> + - common is set on all speeds and can be overridden by speed mode.
> + - List of speed modes and their config name
> + "default", /* MMC_TIMING_LEGACY */
> + "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */
> + "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */
> + "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */
> + "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */
> + "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */
> + "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */
> + "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */
> + "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */
> + "mmc-hs200", /* MMC_TIMING_MMC_HS200 */
> + "mmc-hs400", /* MMC_TIMING_MMC_HS400 */
> + type: object
> + unevaluatedProperties: true
NAK.
> + properties:
> + nvidia,num-tuning-iter:
> + description: Specify DQS trim value for HS400 timing.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + minimum: 0
> + maximum: 0xffff
"iterations" is decimal value. How it can be 0? 0 tries to time?
Best regards,
Krzysztof
On 07/05/2024 00:51, Krishna Yarlagadda wrote:
>
> Patch 01: Documentation about the device tree binding for common config framework.
> Patch 02: Common parser of the device tree config setting node for Tegra SoC.
> Patch 03: Device tree binding documentation for config setting.
> Patch 04: Device tree binding documentation for the I2C config setting.
> Patch 05: Avoid config settings child node to be treated as I2C device.
> Patch 06: Move clock initialization code into new methods
> Patch 07: Using config settings in Tegra I2C driver for interface timing registers.
> Patch 08: Add Tegra234 I2C config settings in DT.
> Patch 09: Device tree binding documentation for the SDHCI config setting.
> Patch 10: Using config settings in Tegra SDHCI driver for tuning iteration.
> Patch 11: Add Tegra234 SDHCI config settings in DT.
>
> Known Issues:
> - DTC warning for config 'missing or empty reg property for I2C nodes'
Which should stop you from sending buggy code, till you fix it.
Best regards,
Krzysztof
On Tue, 07 May 2024 04:21:32 +0530, Krishna Yarlagadda wrote:
> I2C interface timing registers are configured using config setting
> framework. Document available properties for Tegra I2C controllers.
>
> Signed-off-by: Krishna Yarlagadda <[email protected]>
> ---
> .../bindings/i2c/nvidia,tegra20-i2c.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.example.dts:37.20-50.15: Warning (i2c_bus_reg): /example-0/i2c@7000c000/config: missing or empty reg property
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.