2024-05-15 18:51:55

by Dmitry Rokosov

Subject: [PATCH v3 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll input

The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.

Signed-off-by: Dmitry Rokosov <[email protected]>
---
.../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 9 +++++++--
include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h | 1 +
2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
index 6d84cee1bd75..2568ad7dd0ac 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
@@ -30,6 +30,8 @@ properties:
- description: input fixed pll div7
- description: input hifi pll
- description: input oscillator (usually at 24MHz)
+ - description: input sys pll
+ minItems: 6 # sys_pll is optional

clock-names:
items:
@@ -39,6 +41,8 @@ properties:
- const: fclk_div7
- const: hifi_pll
- const: xtal
+ - const: sys_pll
+ minItems: 6 # sys_pll is optional

required:
- compatible
@@ -65,9 +69,10 @@ examples:
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
- <&xtal>;
+ <&xtal>,
+ <&clkc_pll CLKID_SYS_PLL>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
- "hifi_pll", "xtal";
+ "hifi_pll", "xtal", "sys_pll";
};
};
diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
index 06f198ee7623..2ce1a06dc735 100644
--- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
+++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
@@ -164,5 +164,6 @@
#define CLKID_DMC_SEL 151
#define CLKID_DMC_DIV 152
#define CLKID_DMC_SEL2 153
+#define CLKID_SYS_PLL_DIV16 154

#endif /* __A1_PERIPHERALS_CLKC_H */
--
2.43.0

2024-05-15 19:00:34

by Dmitry Rokosov

Subject: Re: [PATCH v3 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll input

Hello Conor,

On Wed, May 15, 2024 at 09:47:27PM +0300, Dmitry Rokosov wrote:
> The 'sys_pll' input is an optional clock that can be used to generate
> 'sys_pll_div16', which serves as one of the sources for the GEN clock.
>
> Signed-off-by: Dmitry Rokosov <[email protected]>

I didn't tag this patch with your Acked-by because I've changed the
connection between the A1 PLL and the A1 peripherals controllers from
'sys_pll_div16' to 'sys_pll'.

Please review this patch again, if possible.

> ---
> .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 9 +++++++--
> include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
> index 6d84cee1bd75..2568ad7dd0ac 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
> @@ -30,6 +30,8 @@ properties:
> - description: input fixed pll div7
> - description: input hifi pll
> - description: input oscillator (usually at 24MHz)
> + - description: input sys pll
> + minItems: 6 # sys_pll is optional
>
> clock-names:
> items:
> @@ -39,6 +41,8 @@ properties:
> - const: fclk_div7
> - const: hifi_pll
> - const: xtal
> + - const: sys_pll
> + minItems: 6 # sys_pll is optional
>
> required:
> - compatible
> @@ -65,9 +69,10 @@ examples:
> <&clkc_pll CLKID_FCLK_DIV5>,
> <&clkc_pll CLKID_FCLK_DIV7>,
> <&clkc_pll CLKID_HIFI_PLL>,
> - <&xtal>;
> + <&xtal>,
> + <&clkc_pll CLKID_SYS_PLL>;
> clock-names = "fclk_div2", "fclk_div3",
> "fclk_div5", "fclk_div7",
> - "hifi_pll", "xtal";
> + "hifi_pll", "xtal", "sys_pll";
> };
> };
> diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
> index 06f198ee7623..2ce1a06dc735 100644
> --- a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
> +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
> @@ -164,5 +164,6 @@
> #define CLKID_DMC_SEL 151
> #define CLKID_DMC_DIV 152
> #define CLKID_DMC_SEL2 153
> +#define CLKID_SYS_PLL_DIV16 154
>
> #endif /* __A1_PERIPHERALS_CLKC_H */
> --
> 2.43.0
>

--
Thank you,
Dmitry

2024-05-20 19:18:32

by Rob Herring (Arm)

Subject: Re: [PATCH v3 4/7] dt-bindings: clock: meson: a1: peripherals: support sys_pll input

On Wed, 15 May 2024 21:47:27 +0300, Dmitry Rokosov wrote:
> The 'sys_pll' input is an optional clock that can be used to generate
> 'sys_pll_div16', which serves as one of the sources for the GEN clock.
>
> Signed-off-by: Dmitry Rokosov <[email protected]>
> ---
> .../bindings/clock/amlogic,a1-peripherals-clkc.yaml | 9 +++++++--
> include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h | 1 +
> 2 files changed, 8 insertions(+), 2 deletions(-)
>

Acked-by: Rob Herring (Arm) <[email protected]>