2024-05-24 14:10:39

by Breno Leitao

Subject: [PATCH] perf/x86/amd: Warn only on new bits set

Warning at every leaking bits can cause a flood of message, triggering
vairous stall-warning mechanisms to fire, including CSD locks, which
makes the machine to be unusable.

Track the bits that are being leaked, and only warn when a new bit is
set.

Suggested-by: Paul E. McKenney <[email protected]>
Signed-off-by: Breno Leitao <[email protected]>
---
arch/x86/events/amd/core.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 1fc4ce44e743..df0ba2382d13 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -941,11 +941,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u
static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
{
struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+ static atomic64_t status_warned = ATOMIC64_INIT(0);
+ u64 reserved, status, mask, new_bits;
struct perf_sample_data data;
struct hw_perf_event *hwc;
struct perf_event *event;
int handled = 0, idx;
- u64 reserved, status, mask;
bool pmu_enabled;

/*
@@ -1010,7 +1011,11 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
* the corresponding PMCs are expected to be inactive according to the
* active_mask
*/
- WARN_ON(status > 0);
+ if (status > 0) {
+ new_bits = atomic64_fetch_or(status, &status_warned) ^ atomic64_read(&status_warned);
+ // A new bit was set for the very first time.
+ WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);
+ }

/* Clear overflow and freeze bits */
amd_pmu_ack_global_status(~status);
--
2.43.0

2024-06-06 05:34:42

by Sandipan Das

Subject: Re: [PATCH] perf/x86/amd: Warn only on new bits set

On 5/24/2024 7:40 PM, Breno Leitao wrote:
> Warning at every leaking bits can cause a flood of message, triggering
> vairous stall-warning mechanisms to fire, including CSD locks, which
> makes the machine to be unusable.
>
> Track the bits that are being leaked, and only warn when a new bit is
> set.
>
> Suggested-by: Paul E. McKenney <[email protected]>
> Signed-off-by: Breno Leitao <[email protected]>

Reviewed-by: Sandipan Das <[email protected]>

> ---
> arch/x86/events/amd/core.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index 1fc4ce44e743..df0ba2382d13 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -941,11 +941,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u
> static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> + static atomic64_t status_warned = ATOMIC64_INIT(0);
> + u64 reserved, status, mask, new_bits;
> struct perf_sample_data data;
> struct hw_perf_event *hwc;
> struct perf_event *event;
> int handled = 0, idx;
> - u64 reserved, status, mask;
> bool pmu_enabled;
>
> /*
> @@ -1010,7 +1011,11 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
> * the corresponding PMCs are expected to be inactive according to the
> * active_mask
> */
> - WARN_ON(status > 0);
> + if (status > 0) {
> + new_bits = atomic64_fetch_or(status, &status_warned) ^ atomic64_read(&status_warned);
> + // A new bit was set for the very first time.
> + WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);
> + }
>
> /* Clear overflow and freeze bits */
> amd_pmu_ack_global_status(~status);