Hi all,
This series enables ARCH_SUPPORTS_ATOMIC_RMW for MIPS.
The first two patches are for making LLSC availability information
available to Kconfig, and the last two select actual options.
Please review.
v1: https://lore.kernel.org/all/[email protected]/
Thanks
- Jiaxun
Signed-off-by: Jiaxun Yang <[email protected]>
---
Jiaxun Yang (4):
MIPS: Introduce WAR_4KC_LLSC config option
MIPS: Introduce config options for LLSC availability
MIPS: Select ARCH_SUPPORTS_ATOMIC_RMW when possible
MIPS: Select ARCH_HAVE_NMI_SAFE_CMPXCHG when possible
arch/mips/Kconfig | 28 ++++++++++++++++++++++
arch/mips/include/asm/cpu-features.h | 9 ++++++-
arch/mips/include/asm/cpu.h | 1 +
.../include/asm/mach-ath25/cpu-feature-overrides.h | 6 ++---
arch/mips/kernel/cpu-probe.c | 9 +++++++
5 files changed, 48 insertions(+), 5 deletions(-)
---
base-commit: 03d44168cbd7fc57d5de56a3730427db758fc7f6
change-id: 20240612-mips-llsc-1f2fb9169c0b
Best regards,
--
Jiaxun Yang <[email protected]>
Select ARCH_SUPPORTS_ATOMIC_RMW when we are certain that our CPU
have LLSC support.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 50260a7e9b54..e83036580a47 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -23,6 +23,7 @@ config MIPS
select ARCH_USE_MEMTEST
select ARCH_USE_QUEUED_RWLOCKS
select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_SUPPORTS_ATOMIC_RMW if CPU_HAS_LLSC
select ARCH_SUPPORTS_HUGETLBFS if CPU_SUPPORTS_HUGEPAGES
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
select ARCH_WANT_IPC_PARSE_VERSION
--
2.43.0
Introduce CPU_HAS_LLSC and CPU_MAY_HAVE_LLSC to determine availability
of LLSC and Kconfig level.
They are both true for almost all supported CPUs besides:
R3000: Doesn't have LLSC, so both false.
R5000 series: LLSC is unusable for 64bit kernel, so both false.
R10000: Some platforms decided to opt-out LLSC due to errata, so only
select CPU_MAY_HAVE_LLSC.
WAR_4KC_LLSC: LLSC is buggy on certain reversion, which can be detected
at cpu-probe or platform override, so only select CPU_MAY_HAVE_LLSC.
Signed-off-by: Jiaxun Yang <[email protected]>
---
v2: Make cpu_has_llsc logic clear
---
arch/mips/Kconfig | 20 ++++++++++++++++++++
arch/mips/include/asm/cpu-features.h | 9 ++++++++-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 8ac467c1f9c8..50260a7e9b54 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1548,6 +1548,7 @@ config CPU_R3000
config CPU_R4300
bool "R4300"
depends on SYS_HAS_CPU_R4300
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
help
@@ -1556,6 +1557,7 @@ config CPU_R4300
config CPU_R4X00
bool "R4x00"
depends on SYS_HAS_CPU_R4X00
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1566,6 +1568,7 @@ config CPU_R4X00
config CPU_TX49XX
bool "R49XX"
depends on SYS_HAS_CPU_TX49XX
+ select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1574,6 +1577,7 @@ config CPU_TX49XX
config CPU_R5000
bool "R5000"
depends on SYS_HAS_CPU_R5000
+ select CPU_HAS_LLSC if !64BIT
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1583,6 +1587,7 @@ config CPU_R5000
config CPU_R5500
bool "R5500"
depends on SYS_HAS_CPU_R5500
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1593,6 +1598,7 @@ config CPU_R5500
config CPU_NEVADA
bool "RM52xx"
depends on SYS_HAS_CPU_NEVADA
+ select CPU_HAS_LLSC if !64BIT
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1602,6 +1608,8 @@ config CPU_NEVADA
config CPU_R10000
bool "R10000"
depends on SYS_HAS_CPU_R10000
+ select CPU_HAS_LLSC if !WAR_R10000_LLSC
+ select CPU_MAY_HAVE_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1613,6 +1621,7 @@ config CPU_R10000
config CPU_RM7000
bool "RM7000"
depends on SYS_HAS_CPU_RM7000
+ select CPU_HAS_LLSC
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
@@ -1622,6 +1631,7 @@ config CPU_RM7000
config CPU_SB1
bool "SB1"
depends on SYS_HAS_CPU_SB1
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1656,6 +1666,7 @@ config CPU_BMIPS
select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
+ select CPU_HAS_LLSC
select CPU_SUPPORTS_32BIT_KERNEL
select DMA_NONCOHERENT
select IRQ_MIPS_CPU
@@ -2381,6 +2392,15 @@ config CPU_DIEI_BROKEN
config CPU_HAS_RIXI
bool
+# For CPU that must have LLSC
+config CPU_HAS_LLSC
+ def_bool TARGET_ISA_REV > 0 && !WAR_4KC_LLSC
+ select CPU_MAY_HAVE_LLSC
+
+# For CPU that LLSC support is optional
+config CPU_MAY_HAVE_LLSC
+ def_bool TARGET_ISA_REV > 0
+
config CPU_NO_LOAD_STORE_LR
bool
help
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 404390bb87ea..40f5570de563 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -185,8 +185,15 @@
#ifndef cpu_has_ejtag
#define cpu_has_ejtag __opt(MIPS_CPU_EJTAG)
#endif
+
#ifndef cpu_has_llsc
-#define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC)
+# if defined(CONFIG_CPU_HAS_LLSC)
+# define cpu_has_llsc 1
+# elif defined(CONFIG_CPU_MAY_HAVE_LLSC)
+# define cpu_has_llsc __opt(MIPS_CPU_LLSC)
+# else
+# define cpu_has_llsc 0
+# endif
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc cpu_has_llsc
--
2.43.0
LLSC based CMPXCHG is safe for NMI.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e83036580a47..1bb274c50636 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -17,6 +17,7 @@ config MIPS
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UBSAN
select ARCH_HAS_GCOV_PROFILE_ALL
+ select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_HAS_LLSC
select ARCH_KEEP_MEMBLOCK
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
--
2.43.0
WAR_4KC_LLSC is used to control workaround of 4KC LLSC issue
that affects 4Kc up to version 0.9.
Early ath25 chips are known to be affected.
Signed-off-by: Jiaxun Yang <[email protected]>
---
v2:
- Improve error message, taint kernel on error
- Don't override cpu_has_llsc if WAR_4KC_LLSC is not selected,
cpu-probe logic can handle it, there is no need to mess around
ifdef as suggested in previous review comments as WAR_4KC_LLSC
is gated by SOC_AR5312.
---
arch/mips/Kconfig | 6 ++++++
arch/mips/include/asm/cpu.h | 1 +
arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h | 6 ++----
arch/mips/kernel/cpu-probe.c | 9 +++++++++
4 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1236ea122061..8ac467c1f9c8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -221,6 +221,7 @@ config ATH25
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_HAS_EARLY_PRINTK
+ select WAR_4KC_LLSC if SOC_AR5312
help
Support for Atheros AR231x and Atheros AR531x based boards
@@ -2543,6 +2544,11 @@ config WAR_ICACHE_REFILLS
config WAR_R10000_LLSC
bool
+# On 4Kc up to version 0.9 (PRID_REV < 1) there is a bug that may cause llsc
+# sequences to deadlock.
+config WAR_4KC_LLSC
+ bool
+
# 34K core erratum: "Problems Executing the TLBR Instruction"
config WAR_MIPS34K_MISSED_ITLB
bool
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index ecb9854cb432..84bb1931a8b4 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -247,6 +247,7 @@
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
+#define PRID_REV_4KC_V1_0 0x0001
#define PRID_REV_34K_V1_0_2 0x0022
#define PRID_REV_LOONGSON1B 0x0020
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
diff --git a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
index ec3604c44ef2..4cf3d1ffba1a 100644
--- a/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
@@ -24,14 +24,12 @@
#define cpu_has_counter 1
#define cpu_has_ejtag 1
-#if !defined(CONFIG_SOC_AR5312)
-# define cpu_has_llsc 1
-#else
/*
* The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
* ll/sc instructions.
*/
-# define cpu_has_llsc 0
+#if !defined(WAR_4KC_LLSC)
+# define cpu_has_llsc 1
#endif
#define cpu_has_mips16 0
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bda7f193baab..ff2905f59f2a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -152,6 +152,15 @@ static inline void check_errata(void)
struct cpuinfo_mips *c = ¤t_cpu_data;
switch (current_cpu_type()) {
+ case CPU_4KC:
+ if ((c->processor_id & PRID_REV_MASK) < PRID_REV_4KC_V1_0) {
+ c->options &= ~MIPS_CPU_LLSC;
+ if (cpu_has_llsc) {
+ pr_crit("CPU has LLSC erratum, but cpu_has_llsc is force enabled!\n");
+ add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
+ }
+ }
+ break;
case CPU_34K:
/*
* Erratum "RPS May Cause Incorrect Instruction Execution"
--
2.43.0