Update GCC, GPUCC clock controller drivers on SA8775P platform.
Changes in V2:
[PATCH 1/6]: Dropped fixes tag for removing ufs hw ctl clocks
[PATCH 3/6]: Updated commit text on setting FORCE_MEM_CORE_ON
bit for ufs phy ice core clk
[PATCH 4/6]: Updated commit text on removing CLK_IS_CRITICAL
for GPU clocks
Link to V1: https://lore.kernel.org/all/[email protected]/
Multimedia clock controller patches from above v1 series have
been split to a separate series:
https://lore.kernel.org/lkml/20240612-sa8775p-mm-clock-controllers-v1-0-db295a846ee7@quicinc.com/T/#t
---
Taniya Das (6):
clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks
clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags
clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk
clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags
clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable
clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's
drivers/clk/qcom/gcc-sa8775p.c | 154 ++++++++++++---------------------------
drivers/clk/qcom/gpucc-sa8775p.c | 41 ++++++-----
2 files changed, 66 insertions(+), 129 deletions(-)
---
base-commit: 03d44168cbd7fc57d5de56a3730427db758fc7f6
change-id: 20240612-sa8775p-v2-gcc-gpucc-fixes-ec128d5847e8
Best regards,
--
Taniya Das <[email protected]>
Update the GDSC wait_val fields as per the default hardware values as
otherwise they would lead to GDSC FSM state to be stuck and causing
failures to power on/off. Also add the GDSC flags as applicable and
add support to control PCIE GDSC's using collapse vote registers.
Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gcc-sa8775p.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 7bb7aa3a7be5..71fa95f59a0a 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4203,74 +4203,114 @@ static struct clk_branch gcc_video_axi1_clk = {
static struct gdsc pcie_0_gdsc = {
.gdscr = 0xa9004,
+ .collapse_ctrl = 0x4b104,
+ .collapse_mask = BIT(0),
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc pcie_1_gdsc = {
.gdscr = 0x77004,
+ .collapse_ctrl = 0x4b104,
+ .collapse_mask = BIT(1),
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc ufs_card_gdsc = {
.gdscr = 0x81004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "ufs_card_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x83004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc usb20_prim_gdsc = {
.gdscr = 0x1c004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "usb20_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc usb30_prim_gdsc = {
.gdscr = 0x1b004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc usb30_sec_gdsc = {
.gdscr = 0x2f004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "usb30_sec_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc emac0_gdsc = {
.gdscr = 0xb6004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "emac0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct gdsc emac1_gdsc = {
.gdscr = 0xb4004,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "emac1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
+ .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR,
};
static struct clk_regmap *gcc_sa8775p_clocks[] = {
--
2.45.2
Update the force mem core bit for UFS ICE clock to force the core on
signal to remain active during halt state of the clk. If force mem
core bit of the clock is not set, the memories of the subsystem will
not retain the logic across power states.
Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gcc-sa8775p.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 71fa95f59a0a..23b5207dc606 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -4686,6 +4686,9 @@ static int gcc_sa8775p_probe(struct platform_device *pdev)
qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */
qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */
+ /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
+ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
+
return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap);
}
--
2.45.2
The UFS hw ctl clocks are not used by any consumers on SA8775P,
and these clocks are not using the correct clock ops to manage the
hw ctl of the branch clock, hence remove these clocks.
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gcc-sa8775p.c | 111 +----------------------------------------
1 file changed, 2 insertions(+), 109 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c
index 5bcbfbf52cb9..7bb7aa3a7be5 100644
--- a/drivers/clk/qcom/gcc-sa8775p.c
+++ b/drivers/clk/qcom/gcc-sa8775p.c
@@ -1,14 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
-#include <linux/clk.h>
#include <linux/clk-provider.h>
-#include <linux/err.h>
-#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/mod_devicetable.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -1737,26 +1735,6 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
},
};
-static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
- .halt_reg = 0x830d4,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x830d4,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x830d4,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_aggre_usb2_prim_axi_clk = {
.halt_reg = 0x1c05c,
.halt_check = BRANCH_HALT_VOTED,
@@ -3809,26 +3787,6 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
},
};
-static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
- .halt_reg = 0x83018,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x83018,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x83018,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_axi_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_axi_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x8306c,
.halt_check = BRANCH_HALT_VOTED,
@@ -3849,26 +3807,6 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
},
};
-static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
- .halt_reg = 0x8306c,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x8306c,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x8306c,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x830a4,
.halt_check = BRANCH_HALT_VOTED,
@@ -3889,26 +3827,6 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
},
};
-static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
- .halt_reg = 0x830a4,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x830a4,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x830a4,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x83028,
.halt_check = BRANCH_HALT_DELAY,
@@ -3983,26 +3901,6 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
},
};
-static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
- .halt_reg = 0x83064,
- .halt_check = BRANCH_HALT_VOTED,
- .hwcg_reg = 0x83064,
- .hwcg_bit = 1,
- .clkr = {
- .enable_reg = 0x83064,
- .enable_mask = BIT(1),
- .hw.init = &(const struct clk_init_data){
- .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
- .parent_hws = (const struct clk_hw*[]){
- &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
- },
- },
-};
-
static struct clk_branch gcc_usb20_master_clk = {
.halt_reg = 0x1c018,
.halt_check = BRANCH_HALT,
@@ -4379,7 +4277,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
- [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
@@ -4569,13 +4466,10 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
- [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
- [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
- [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
@@ -4584,7 +4478,6 @@ static struct clk_regmap *gcc_sa8775p_clocks[] = {
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
- [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
--
2.45.2
Update wait_val fields as per the default hardware values of the GDSC as
otherwise it would lead to GDSC FSM state stuck causing power on/off
failures of the GSDC.
Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gpucc-sa8775p.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 1f7a02a7503d..3deabf833388 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -523,6 +523,9 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
static struct gdsc cx_gdsc = {
.gdscr = 0x9108,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.gds_hw_ctrl = 0x953c,
.pd = {
.name = "cx_gdsc",
@@ -533,6 +536,9 @@ static struct gdsc cx_gdsc = {
static struct gdsc gx_gdsc = {
.gdscr = 0x905c,
+ .en_rest_wait_val = 0x2,
+ .en_few_wait_val = 0x2,
+ .clk_dis_wait_val = 0xf,
.pd = {
.name = "gx_gdsc",
.power_on = gdsc_gx_do_nothing_enable,
--
2.45.2
The GPU clocks/GDSCs have been marked critical from the clock driver
but the GPU driver votes on these resources as per the HW requirement.
In the case where these clocks & GDSCs are left enabled, would have
power impact and also cause GPU stability/corruptions.
Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON
flags for the GPU GDSCs.
Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gpucc-sa8775p.c | 27 +++++++++++----------------
1 file changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 1167c42da39d..f965babf4330 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2023, Linaro Limited
*/
@@ -280,7 +280,7 @@ static struct clk_branch gpu_cc_ahb_clk = {
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -294,7 +294,6 @@ static struct clk_branch gpu_cc_cb_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cb_clk",
- .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -312,7 +311,7 @@ static struct clk_branch gpu_cc_crc_ahb_clk = {
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -330,7 +329,7 @@ static struct clk_branch gpu_cc_cx_ff_clk = {
&gpu_cc_ff_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -348,7 +347,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = {
&gpu_cc_gmu_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
@@ -362,7 +361,6 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cx_snoc_dvm_clk",
- .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -380,7 +378,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -398,7 +396,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
&gpu_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
@@ -416,7 +414,7 @@ static struct clk_branch gpu_cc_demet_clk = {
&gpu_cc_demet_div_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
@@ -430,7 +428,6 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
- .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -448,7 +445,7 @@ static struct clk_branch gpu_cc_hub_aon_clk = {
&gpu_cc_hub_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
@@ -466,7 +463,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = {
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
},
.num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_aon_ops,
},
},
@@ -480,7 +477,6 @@ static struct clk_branch gpu_cc_memnoc_gfx_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_memnoc_gfx_clk",
- .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -494,7 +490,6 @@ static struct clk_branch gpu_cc_sleep_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_sleep_clk",
- .flags = CLK_IS_CRITICAL,
.ops = &clk_branch2_ops,
},
},
@@ -533,7 +528,7 @@ static struct gdsc cx_gdsc = {
.name = "cx_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
- .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON,
+ .flags = VOTABLE | RETAIN_FF_ENABLE,
};
static struct gdsc gx_gdsc = {
--
2.45.2
The RCG's clk src has to be parked at XO while disabling as per the
HW recommendation, hence use clk_rcg2_shared_ops to achieve the same.
Also gpu_cc_cb_clk is recommended to be kept always ON, hence use
clk_branch2_aon_ops to keep the clock always ON.
Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gpucc-sa8775p.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index f965babf4330..1f7a02a7503d 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -161,7 +161,7 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = {
.name = "gpu_cc_ff_clk_src",
.parent_data = gpu_cc_parent_data_0,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -181,7 +181,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
.parent_data = gpu_cc_parent_data_1,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -200,7 +200,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
.name = "gpu_cc_hub_clk_src",
.parent_data = gpu_cc_parent_data_2,
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
- .ops = &clk_rcg2_ops,
+ .ops = &clk_rcg2_shared_ops,
},
};
@@ -294,7 +294,7 @@ static struct clk_branch gpu_cc_cb_clk = {
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data){
.name = "gpu_cc_cb_clk",
- .ops = &clk_branch2_ops,
+ .ops = &clk_branch2_aon_ops,
},
},
};
--
2.45.2
On 6/12/24 13:08, Taniya Das wrote:
> Update the force mem core bit for UFS ICE clock to force the core on
> signal to remain active during halt state of the clk. If force mem
> core bit of the clock is not set, the memories of the subsystem will
> not retain the logic across power states.
>
> Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
> Signed-off-by: Taniya Das <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad