From: Hsiao Chien Sung <[email protected]>
Based-on: commit 1613e604df0c ("Linux 6.10-rc1")
This series adds support for running IGT (Intel GPU Tool) tests with
MediaTek display driver. The following changes will be applied:
1. Add a new API for creating GCE thread loop to retrieve CRCs
from the hardware component
2. Support hardware CRC calculation in both VDOSYS0 and VDOSYS1
3. Support alpha blending in both VDOSYS0 and VDOSYS1
Changes in v8:
- Start/Stop CRC CMDQ thread on when needed
- Squash and rearrange the commits
- Add more information to the commit message and comments
Changes in v7:
- Separate the patch into smaller ones
Changes in v6:
- Use drm_vblank_work to deffer the CRC work into bottom halves
- Separate the patches for "Premultiplied" and "None" alpha blending
Changes in v5:
- Add more descriptions to the codes
- Add DRM mode configs to the driver data
- Squash and rearrange the commits
Changes in v4:
- Separate the patch into smaller ones
- Change the title of some patches
- Revert the changes that are not related to the series
Changes in v3:
- Modify the dt-binding document of Mediatek OVL
- Set DRM mode configs accroding to the hardware capabilities
- Replace cmdq_pkt_jump_absolute() with cmdq_pkt_jump()
Changes in v2:
- Simplify CMDQ by adding commands that are currently used only
- Integrate CRC related codes into new APIs for Mixer and OVL to reuse
- Add CPU version CRC retrieval when CMDQ is disabled
Hsiao Chien Sung (16):
soc: mediatek: Disable 9-bit alpha in ETHDR
drm/mediatek: Add OVL compatible name for MT8195
drm/mediatek: Add missing plane settings when async update
drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property
drm/mediatek: Set DRM mode configs accordingly
drm/mediatek: Turn off the layers with zero width or height
drm/mediatek: Support more 10bit formats in OVL
drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195
drm/mediatek: Support "None" blending in OVL
drm/mediatek: Support "None" blending in Mixer
drm/mediatek: Support "Pre-multiplied" blending in OVL
drm/mediatek: Support "Pre-multiplied" blending in Mixer
drm/mediatek: Support alpha blending in display driver
drm/mediatek: Support CRC in display driver
drm/mediatek: Support CRC in OVL
drm/mediatek: Support CRC in OVL adaptor
drivers/gpu/drm/mediatek/mtk_crtc.c | 280 ++++++++++++++++
drivers/gpu/drm/mediatek/mtk_crtc.h | 38 +++
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 10 +
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 11 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 10 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 316 ++++++++++++++++--
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 37 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 +
drivers/gpu/drm/mediatek/mtk_ethdr.c | 106 +++++-
drivers/gpu/drm/mediatek/mtk_ethdr.h | 7 +
drivers/gpu/drm/mediatek/mtk_plane.c | 15 +-
drivers/soc/mediatek/mtk-mmsys.c | 1 +
13 files changed, 816 insertions(+), 43 deletions(-)
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Set DRM mode configs limitation according to the hardware capabilities
and pass the IGT checks as below:
- The test "graphics.IgtKms.kms_plane" requires a frame buffer with
width of 4512 pixels (> 4096).
- The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is
defined, and run the test with cursor size from 1x1 to 512x512.
Please notice that the test conditions may change as IGT is updated.
Reviewed-by: CK Hu <[email protected]>
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 ++++
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 8e047043202b..c9cad3a82737 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -294,6 +294,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
.conn_routes = mt8188_mtk_ddp_main_routes,
.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
.mmsys_dev_num = 2,
+ .max_width = 8191,
+ .min_width = 1,
+ .min_height = 1,
};
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -308,6 +311,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
.mmsys_dev_num = 2,
+ .max_width = 8191,
+ .min_width = 1,
+ .min_height = 1,
};
static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
@@ -315,6 +321,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
.mmsys_id = 1,
.mmsys_dev_num = 2,
+ .max_width = 8191,
+ .min_width = 2, /* 2-pixel align when ethdr is bypassed */
+ .min_height = 1,
};
static const struct of_device_id mtk_drm_of_ids[] = {
@@ -493,6 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
for (j = 0; j < private->data->mmsys_dev_num; j++) {
priv_n = private->all_drm_private[j];
+ if (priv_n->data->max_width)
+ drm->mode_config.max_width = priv_n->data->max_width;
+
+ if (priv_n->data->min_width)
+ drm->mode_config.min_width = priv_n->data->min_width;
+
+ if (priv_n->data->min_height)
+ drm->mode_config.min_height = priv_n->data->min_height;
+
if (i == CRTC_MAIN && priv_n->data->main_len) {
ret = mtk_crtc_create(drm, priv_n->data->main_path,
priv_n->data->main_len, j,
@@ -520,6 +538,10 @@ static int mtk_drm_kms_init(struct drm_device *drm)
}
}
+ /* IGT will check if the cursor size is configured */
+ drm->mode_config.cursor_width = drm->mode_config.max_width;
+ drm->mode_config.cursor_height = drm->mode_config.max_height;
+
/* Use OVL device for all DMA memory allocations */
crtc = drm_crtc_from_index(drm, 0);
if (crtc)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 78d698ede1bf..6cfa790e8df5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data {
bool shadow_register;
unsigned int mmsys_id;
unsigned int mmsys_dev_num;
+
+ int max_width;
+ int min_width;
+ int min_height;
};
struct mtk_drm_private {
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Add OVL compatible name for MT8195.
Without this commit, DRM won't work after modifying the device tree.
Reviewed-by: CK Hu <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b5f605751b0a..8e047043202b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -743,6 +743,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8192-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8195-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt8192-disp-ovl-2l",
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Support more 10bit formats in OVL.
Reviewed-by: CK Hu <[email protected]>
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 ++++++++++++++++++++++---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 862ab683ed1b..d970cdce06bc 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -71,6 +71,22 @@
#define OVL_CON_VIRT_FLIP BIT(9)
#define OVL_CON_HORZ_FLIP BIT(10)
+static inline bool is_10bit_rgb(u32 fmt)
+{
+ switch (fmt) {
+ case DRM_FORMAT_XRGB2101010:
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_BGRX1010102:
+ case DRM_FORMAT_BGRA1010102:
+ return true;
+ }
+ return false;
+}
+
static const u32 mt8173_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
@@ -88,12 +104,18 @@ static const u32 mt8173_formats[] = {
static const u32 mt8195_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_XRGB2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_BGRX8888,
DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_BGRX1010102,
DRM_FORMAT_BGRA1010102,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_XBGR2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_RGBX1010102,
+ DRM_FORMAT_RGBA1010102,
DRM_FORMAT_RGB888,
DRM_FORMAT_BGR888,
DRM_FORMAT_RGB565,
@@ -253,9 +275,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, int idx, u32 format,
reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT);
reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx);
- if (format == DRM_FORMAT_RGBA1010102 ||
- format == DRM_FORMAT_BGRA1010102 ||
- format == DRM_FORMAT_ARGB2101010)
+ if (is_10bit_rgb(format))
bit_depth = OVL_CON_CLRFMT_10_BIT;
reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx);
@@ -368,17 +388,23 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_RGBX8888:
case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_RGBX1010102:
+ case DRM_FORMAT_RGBA1010102:
return OVL_CON_CLRFMT_ARGB8888;
case DRM_FORMAT_BGRX8888:
case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_BGRX1010102:
case DRM_FORMAT_BGRA1010102:
return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XRGB2101010:
case DRM_FORMAT_ARGB2101010:
return OVL_CON_CLRFMT_RGBA8888;
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_XBGR2101010:
+ case DRM_FORMAT_ABGR2101010:
return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
case DRM_FORMAT_UYVY:
return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
We choose OVL as the CRC generator from other hardware
components that are also capable of calculating CRCs,
since its frame done event triggers vblanks, it can be
used as a signal to know when is safe to retrieve CRC of
the frame.
Please note that position of the hardware component
that is chosen as CRC generator in the display path is
significant. For example, while OVL is the first module
in VDOSYS0, its CRC won't be affected by the modules
after it, which means effects applied by PQ, Gamma,
Dither or any other components after OVL won't be
calculated in CRC generation.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 5 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 5 +
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 209 ++++++++++++++++++++++--
3 files changed, 209 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 17b036411292..07c3b5c5e14e 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -351,6 +351,11 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
.clk_enable = mtk_ovl_clk_enable,
.clk_disable = mtk_ovl_clk_disable,
.config = mtk_ovl_config,
+ .crc_cnt = mtk_ovl_crc_cnt,
+ .crc_entry = mtk_ovl_crc_entry,
+ .crc_read = mtk_ovl_crc_read,
+ .crc_start = mtk_ovl_crc_start,
+ .crc_stop = mtk_ovl_crc_stop,
.start = mtk_ovl_start,
.stop = mtk_ovl_stop,
.register_vblank_cb = mtk_ovl_register_vblank_cb,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 082ac18fe04a..a03d7a10847a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -105,6 +105,11 @@ void mtk_ovl_enable_vblank(struct device *dev);
void mtk_ovl_disable_vblank(struct device *dev);
const u32 *mtk_ovl_get_formats(struct device *dev);
size_t mtk_ovl_get_num_formats(struct device *dev);
+size_t mtk_ovl_crc_cnt(struct device *dev);
+u32 *mtk_ovl_crc_entry(struct device *dev);
+void mtk_ovl_crc_read(struct device *dev);
+void mtk_ovl_crc_start(struct device *dev);
+void mtk_ovl_crc_stop(struct device *dev);
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex);
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index de1633988921..d77b25c528ea 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -24,12 +24,20 @@
#define OVL_FME_CPL_INT BIT(1)
#define DISP_REG_OVL_INTSTA 0x0008
#define DISP_REG_OVL_EN 0x000c
+#define OVL_EN BIT(0)
+#define OVL_OP_8BIT_MODE BIT(4)
+#define OVL_HG_FOVL_CK_ON BIT(8)
+#define OVL_HF_FOVL_CK_ON BIT(10)
+#define DISP_REG_OVL_TRIG 0x0010
+#define OVL_CRC_EN BIT(8)
+#define OVL_CRC_CLR BIT(9)
#define DISP_REG_OVL_RST 0x0014
#define DISP_REG_OVL_ROI_SIZE 0x0020
#define DISP_REG_OVL_DATAPATH_CON 0x0024
#define OVL_LAYER_SMI_ID_EN BIT(0)
#define OVL_BGCLR_SEL_IN BIT(2)
#define OVL_LAYER_AFBC_EN(n) BIT(4+n)
+#define OVL_OUTPUT_CLAMP BIT(26)
#define DISP_REG_OVL_ROI_BGCLR 0x0028
#define DISP_REG_OVL_SRC_CON 0x002c
#define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
@@ -42,7 +50,26 @@
#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
#define DISP_REG_OVL_ADDR_MT2701 0x0040
+#define DISP_REG_OVL_CRC 0x0270
+#define OVL_CRC_OUT_MASK GENMASK(30, 0)
#define DISP_REG_OVL_CLRFMT_EXT 0x02D0
+#define DISP_REG_OVL_CLRFMT_EXT1 0x02D8
+#define OVL_CLRFMT_EXT1_CSC_EN(n) (1 << (((n) * 4) + 1))
+#define DISP_REG_OVL_Y2R_PARA_R0(n) (0x0134 + 0x28 * (n))
+#define OVL_Y2R_PARA_C_CF_RMY (GENMASK(14, 0))
+#define DISP_REG_OVL_Y2R_PARA_G0(n) (0x013c + 0x28 * (n))
+#define OVL_Y2R_PARA_C_CF_GMU (GENMASK(30, 16))
+#define DISP_REG_OVL_Y2R_PARA_B1(n) (0x0148 + 0x28 * (n))
+#define OVL_Y2R_PARA_C_CF_BMV (GENMASK(14, 0))
+#define DISP_REG_OVL_Y2R_PARA_YUV_A_0(n) (0x014c + 0x28 * (n))
+#define OVL_Y2R_PARA_C_CF_YA (GENMASK(10, 0))
+#define OVL_Y2R_PARA_C_CF_UA (GENMASK(26, 16))
+#define DISP_REG_OVL_Y2R_PARA_YUV_A_1(n) (0x0150 + 0x28 * (n))
+#define OVL_Y2R_PARA_C_CF_VA (GENMASK(10, 0))
+#define DISP_REG_OVL_Y2R_PRE_ADD2(n) (0x0154 + 0x28 * (n))
+#define DISP_REG_OVL_R2R_R0(n) (0x0500 + 0x40 * (n))
+#define DISP_REG_OVL_R2R_G1(n) (0x0510 + 0x40 * (n))
+#define DISP_REG_OVL_R2R_B2(n) (0x0520 + 0x40 * (n))
#define DISP_REG_OVL_ADDR_MT8173 0x0f40
#define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
#define DISP_REG_OVL_HDR_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n) + 0x04)
@@ -55,6 +82,8 @@
#define OVL_CON_CLRFMT_MAN BIT(23)
#define OVL_CON_BYTE_SWAP BIT(24)
#define OVL_CON_RGB_SWAP BIT(25)
+#define OVL_CON_MTX_AUTO_DIS BIT(26)
+#define OVL_CON_MTX_EN BIT(27)
#define OVL_CON_CLRFMT_RGB (1 << 12)
#define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
#define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
@@ -62,6 +91,7 @@
#define OVL_CON_CLRFMT_YUYV (5 << 12)
#define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_CLRFMT_MAN)
+#define OVL_CON_MTX_PROGRAMMABLE (8 << 16)
#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
0 : OVL_CON_CLRFMT_RGB)
#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
@@ -131,6 +161,10 @@ static const u32 mt8195_formats[] = {
DRM_FORMAT_YUYV,
};
+static const u32 mt8195_ovl_crc_ofs[] = {
+ DISP_REG_OVL_CRC,
+};
+
struct mtk_disp_ovl_data {
unsigned int addr;
unsigned int gmc_bits;
@@ -141,12 +175,15 @@ struct mtk_disp_ovl_data {
const u32 *formats;
size_t num_formats;
bool supports_clrfmt_ext;
+ const u32 *crc_ofs;
+ size_t crc_cnt;
};
/*
* struct mtk_disp_ovl - DISP_OVL driver structure
* @crtc: associated crtc to report vblank events to
* @data: platform data
+ * @crc: crc related information
*/
struct mtk_disp_ovl {
struct drm_crtc *crtc;
@@ -156,8 +193,49 @@ struct mtk_disp_ovl {
const struct mtk_disp_ovl_data *data;
void (*vblank_cb)(void *data);
void *vblank_cb_data;
+ resource_size_t regs_pa;
+ struct mtk_crtc_crc crc;
};
+size_t mtk_ovl_crc_cnt(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+ return ovl->crc.cnt;
+}
+
+u32 *mtk_ovl_crc_entry(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+ return ovl->crc.va;
+}
+
+void mtk_ovl_crc_read(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+ mtk_crtc_read_crc(&ovl->crc, ovl->regs);
+}
+
+void mtk_ovl_crc_start(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ mtk_crtc_start_crc_cmdq(&ovl->crc);
+#endif
+}
+
+void mtk_ovl_crc_stop(struct device *dev)
+{
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ mtk_crtc_stop_crc_cmdq(&ovl->crc);
+#endif
+}
+
static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
{
struct mtk_disp_ovl *priv = dev_id;
@@ -237,15 +315,27 @@ void mtk_ovl_clk_disable(struct device *dev)
void mtk_ovl_start(struct device *dev)
{
struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+ unsigned int reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
- if (ovl->data->smi_id_en) {
- unsigned int reg;
+ if (ovl->data->smi_id_en)
+ reg |= OVL_LAYER_SMI_ID_EN;
- reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
- reg = reg | OVL_LAYER_SMI_ID_EN;
- writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
+ /*
+ * When doing Y2R conversion, it's common to get an output
+ * that is larger than 10 bits (negative numbers).
+ * Enable this bit to clamp the output to 10 bits per channel
+ * (should always be enabled)
+ */
+ reg |= OVL_OUTPUT_CLAMP;
+ writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
+
+ reg = OVL_EN;
+ if (ovl->data->crc_cnt) {
+ /* enable crc and its related clocks */
+ writel_relaxed(OVL_CRC_EN, ovl->regs + DISP_REG_OVL_TRIG);
+ reg |= OVL_OP_8BIT_MODE | OVL_HG_FOVL_CK_ON | OVL_HF_FOVL_CK_ON;
}
- writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
+ writel_relaxed(reg, ovl->regs + DISP_REG_OVL_EN);
}
void mtk_ovl_stop(struct device *dev)
@@ -489,6 +579,83 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
(state->base.fb && !state->base.fb->format->has_alpha))
ignore_pixel_alpha = OVL_CONST_BLEND;
+ /*
+ * OVL only supports 8 bits data in CRC calculation, transform 10-bit
+ * RGB to 8-bit RGB by leveraging the ability of the Y2R (YUV-to-RGB)
+ * hardware to multiply coefficients, although there is nothing to do
+ * with the YUV format.
+ */
+ if (ovl->data->supports_clrfmt_ext) {
+ u32 y2r_coef = 0, y2r_offset = 0, r2r_coef = 0, csc_en = 0;
+
+ if (is_10bit_rgb(fmt)) {
+ con |= OVL_CON_MTX_AUTO_DIS | OVL_CON_MTX_EN | OVL_CON_MTX_PROGRAMMABLE;
+
+ /*
+ * Y2R coefficient setting
+ * bit 13 is 2^1, bit 12 is 2^0, bit 11 is 2^-1,
+ * bit 10 is 2^-2 = 0.25
+ */
+ y2r_coef = BIT(10);
+
+ /* -1 in 10bit */
+ y2r_offset = GENMASK(10, 0) - 1;
+
+ /*
+ * R2R coefficient setting
+ * bit 19 is 2^1, bit 18 is 2^0, bit 17 is 2^-1,
+ * bit 20 is 2^2 = 4
+ */
+ r2r_coef = BIT(20);
+
+ /* CSC_EN is for R2R */
+ csc_en = OVL_CLRFMT_EXT1_CSC_EN(idx);
+
+ /*
+ * 1. YUV input data - 1 and shift right for 2 bits to remove it
+ * [R'] [0.25 0 0] [Y in - 1]
+ * [G'] = [ 0 0.25 0] * [U in - 1]
+ * [B'] [ 0 0 0.25] [V in - 1]
+ *
+ * 2. shift left for 2 bit letting the last 2 bits become 0
+ * [R out] [ 4 0 0] [R']
+ * [G out] = [ 0 4 0] * [G']
+ * [B out] [ 0 0 4] [B']
+ */
+ }
+
+ mtk_ddp_write_mask(cmdq_pkt, y2r_coef,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_R0(idx),
+ OVL_Y2R_PARA_C_CF_RMY);
+ mtk_ddp_write_mask(cmdq_pkt, (y2r_coef << 16),
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_G0(idx),
+ OVL_Y2R_PARA_C_CF_GMU);
+ mtk_ddp_write_mask(cmdq_pkt, y2r_coef,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_B1(idx),
+ OVL_Y2R_PARA_C_CF_BMV);
+
+ mtk_ddp_write_mask(cmdq_pkt, y2r_offset,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx),
+ OVL_Y2R_PARA_C_CF_YA);
+ mtk_ddp_write_mask(cmdq_pkt, (y2r_offset << 16),
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx),
+ OVL_Y2R_PARA_C_CF_UA);
+ mtk_ddp_write_mask(cmdq_pkt, y2r_offset,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_1(idx),
+ OVL_Y2R_PARA_C_CF_VA);
+
+ mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_R0(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_G1(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_B2(idx));
+
+ mtk_ddp_write_mask(cmdq_pkt, csc_en,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT1,
+ OVL_CLRFMT_EXT1_CSC_EN(idx));
+ }
+
if (pending->rotation & DRM_MODE_REFLECT_Y) {
con |= OVL_CON_VIRT_FLIP;
addr += (pending->height - 1) * pending->pitch;
@@ -595,15 +762,31 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
dev_err(dev, "failed to ioremap ovl\n");
return PTR_ERR(priv->regs);
}
+
+ priv->data = of_device_get_match_data(dev);
+ platform_set_drvdata(pdev, priv);
+
+ if (priv->data->crc_cnt) {
+ mtk_crtc_init_crc(&priv->crc,
+ priv->data->crc_ofs, priv->data->crc_cnt,
+ DISP_REG_OVL_TRIG, OVL_CRC_CLR);
+ }
+
#if IS_REACHABLE(CONFIG_MTK_CMDQ)
ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
-#endif
-
- priv->data = of_device_get_match_data(dev);
- platform_set_drvdata(pdev, priv);
+ if (priv->data->crc_cnt) {
+ if (of_property_read_u32_index(dev->of_node,
+ "mediatek,gce-events", 0,
+ &priv->crc.cmdq_event)) {
+ dev_warn(dev, "failed to get gce-events for crc\n");
+ }
+ priv->crc.cmdq_reg = &priv->cmdq_reg;
+ mtk_crtc_create_crc_cmdq(dev, &priv->crc);
+ }
+#endif
ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
IRQF_TRIGGER_NONE, dev_name(dev), priv);
if (ret < 0) {
@@ -624,6 +807,10 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
static void mtk_disp_ovl_remove(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
+
+ mtk_crtc_destroy_crc(&ovl->crc);
component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
pm_runtime_disable(&pdev->dev);
}
@@ -694,6 +881,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
.formats = mt8195_formats,
.num_formats = ARRAY_SIZE(mt8195_formats),
.supports_clrfmt_ext = true,
+ .crc_ofs = mt8195_ovl_crc_ofs,
+ .crc_cnt = ARRAY_SIZE(mt8195_ovl_crc_ofs),
};
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Support "Pre-multiplied" and "None" blend mode on MediaTek's chips by
adding correct blend mode property when the planes init.
Before this patch, only the "Coverage" mode (default) is supported.
For more information, there are three pixel blend modes in DRM driver:
"None", "Pre-multiplied", and "Coverage".
To understand the difference between these modes, let's take a look at
the following two approaches to do alpha blending:
1. Straight:
dst.RGB = src.RGB * src.A + dst.RGB * (1 - src.A)
This is straightforward and easy to understand, when the source layer is
compositing with the destination layer, it's alpha will affect the
result. This is also known as "post-multiplied", or "Coverage" mode.
2. Pre-multiplied:
dst.RGB = src.RGB + dst.RGB * (1 - src.A)
Since the source RGB have already multiplied its alpha, only destination
RGB need to multiply it. This is the "Pre-multiplied" mode in DRM.
For the "None" blend mode in DRM, it means the pixel alpha is ignored
when compositing the layers, only the constant alpha for the composited
layer will take effects.
Reviewed-by: CK Hu <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_plane.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_plane.c b/drivers/gpu/drm/mediatek/mtk_plane.c
index 1723d4333f37..5bf757a3ef20 100644
--- a/drivers/gpu/drm/mediatek/mtk_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_plane.c
@@ -346,6 +346,17 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
DRM_INFO("Create rotation property failed\n");
}
+ err = drm_plane_create_alpha_property(plane);
+ if (err)
+ DRM_ERROR("failed to create property: alpha\n");
+
+ err = drm_plane_create_blend_mode_property(plane,
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE) |
+ BIT(DRM_MODE_BLEND_PIXEL_NONE));
+ if (err)
+ DRM_ERROR("failed to create property: blend_mode\n");
+
drm_plane_helper_add(plane, &mtk_plane_helper_funcs);
return 0;
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
We choose Mixer as CRC generator in OVL adaptor since
its frame done event will trigger vblanks, we can know
when is safe to retrieve CRC of the frame.
In OVL adaptor, there's no image procession after Mixer,
unlike the OVL in VDOSYS0, Mixer's CRC will include all
the effects that are applied to the frame.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 5 ++
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 5 ++
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 35 +++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.c | 72 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ethdr.h | 7 ++
5 files changed, 124 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 07c3b5c5e14e..473460ab3a7a 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -408,6 +408,11 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
.clk_enable = mtk_ovl_adaptor_clk_enable,
.clk_disable = mtk_ovl_adaptor_clk_disable,
.config = mtk_ovl_adaptor_config,
+ .crc_cnt = mtk_ovl_adaptor_crc_cnt,
+ .crc_entry = mtk_ovl_adaptor_crc_entry,
+ .crc_read = mtk_ovl_adaptor_crc_read,
+ .crc_start = mtk_ovl_adaptor_crc_start,
+ .crc_stop = mtk_ovl_adaptor_crc_stop,
.start = mtk_ovl_adaptor_start,
.stop = mtk_ovl_adaptor_stop,
.layer_nr = mtk_ovl_adaptor_layer_nr,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index a03d7a10847a..0ef32bc3b996 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -140,6 +140,11 @@ const u32 *mtk_ovl_adaptor_get_formats(struct device *dev);
size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
const struct drm_display_mode *mode);
+size_t mtk_ovl_adaptor_crc_cnt(struct device *dev);
+u32 *mtk_ovl_adaptor_crc_entry(struct device *dev);
+void mtk_ovl_adaptor_crc_read(struct device *dev);
+void mtk_ovl_adaptor_crc_start(struct device *dev);
+void mtk_ovl_adaptor_crc_stop(struct device *dev);
void mtk_rdma_bypass_shadow(struct device *dev);
int mtk_rdma_clk_enable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 2b62d6475918..02a617ac8265 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -207,6 +207,41 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
}
+size_t mtk_ovl_adaptor_crc_cnt(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ return mtk_ethdr_crc_cnt(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+u32 *mtk_ovl_adaptor_crc_entry(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ return mtk_ethdr_crc_entry(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_crc_read(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_crc_read(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_crc_start(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_crc_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
+void mtk_ovl_adaptor_crc_stop(struct device *dev)
+{
+ struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
+
+ mtk_ethdr_crc_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);
+}
+
void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index d01f65819816..1e6a51979ec6 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -25,6 +25,9 @@
#define MIX_FME_CPL_INTEN BIT(1)
#define MIX_INTSTA 0x8
#define MIX_EN 0xc
+#define MIX_TRIG 0x10
+#define MIX_TRIG_CRC_EN BIT(8)
+#define MIX_TRIG_CRC_RST BIT(9)
#define MIX_RST 0x14
#define MIX_ROI_SIZE 0x18
#define MIX_DATAPATH_CON 0x1c
@@ -40,6 +43,11 @@
#define PREMULTI_SOURCE (3 << 12)
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
+
+/* CRC register offsets for odd and even lines */
+#define MIX_CRC_ODD 0x110
+#define MIX_CRC_EVEN 0x114
+
#define MIX_FUNC_DCM0 0x120
#define MIX_FUNC_DCM1 0x124
#define MIX_FUNC_DCM_ENABLE 0xffffffff
@@ -83,6 +91,7 @@ struct mtk_ethdr {
void *vblank_cb_data;
int irq;
struct reset_control *reset_ctl;
+ struct mtk_crtc_crc crc;
};
static const char * const ethdr_clk_str[] = {
@@ -101,6 +110,50 @@ static const char * const ethdr_clk_str[] = {
"vdo_be_async",
};
+static const u32 ethdr_crc_ofs[] = {
+ MIX_CRC_ODD,
+ MIX_CRC_EVEN,
+};
+
+size_t mtk_ethdr_crc_cnt(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ return priv->crc.cnt;
+}
+
+u32 *mtk_ethdr_crc_entry(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ return priv->crc.va;
+}
+
+void mtk_ethdr_crc_read(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+ mtk_crtc_read_crc(&priv->crc, priv->ethdr_comp[ETHDR_MIXER].regs);
+}
+
+void mtk_ethdr_crc_start(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ mtk_crtc_start_crc_cmdq(&priv->crc);
+#endif
+}
+
+void mtk_ethdr_crc_stop(struct device *dev)
+{
+ struct mtk_ethdr *priv = dev_get_drvdata(dev);
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ mtk_crtc_stop_crc_cmdq(&priv->crc);
+#endif
+}
+
void mtk_ethdr_register_vblank_cb(struct device *dev,
void (*vblank_cb)(void *),
void *vblank_cb_data)
@@ -259,6 +312,9 @@ void mtk_ethdr_start(struct device *dev)
struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
writel(1, mixer->regs + MIX_EN);
+
+ if (priv->crc.cnt)
+ writel(MIX_TRIG_CRC_EN, mixer->regs + MIX_TRIG);
}
void mtk_ethdr_stop(struct device *dev)
@@ -320,6 +376,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
+ mtk_crtc_init_crc(&priv->crc, ethdr_crc_ofs, ARRAY_SIZE(ethdr_crc_ofs),
+ MIX_TRIG, MIX_TRIG_CRC_RST);
+
for (i = 0; i < ETHDR_ID_MAX; i++) {
priv->ethdr_comp[i].dev = dev;
priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
@@ -328,6 +387,16 @@ static int mtk_ethdr_probe(struct platform_device *pdev)
&priv->ethdr_comp[i].cmdq_base, i);
if (ret)
dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+
+ if (i == ETHDR_MIXER) {
+ if (of_property_read_u32_index(dev->of_node,
+ "mediatek,gce-events", i,
+ &priv->crc.cmdq_event)) {
+ dev_warn(dev, "failed to get gce-events for crc\n");
+ }
+ priv->crc.cmdq_reg = &priv->ethdr_comp[i].cmdq_base;
+ mtk_crtc_create_crc_cmdq(dev, &priv->crc);
+ }
#endif
dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i);
}
@@ -368,6 +437,9 @@ static int mtk_ethdr_probe(struct platform_device *pdev)
static void mtk_ethdr_remove(struct platform_device *pdev)
{
+ struct mtk_ethdr *priv = dev_get_drvdata(&pdev->dev);
+
+ mtk_crtc_destroy_crc(&priv->crc);
component_del(&pdev->dev, &mtk_ethdr_component_ops);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.h b/drivers/gpu/drm/mediatek/mtk_ethdr.h
index 81af9edea3f7..6c479c460ac0 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.h
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.h
@@ -22,4 +22,11 @@ void mtk_ethdr_register_vblank_cb(struct device *dev,
void mtk_ethdr_unregister_vblank_cb(struct device *dev);
void mtk_ethdr_enable_vblank(struct device *dev);
void mtk_ethdr_disable_vblank(struct device *dev);
+
+size_t mtk_ethdr_crc_cnt(struct device *dev);
+u32 *mtk_ethdr_crc_entry(struct device *dev);
+void mtk_ethdr_crc_read(struct device *dev);
+void mtk_ethdr_crc_start(struct device *dev);
+void mtk_ethdr_crc_stop(struct device *dev);
+
#endif
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
We found that IGT (Intel GPU Tool) will try to commit layers with
zero width or height and lead to undefined behaviors in hardware.
Disable the layers in such a situation.
Fixes: 777b7bc86a0a ("UPSTREAM: drm/mediatek: Add ovl_adaptor support for MT8195")
Fixes: fa97fe71f6f9 ("UPSTREAM: drm/mediatek: Add ETHDR support for MT8195")
Reviewed-by: CK Hu <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +-
drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 ++++++-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 02dd7dcdfedb..2b62d6475918 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -158,7 +158,7 @@ void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
- if (!pending->enable) {
+ if (!pending->enable || !pending->width || !pending->height) {
mtk_merge_stop_cmdq(merge, cmdq_pkt);
mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index 156c6ff547e8..4ffd0a064861 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
if (idx >= 4)
return;
- if (!pending->enable) {
+ if (!pending->enable || !pending->width || !pending->height) {
+ /*
+ * instead of disabling layer with MIX_SRC_CON directly
+ * set the size to 0 to avoid screen shift due to mixer
+ * mode switch (hardware behavior)
+ */
mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
return;
}
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Support "None" alpha blending mode on MediaTek's chips.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_ethdr.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index 4ffd0a064861..bcced62e455d 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -3,6 +3,7 @@
* Copyright (c) 2021 MediaTek Inc.
*/
+#include <drm/drm_blend.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
#include <linux/clk.h>
@@ -154,6 +155,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
unsigned int align_width = ALIGN_DOWN(pending->width, 2);
unsigned int alpha_con = 0;
+ bool replace_src_a = false;
dev_dbg(dev, "%s+ idx:%d", __func__, idx);
@@ -173,8 +175,16 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
if (state->base.fb && state->base.fb->format->has_alpha)
alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
- mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true,
- DEFAULT_9BIT_ALPHA,
+ if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
+ (state->base.fb && !state->base.fb->format->has_alpha)) {
+ /*
+ * Mixer doesn't support CONST_BLD mode,
+ * use a trick to make the output equivalent
+ */
+ replace_src_a = true;
+ }
+
+ mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA,
pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Support "None" alpha blending mode on MediaTek's chips.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 738244a6164e..54a6f11aa867 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -38,6 +38,7 @@
#define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
#define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
#define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
+#define OVL_CONST_BLEND BIT(28)
#define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
#define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
#define DISP_REG_OVL_ADDR_MT2701 0x0040
@@ -428,6 +429,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
unsigned int fmt = pending->format;
unsigned int offset = (pending->y << 16) | pending->x;
unsigned int src_size = (pending->height << 16) | pending->width;
+ unsigned int blend_mode = state->base.pixel_blend_mode;
+ unsigned int ignore_pixel_alpha = 0;
unsigned int con;
bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
union overlay_pitch {
@@ -449,6 +452,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
+ /* CONST_BLD must be enabled for XRGB formats although the alpha channel
+ * can be ignored, or OVL will still read the value from memory.
+ * For RGB888 related formats, whether CONST_BLD is enabled or not won't
+ * affect the result. Therefore we use !has_alpha as the condition.
+ */
+ if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
+ (state->base.fb && !state->base.fb->format->has_alpha))
+ ignore_pixel_alpha = OVL_CONST_BLEND;
+
if (pending->rotation & DRM_MODE_REFLECT_Y) {
con |= OVL_CON_VIRT_FLIP;
addr += (pending->height - 1) * pending->pitch;
@@ -464,8 +476,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_CON(idx));
- mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
- DISP_REG_OVL_PITCH(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
+ &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_SRC_SIZE(idx));
mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Register CRC related function pointers to support
CRC retrieval.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 280 ++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_crtc.h | 38 ++++
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 5 +
3 files changed, 323 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 6f34f573e127..be7cf61b9f9b 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -18,6 +18,7 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
+#include <drm/drm_vblank_work.h>
#include "mtk_crtc.h"
#include "mtk_ddp_comp.h"
@@ -69,6 +70,9 @@ struct mtk_crtc {
/* lock for display hardware access */
struct mutex hw_lock;
bool config_updating;
+
+ struct mtk_ddp_comp *crc_provider;
+ struct drm_vblank_work crc_work;
};
struct mtk_crtc_state {
@@ -703,6 +707,88 @@ static void mtk_crtc_update_output(struct drm_crtc *crtc,
}
}
+static void mtk_crtc_crc_work(struct kthread_work *base)
+{
+ struct drm_vblank_work *work = to_drm_vblank_work(base);
+ struct mtk_crtc *mtk_crtc =
+ container_of(work, typeof(*mtk_crtc), crc_work);
+ struct mtk_ddp_comp *comp = mtk_crtc->crc_provider;
+
+ if (!comp) {
+ DRM_WARN("%s(crtc-%d): no crc provider\n",
+ __func__, drm_crtc_index(&mtk_crtc->base));
+ return;
+ }
+
+ if (mtk_crtc->base.crc.opened) {
+ u64 vblank = drm_crtc_vblank_count(&mtk_crtc->base);
+
+ comp->funcs->crc_read(comp->dev);
+
+ /* could take more than 50ms to finish */
+ drm_crtc_add_crc_entry(&mtk_crtc->base, true, vblank,
+ comp->funcs->crc_entry(comp->dev));
+
+ drm_vblank_work_schedule(&mtk_crtc->crc_work, vblank + 1, true);
+ } else {
+ comp->funcs->crc_stop(comp->dev);
+ }
+}
+
+static int mtk_crtc_set_crc_source(struct drm_crtc *crtc, const char *src)
+{
+ struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_ddp_comp *comp = mtk_crtc->crc_provider;
+
+ if (!comp) {
+ DRM_ERROR("%s(crtc-%d): no crc provider\n",
+ __func__, drm_crtc_index(crtc));
+ return -ENOENT;
+ }
+
+ if (!src)
+ return -EINVAL;
+
+ if (strcmp(src, "auto") != 0) {
+ DRM_ERROR("%s(crtc-%d): unknown source '%s'\n",
+ __func__, drm_crtc_index(crtc), src);
+ return -EINVAL;
+ }
+
+ comp->funcs->crc_start(comp->dev);
+
+ /*
+ * skip the first crc because the first frame (vblank + 1) is configured
+ * by mtk_crtc_ddp_hw_init() when atomic enable
+ */
+ drm_vblank_work_schedule(&mtk_crtc->crc_work,
+ drm_crtc_vblank_count(crtc) + 2, false);
+ return 0;
+}
+
+static int mtk_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src,
+ size_t *cnt)
+{
+ struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_ddp_comp *comp = mtk_crtc->crc_provider;
+
+ if (!comp) {
+ DRM_ERROR("%s(crtc-%d): no crc provider\n",
+ __func__, drm_crtc_index(crtc));
+ return -ENOENT;
+ }
+
+ if (src && strcmp(src, "auto") != 0) {
+ DRM_ERROR("%s(crtc-%d): unknown source '%s'\n",
+ __func__, drm_crtc_index(crtc), src);
+ return -EINVAL;
+ }
+
+ *cnt = comp->funcs->crc_cnt(comp->dev);
+
+ return 0;
+}
+
int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
struct mtk_plane_state *state)
{
@@ -751,6 +837,8 @@ static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
drm_crtc_vblank_on(crtc);
mtk_crtc->enabled = true;
+
+ drm_vblank_work_init(&mtk_crtc->crc_work, crtc, mtk_crtc_crc_work);
}
static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
@@ -840,6 +928,8 @@ static const struct drm_crtc_funcs mtk_crtc_funcs = {
.atomic_destroy_state = mtk_crtc_destroy_state,
.enable_vblank = mtk_crtc_enable_vblank,
.disable_vblank = mtk_crtc_disable_vblank,
+ .set_crc_source = mtk_crtc_set_crc_source,
+ .verify_crc_source = mtk_crtc_verify_crc_source,
};
static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
@@ -1033,6 +1123,13 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
if (comp->funcs->ctm_set)
has_ctm = true;
+
+ if (comp->funcs->crc_cnt &&
+ comp->funcs->crc_entry &&
+ comp->funcs->crc_read &&
+ comp->funcs->crc_start &&
+ comp->funcs->crc_stop)
+ mtk_crtc->crc_provider = comp;
}
mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
@@ -1136,3 +1233,186 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
return 0;
}
+
+void mtk_crtc_init_crc(struct mtk_crtc_crc *crc, const u32 *crc_offset_table,
+ size_t crc_count, u32 reset_offset, u32 reset_mask)
+{
+ crc->ofs = crc_offset_table;
+ crc->cnt = crc_count;
+ crc->rst_ofs = reset_offset;
+ crc->rst_msk = reset_mask;
+ crc->va = kcalloc(crc->cnt, sizeof(*crc->va), GFP_KERNEL);
+ if (!crc->va) {
+ DRM_ERROR("failed to allocate memory for crc\n");
+ crc->cnt = 0;
+ }
+}
+
+void mtk_crtc_read_crc(struct mtk_crtc_crc *crc, void __iomem *reg)
+{
+ if (!crc->cnt || !crc->ofs || !crc->va)
+ return;
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ /* sync to see the most up-to-date copy of the DMA buffer */
+ dma_sync_single_for_cpu(crc->cmdq_client.chan->mbox->dev,
+ crc->pa, crc->cnt * sizeof(*crc->va),
+ DMA_FROM_DEVICE);
+#endif
+}
+
+void mtk_crtc_destroy_crc(struct mtk_crtc_crc *crc)
+{
+ if (!crc->cnt)
+ return;
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ if (crc->pa) {
+ dma_unmap_single(crc->cmdq_client.chan->mbox->dev,
+ crc->pa, crc->cnt * sizeof(*crc->va),
+ DMA_TO_DEVICE);
+ crc->pa = 0;
+ }
+ if (crc->cmdq_client.chan) {
+ mtk_drm_cmdq_pkt_destroy(&crc->cmdq_handle);
+ mbox_free_channel(crc->cmdq_client.chan);
+ crc->cmdq_client.chan = NULL;
+ }
+#endif
+ kfree(crc->va);
+ crc->va = NULL;
+ crc->cnt = 0;
+}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+/**
+ * mtk_crtc_create_crc_cmdq - Create a CMDQ thread for syncing the CRCs
+ * @dev: Kernel device node of the CRC provider
+ * @crc: Pointer of the CRC to init
+ *
+ * This function will create a looping thread on GCE (Global Command Engine) to
+ * keep the CRC up to date by monitoring the assigned event (usually the frame
+ * done event) of the CRC provider, and read the CRCs from the registers to a
+ * shared memory for the workqueue to read. To start/stop the looping thread,
+ * please call `mtk_crtc_start_crc_cmdq()` and `mtk_crtc_stop_crc_cmdq()`
+ * defined blow.
+ *
+ * The reason why we don't update the CRCs with CPU is that the front porch of
+ * 4K60 timing in CEA-861 is less than 60us, and register read/write speed is
+ * relatively unreliable comparing to GCE due to the bus design.
+ *
+ * We must create a new thread instead of using the original one for plane
+ * update is because:
+ * 1. We cannot add another wait-for-event command at the end of cmdq packet, or
+ * the cmdq callback will delay for too long
+ * 2. Will get the CRC of the previous frame if using the existed wait-for-event
+ * command which is at the beginning of the packet
+ */
+void mtk_crtc_create_crc_cmdq(struct device *dev, struct mtk_crtc_crc *crc)
+{
+ int i;
+
+ if (!crc->cnt) {
+ dev_warn(dev, "%s: not support\n", __func__);
+ goto cleanup;
+ }
+
+ if (!crc->ofs) {
+ dev_warn(dev, "%s: not defined\n", __func__);
+ goto cleanup;
+ }
+
+ crc->cmdq_client.client.dev = dev;
+ crc->cmdq_client.client.tx_block = false;
+ crc->cmdq_client.client.knows_txdone = true;
+ crc->cmdq_client.client.rx_callback = NULL;
+ crc->cmdq_client.chan = mbox_request_channel(&crc->cmdq_client.client, 0);
+ if (IS_ERR(crc->cmdq_client.chan)) {
+ dev_warn(dev, "%s: failed to create mailbox client\n", __func__);
+ crc->cmdq_client.chan = NULL;
+ goto cleanup;
+ }
+
+ if (mtk_drm_cmdq_pkt_create(&crc->cmdq_client, &crc->cmdq_handle, PAGE_SIZE)) {
+ dev_warn(dev, "%s: failed to create cmdq packet\n", __func__);
+ goto cleanup;
+ }
+
+ if (!crc->va) {
+ dev_warn(dev, "%s: no memory\n", __func__);
+ goto cleanup;
+ }
+
+ /* map the entry to get a dma address for cmdq to store the crc */
+ crc->pa = dma_map_single(crc->cmdq_client.chan->mbox->dev,
+ crc->va, crc->cnt * sizeof(*crc->va),
+ DMA_FROM_DEVICE);
+
+ if (dma_mapping_error(crc->cmdq_client.chan->mbox->dev, crc->pa)) {
+ dev_err(dev, "%s: failed to map dma\n", __func__);
+ goto cleanup;
+ }
+
+ if (crc->cmdq_event)
+ cmdq_pkt_wfe(&crc->cmdq_handle, crc->cmdq_event, true);
+
+ for (i = 0; i < crc->cnt; i++) {
+ /* put crc to spr1 register */
+ cmdq_pkt_read_s(&crc->cmdq_handle, crc->cmdq_reg->subsys,
+ crc->cmdq_reg->offset + crc->ofs[i],
+ CMDQ_THR_SPR_IDX1);
+
+ /* copy spr1 register to physical address of the crc */
+ cmdq_pkt_assign(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0,
+ CMDQ_ADDR_HIGH(crc->pa + i * sizeof(*crc->va)));
+ cmdq_pkt_write_s(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0,
+ CMDQ_ADDR_LOW(crc->pa + i * sizeof(*crc->va)),
+ CMDQ_THR_SPR_IDX1);
+ }
+ /* reset crc */
+ mtk_ddp_write_mask(&crc->cmdq_handle, ~0, crc->cmdq_reg, 0,
+ crc->rst_ofs, crc->rst_msk);
+
+ /* clear reset bit */
+ mtk_ddp_write_mask(&crc->cmdq_handle, 0, crc->cmdq_reg, 0,
+ crc->rst_ofs, crc->rst_msk);
+
+ /* jump to head of the cmdq packet */
+ cmdq_pkt_jump_abs(&crc->cmdq_handle, crc->cmdq_handle.pa_base,
+ cmdq_get_shift_pa(crc->cmdq_client.chan));
+
+ return;
+cleanup:
+ mtk_crtc_destroy_crc(crc);
+}
+
+/**
+ * mtk_crtc_start_crc_cmdq - Start the GCE looping thread for CRC update
+ * @crc: Pointer of the CRC information
+ */
+void mtk_crtc_start_crc_cmdq(struct mtk_crtc_crc *crc)
+{
+ if (!crc->cmdq_client.chan)
+ return;
+
+ dma_sync_single_for_device(crc->cmdq_client.chan->mbox->dev,
+ crc->cmdq_handle.pa_base,
+ crc->cmdq_handle.cmd_buf_size,
+ DMA_TO_DEVICE);
+ mbox_send_message(crc->cmdq_client.chan, &crc->cmdq_handle);
+ mbox_client_txdone(crc->cmdq_client.chan, 0);
+}
+
+/**
+ * mtk_crtc_stop_crc_cmdq - Stop the GCE looping thread for CRC update
+ * @crc: Pointer of the CRC information
+ */
+void mtk_crtc_stop_crc_cmdq(struct mtk_crtc_crc *crc)
+{
+ if (!crc->cmdq_client.chan)
+ return;
+
+ /* remove all the commands from the cmdq packet */
+ mbox_flush(crc->cmdq_client.chan, 2000);
+}
+#endif
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek/mtk_crtc.h
index 388e900b6f4d..a79c4611754e 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.h
@@ -14,6 +14,34 @@
#define MTK_MAX_BPC 10
#define MTK_MIN_BPC 3
+/**
+ * struct mtk_crtc_crc - crc related information
+ * @ofs: register offset of crc
+ * @rst_ofs: register offset of crc reset
+ * @rst_msk: register mask of crc reset
+ * @cnt: count of crc
+ * @va: pointer to the start of crc array
+ * @pa: physical address of the crc for gce to access
+ * @cmdq_event: the event to trigger the cmdq
+ * @cmdq_reg: address of the register that cmdq is going to access
+ * @cmdq_client: handler to control cmdq (mbox channel, thread ...etc.)
+ * @cmdq_handle: cmdq packet to store the commands
+ */
+struct mtk_crtc_crc {
+ const u32 *ofs;
+ u32 rst_ofs;
+ u32 rst_msk;
+ size_t cnt;
+ u32 *va;
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ dma_addr_t pa;
+ u32 cmdq_event;
+ struct cmdq_client_reg *cmdq_reg;
+ struct cmdq_client cmdq_client;
+ struct cmdq_pkt cmdq_handle;
+#endif
+};
+
void mtk_crtc_commit(struct drm_crtc *crtc);
int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
unsigned int path_len, int priv_data_index,
@@ -25,4 +53,14 @@ void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
struct drm_atomic_state *plane_state);
struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc);
+void mtk_crtc_init_crc(struct mtk_crtc_crc *crc, const u32 *crc_offset_table,
+ size_t crc_count, u32 reset_offset, u32 reset_mask);
+void mtk_crtc_read_crc(struct mtk_crtc_crc *crc, void __iomem *reg);
+void mtk_crtc_destroy_crc(struct mtk_crtc_crc *crc);
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+void mtk_crtc_create_crc_cmdq(struct device *dev, struct mtk_crtc_crc *crc);
+void mtk_crtc_start_crc_cmdq(struct mtk_crtc_crc *crc);
+void mtk_crtc_stop_crc_cmdq(struct mtk_crtc_crc *crc);
+#endif
+
#endif /* MTK_CRTC_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index f7fe2e08dc8e..b220a672d182 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -88,6 +88,11 @@ struct mtk_ddp_comp_funcs {
void (*remove)(struct device *dev, struct mtk_mutex *mutex);
unsigned int (*encoder_index)(struct device *dev);
enum drm_mode_status (*mode_valid)(struct device *dev, const struct drm_display_mode *mode);
+ size_t (*crc_cnt)(struct device *dev);
+ u32 *(*crc_entry)(struct device *dev);
+ void (*crc_read)(struct device *dev);
+ void (*crc_start)(struct device *dev);
+ void (*crc_stop)(struct device *dev);
};
struct mtk_ddp_comp {
--
2.18.0
From: Hsiao Chien Sung <[email protected]>
Support "Pre-multiplied" alpha blending mode in Mixer.
Before this patch, only the coverage mode is supported.
Signed-off-by: Hsiao Chien Sung <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
index bcced62e455d..d01f65819816 100644
--- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
+++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
@@ -6,6 +6,7 @@
#include <drm/drm_blend.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_framebuffer.h>
+#include <drm/drm_blend.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/of.h>
@@ -36,6 +37,7 @@
#define MIX_SRC_L0_EN BIT(0)
#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
#define NON_PREMULTI_SOURCE (2 << 12)
+#define PREMULTI_SOURCE (3 << 12)
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
#define MIX_FUNC_DCM0 0x120
@@ -172,8 +174,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
return;
}
- if (state->base.fb && state->base.fb->format->has_alpha)
- alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
+ alpha_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA);
+
+ if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE)
+ alpha_con |= PREMULTI_SOURCE;
+ else
+ alpha_con |= NON_PREMULTI_SOURCE;
if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
(state->base.fb && !state->base.fb->format->has_alpha)) {
@@ -191,8 +197,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
mixer->regs, MIX_L_SRC_SIZE(idx));
mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
- mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
- 0x1ff);
+ mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
BIT(idx));
}
--
2.18.0
Il 06/06/24 11:26, Shawn Sung ha scritto:
> From: Hsiao Chien Sung <[email protected]>
>
> Set DRM mode configs limitation according to the hardware capabilities
> and pass the IGT checks as below:
>
> - The test "graphics.IgtKms.kms_plane" requires a frame buffer with
> width of 4512 pixels (> 4096).
> - The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is
> defined, and run the test with cursor size from 1x1 to 512x512.
>
> Please notice that the test conditions may change as IGT is updated.
>
> Reviewed-by: CK Hu <[email protected]>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 4 ++++
> 2 files changed, 26 insertions(+)
>
..snip..
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 78d698ede1bf..6cfa790e8df5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data {
> bool shadow_register;
> unsigned int mmsys_id;
> unsigned int mmsys_dev_num;
> +
> + int max_width;
> + int min_width;
> + int min_height;
Only one nit here.
Since {min,max}_{width,height}:
- Will never be negative; and
- Will never need more than 16 bits; and
- Are local to this driver and anyway copied to drm later
Can you please change them to unsigned 16-bits (u16)?
After which,
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Cheers,
Angelo
> };
>
> struct mtk_drm_private {
Il 06/06/24 11:26, Shawn Sung ha scritto:
> From: Hsiao Chien Sung <[email protected]>
>
> Support more 10bit formats in OVL.
>
> Reviewed-by: CK Hu <[email protected]>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Hi, Shawn:
On Thu, 2024-06-06 at 17:26 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <[email protected]>
>
> Support "None" alpha blending mode on MediaTek's chips.
>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 16 ++++++++++++++--
> 1 file changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 738244a6164e..54a6f11aa867 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -38,6 +38,7 @@
> #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n))
> #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16)
> #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
> +#define OVL_CONST_BLEND BIT(28)
> #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
> #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
> #define DISP_REG_OVL_ADDR_MT2701 0x0040
> @@ -428,6 +429,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> unsigned int fmt = pending->format;
> unsigned int offset = (pending->y << 16) | pending->x;
> unsigned int src_size = (pending->height << 16) | pending->width;
> + unsigned int blend_mode = state->base.pixel_blend_mode;
> + unsigned int ignore_pixel_alpha = 0;
> unsigned int con;
> bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
> union overlay_pitch {
> @@ -449,6 +452,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> if (state->base.fb && state->base.fb->format->has_alpha)
> con |= OVL_CON_AEN | OVL_CON_ALPHA;
>
> + /* CONST_BLD must be enabled for XRGB formats although the alpha channel
> + * can be ignored, or OVL will still read the value from memory.
> + * For RGB888 related formats, whether CONST_BLD is enabled or not won't
> + * affect the result. Therefore we use !has_alpha as the condition.
> + */
This patch looks good to me, but OVL driver has already declare some X format.
So I would like to separate X format related part to a fix patch.
Regards,
CK
> + if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> + (state->base.fb && !state->base.fb->format->has_alpha))
> + ignore_pixel_alpha = OVL_CONST_BLEND;
> +
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> con |= OVL_CON_VIRT_FLIP;
> addr += (pending->height - 1) * pending->pitch;
> @@ -464,8 +476,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
>
> mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_CON(idx));
> - mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
> - DISP_REG_OVL_PITCH(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
> mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_SRC_SIZE(idx));
> mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
> --
> 2.18.0
>
Hi, Shawn:
On Thu, 2024-06-06 at 17:26 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <[email protected]>
>
> Support "None" alpha blending mode on MediaTek's chips.
>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index 4ffd0a064861..bcced62e455d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -3,6 +3,7 @@
> * Copyright (c) 2021 MediaTek Inc.
> */
>
> +#include <drm/drm_blend.h>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_framebuffer.h>
> #include <linux/clk.h>
> @@ -154,6 +155,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
> unsigned int align_width = ALIGN_DOWN(pending->width, 2);
> unsigned int alpha_con = 0;
> + bool replace_src_a = false;
>
> dev_dbg(dev, "%s+ idx:%d", __func__, idx);
>
> @@ -173,8 +175,16 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> if (state->base.fb && state->base.fb->format->has_alpha)
> alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
>
> - mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, alpha_con ? false : true,
> - DEFAULT_9BIT_ALPHA,
> + if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> + (state->base.fb && !state->base.fb->format->has_alpha)) {
> + /*
> + * Mixer doesn't support CONST_BLD mode,
> + * use a trick to make the output equivalent
> + */
> + replace_src_a = true;
> + }
> +
> + mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a, MIXER_ALPHA,
It seems originally replace source alpha with 9 bits constant alpha, but this patch change to 8 bits constant alpha.
Changing from 9 bits to 8 bits is not related to this patch, so separate it to another patch.
Regards,
CK
> pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
> MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);
>
> --
> 2.18.0
>
>
Hi, Shawn:
On Thu, 2024-06-06 at 17:26 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <[email protected]>
>
> Support "Pre-multiplied" alpha blending mode in Mixer.
> Before this patch, only the coverage mode is supported.
>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index bcced62e455d..d01f65819816 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -6,6 +6,7 @@
> #include <drm/drm_blend.h>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_framebuffer.h>
> +#include <drm/drm_blend.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/of.h>
> @@ -36,6 +37,7 @@
> #define MIX_SRC_L0_EN BIT(0)
> #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
> #define NON_PREMULTI_SOURCE (2 << 12)
> +#define PREMULTI_SOURCE (3 << 12)
> #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
> #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
> #define MIX_FUNC_DCM0 0x120
> @@ -172,8 +174,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> return;
> }
>
> - if (state->base.fb && state->base.fb->format->has_alpha)
> - alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> + alpha_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA);
This is constant alpha, not related to pre-multiplied alpha, so separate it to another patch.
Regards,
CK
> +
> + if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE)
> + alpha_con |= PREMULTI_SOURCE;
> + else
> + alpha_con |= NON_PREMULTI_SOURCE;
>
> if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> (state->base.fb && !state->base.fb->format->has_alpha)) {
> @@ -191,8 +197,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
> mixer->regs, MIX_L_SRC_SIZE(idx));
> mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> - mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> - 0x1ff);
> + mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
> mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> BIT(idx));
> }
Hi, Shawn:
On Thu, 2024-06-06 at 17:26 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <[email protected]>
>
> Register CRC related function pointers to support
> CRC retrieval.
>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
[snip]
>
> +static void mtk_crtc_crc_work(struct kthread_work *base)
> +{
> + struct drm_vblank_work *work = to_drm_vblank_work(base);
> + struct mtk_crtc *mtk_crtc =
> + container_of(work, typeof(*mtk_crtc), crc_work);
> + struct mtk_ddp_comp *comp = mtk_crtc->crc_provider;
> +
> + if (!comp) {
> + DRM_WARN("%s(crtc-%d): no crc provider\n",
> + __func__, drm_crtc_index(&mtk_crtc->base));
> + return;
> + }
> +
> + if (mtk_crtc->base.crc.opened) {
> + u64 vblank = drm_crtc_vblank_count(&mtk_crtc->base);
> +
> + comp->funcs->crc_read(comp->dev);
> +
> + /* could take more than 50ms to finish */
> + drm_crtc_add_crc_entry(&mtk_crtc->base, true, vblank,
> + comp->funcs->crc_entry(comp->dev));
It seems that you could regenerate cmdq packet for crc here. So crtc
atomic flush and crc could use the same mailbox channel.
Regards,
CK
> +
> + drm_vblank_work_schedule(&mtk_crtc->crc_work, vblank + 1, true);
> + } else {
> + comp->funcs->crc_stop(comp->dev);
> + }
> +}
> +
Hi, Shawn:
On Thu, 2024-06-06 at 17:26 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <[email protected]>
>
> We choose OVL as the CRC generator from other hardware
> components that are also capable of calculating CRCs,
> since its frame done event triggers vblanks, it can be
> used as a signal to know when is safe to retrieve CRC of
> the frame.
>
> Please note that position of the hardware component
> that is chosen as CRC generator in the display path is
> significant. For example, while OVL is the first module
> in VDOSYS0, its CRC won't be affected by the modules
> after it, which means effects applied by PQ, Gamma,
> Dither or any other components after OVL won't be
> calculated in CRC generation.
>
> Signed-off-by: Hsiao Chien Sung <[email protected]>
> ---
[snip]
>
> void mtk_ovl_stop(struct device *dev)
> @@ -489,6 +579,83 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> (state->base.fb && !state->base.fb->format->has_alpha))
> ignore_pixel_alpha = OVL_CONST_BLEND;
>
> + /*
> + * OVL only supports 8 bits data in CRC calculation, transform 10-bit
> + * RGB to 8-bit RGB by leveraging the ability of the Y2R (YUV-to-RGB)
> + * hardware to multiply coefficients, although there is nothing to do
> + * with the YUV format.
> + */
> + if (ovl->data->supports_clrfmt_ext) {
> + u32 y2r_coef = 0, y2r_offset = 0, r2r_coef = 0, csc_en = 0;
> +
> + if (is_10bit_rgb(fmt)) {
> + con |= OVL_CON_MTX_AUTO_DIS | OVL_CON_MTX_EN | OVL_CON_MTX_PROGRAMMABLE;
> +
> + /*
> + * Y2R coefficient setting
> + * bit 13 is 2^1, bit 12 is 2^0, bit 11 is 2^-1,
> + * bit 10 is 2^-2 = 0.25
> + */
> + y2r_coef = BIT(10);
> +
> + /* -1 in 10bit */
> + y2r_offset = GENMASK(10, 0) - 1;
I don't know why do this? If an input value is 0x100, then
0x100 right shit 2 bit become 0x40.
0x40 - 1 = 0x3f.
0x3f left shift 2 bit become 0xfc.
So input 0x100 and output 0xfc. Why?
> +
> + /*
> + * R2R coefficient setting
> + * bit 19 is 2^1, bit 18 is 2^0, bit 17 is 2^-1,
> + * bit 20 is 2^2 = 4
> + */
> + r2r_coef = BIT(20);
> +
> + /* CSC_EN is for R2R */
> + csc_en = OVL_CLRFMT_EXT1_CSC_EN(idx);
> +
> + /*
> + * 1. YUV input data - 1 and shift right for 2 bits to remove it
> + * [R'] [0.25 0 0] [Y in - 1]
> + * [G'] = [ 0 0.25 0] * [U in - 1]
> + * [B'] [ 0 0 0.25] [V in - 1]
> + *
> + * 2. shift left for 2 bit letting the last 2 bits become 0
You truncate the last two bit, so some quality lost. I think the
quality is main function and CRC is just for debug. So it's better that
in normal case we keep quality and only for debug to lost the quality.
I have another question. You just truncate the last two bit but it is
still 10 bit value, so CRC could calculate this 10 bit value? I don't
know why you say CRC just for 8 bit?
Regards,
CK
> + * [R out] [ 4 0 0] [R']
> + * [G out] = [ 0 4 0] * [G']
> + * [B out] [ 0 0 4] [B']
> + */
> + }
> +
> + mtk_ddp_write_mask(cmdq_pkt, y2r_coef,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_R0(idx),
> + OVL_Y2R_PARA_C_CF_RMY);
> + mtk_ddp_write_mask(cmdq_pkt, (y2r_coef << 16),
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_G0(idx),
> + OVL_Y2R_PARA_C_CF_GMU);
> + mtk_ddp_write_mask(cmdq_pkt, y2r_coef,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_B1(idx),
> + OVL_Y2R_PARA_C_CF_BMV);
> +
> + mtk_ddp_write_mask(cmdq_pkt, y2r_offset,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx),
> + OVL_Y2R_PARA_C_CF_YA);
> + mtk_ddp_write_mask(cmdq_pkt, (y2r_offset << 16),
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_0(idx),
> + OVL_Y2R_PARA_C_CF_UA);
> + mtk_ddp_write_mask(cmdq_pkt, y2r_offset,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_Y2R_PARA_YUV_A_1(idx),
> + OVL_Y2R_PARA_C_CF_VA);
> +
> + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_R0(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_G1(idx));
> + mtk_ddp_write_relaxed(cmdq_pkt, r2r_coef,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_R2R_B2(idx));
> +
> + mtk_ddp_write_mask(cmdq_pkt, csc_en,
> + &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT1,
> + OVL_CLRFMT_EXT1_CSC_EN(idx));
> + }
> +
> if (pending->rotation & DRM_MODE_REFLECT_Y) {
> con |= OVL_CON_VIRT_FLIP;
> addr += (pending->height - 1) * pending->pitch;
>
Hi Shawn,
kernel test robot noticed the following build warnings:
[auto build test WARNING on v6.10-rc2]
[also build test WARNING on linus/master next-20240613]
[cannot apply to chrome-os/chromeos-6.1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shawn-Sung/soc-mediatek-Disable-9-bit-alpha-in-ETHDR/20240606-172904
base: v6.10-rc2
patch link: https://lore.kernel.org/r/20240606092635.27981-15-shawn.sung%40mediatek.com
patch subject: [PATCH v8 14/16] drm/mediatek: Support CRC in display driver
config: arm64-randconfig-r113-20240615 (https://download.01.org/0day-ci/archive/20240616/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240616/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/mediatek/mtk_crtc.c:1373:66: sparse: sparse: Using plain integer as NULL pointer
drivers/gpu/drm/mediatek/mtk_crtc.c:1377:65: sparse: sparse: Using plain integer as NULL pointer
vim +1373 drivers/gpu/drm/mediatek/mtk_crtc.c
1286
1287 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
1288 /**
1289 * mtk_crtc_create_crc_cmdq - Create a CMDQ thread for syncing the CRCs
1290 * @dev: Kernel device node of the CRC provider
1291 * @crc: Pointer of the CRC to init
1292 *
1293 * This function will create a looping thread on GCE (Global Command Engine) to
1294 * keep the CRC up to date by monitoring the assigned event (usually the frame
1295 * done event) of the CRC provider, and read the CRCs from the registers to a
1296 * shared memory for the workqueue to read. To start/stop the looping thread,
1297 * please call `mtk_crtc_start_crc_cmdq()` and `mtk_crtc_stop_crc_cmdq()`
1298 * defined blow.
1299 *
1300 * The reason why we don't update the CRCs with CPU is that the front porch of
1301 * 4K60 timing in CEA-861 is less than 60us, and register read/write speed is
1302 * relatively unreliable comparing to GCE due to the bus design.
1303 *
1304 * We must create a new thread instead of using the original one for plane
1305 * update is because:
1306 * 1. We cannot add another wait-for-event command at the end of cmdq packet, or
1307 * the cmdq callback will delay for too long
1308 * 2. Will get the CRC of the previous frame if using the existed wait-for-event
1309 * command which is at the beginning of the packet
1310 */
1311 void mtk_crtc_create_crc_cmdq(struct device *dev, struct mtk_crtc_crc *crc)
1312 {
1313 int i;
1314
1315 if (!crc->cnt) {
1316 dev_warn(dev, "%s: not support\n", __func__);
1317 goto cleanup;
1318 }
1319
1320 if (!crc->ofs) {
1321 dev_warn(dev, "%s: not defined\n", __func__);
1322 goto cleanup;
1323 }
1324
1325 crc->cmdq_client.client.dev = dev;
1326 crc->cmdq_client.client.tx_block = false;
1327 crc->cmdq_client.client.knows_txdone = true;
1328 crc->cmdq_client.client.rx_callback = NULL;
1329 crc->cmdq_client.chan = mbox_request_channel(&crc->cmdq_client.client, 0);
1330 if (IS_ERR(crc->cmdq_client.chan)) {
1331 dev_warn(dev, "%s: failed to create mailbox client\n", __func__);
1332 crc->cmdq_client.chan = NULL;
1333 goto cleanup;
1334 }
1335
1336 if (mtk_drm_cmdq_pkt_create(&crc->cmdq_client, &crc->cmdq_handle, PAGE_SIZE)) {
1337 dev_warn(dev, "%s: failed to create cmdq packet\n", __func__);
1338 goto cleanup;
1339 }
1340
1341 if (!crc->va) {
1342 dev_warn(dev, "%s: no memory\n", __func__);
1343 goto cleanup;
1344 }
1345
1346 /* map the entry to get a dma address for cmdq to store the crc */
1347 crc->pa = dma_map_single(crc->cmdq_client.chan->mbox->dev,
1348 crc->va, crc->cnt * sizeof(*crc->va),
1349 DMA_FROM_DEVICE);
1350
1351 if (dma_mapping_error(crc->cmdq_client.chan->mbox->dev, crc->pa)) {
1352 dev_err(dev, "%s: failed to map dma\n", __func__);
1353 goto cleanup;
1354 }
1355
1356 if (crc->cmdq_event)
1357 cmdq_pkt_wfe(&crc->cmdq_handle, crc->cmdq_event, true);
1358
1359 for (i = 0; i < crc->cnt; i++) {
1360 /* put crc to spr1 register */
1361 cmdq_pkt_read_s(&crc->cmdq_handle, crc->cmdq_reg->subsys,
1362 crc->cmdq_reg->offset + crc->ofs[i],
1363 CMDQ_THR_SPR_IDX1);
1364
1365 /* copy spr1 register to physical address of the crc */
1366 cmdq_pkt_assign(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0,
1367 CMDQ_ADDR_HIGH(crc->pa + i * sizeof(*crc->va)));
1368 cmdq_pkt_write_s(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0,
1369 CMDQ_ADDR_LOW(crc->pa + i * sizeof(*crc->va)),
1370 CMDQ_THR_SPR_IDX1);
1371 }
1372 /* reset crc */
> 1373 mtk_ddp_write_mask(&crc->cmdq_handle, ~0, crc->cmdq_reg, 0,
1374 crc->rst_ofs, crc->rst_msk);
1375
1376 /* clear reset bit */
1377 mtk_ddp_write_mask(&crc->cmdq_handle, 0, crc->cmdq_reg, 0,
1378 crc->rst_ofs, crc->rst_msk);
1379
1380 /* jump to head of the cmdq packet */
1381 cmdq_pkt_jump_abs(&crc->cmdq_handle, crc->cmdq_handle.pa_base,
1382 cmdq_get_shift_pa(crc->cmdq_client.chan));
1383
1384 return;
1385 cleanup:
1386 mtk_crtc_destroy_crc(crc);
1387 }
1388
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki