Verisilicon/DC8200 display controller IP has 2 display pipes and each
pipe support a primary plane and a cursor plane .
In addition, there are four overlay planes as two display pipes common resources.
The first display pipe is bound to the inno HDMI encoder.
The second display pipe is bound to a simple encoder, which is used to
find dsi bridge by dts node.
Patch 1 adds YAML schema for JH7110 display pipeline.
Patches 2 to 3 add inno common api and match the ROCKCHIP inno hdmi driver
by calling the common api.
The collating public interface is based on ROCKCHIP inno hdmi,
and it can be resused by JH7110 inno hdmi.
Those common api are tested on rk-3128 SDK, which kernel version is 4.x.
step1, make sure the process is consistent with the latest kernel version.
step2, just remove the interface and add a common interface.
Patches 4 to 8 add kms driver for dc8200 display controller.
Patch 9 adds inno hdmi support for JH7110 display pipeline.
Patch 10 adds a simple encoder.
This patchset should be applied on next branch.
V1:
Changes since v1:
- Further standardize the yaml file.
- Dts naming convention improved.
- Fix the problem of compiling and loading ko files.
- Use drm new api to automatically manage resources.
- Drop vs_crtc_funcs&vs_plane_funcs, subdivide the plane's help interface.
- Reduce the modifiers unused.
- Optimize the hdmi driver code
V2:
Changes since v2:
- fix the error about checking the yaml file.
- match drm driver GEM DMA API.
- Delete the custom crtc property .
- hdmi use drmm_ new api to automatically manage resources.
- update the modifiers comments.
- enabling KASAN, fix the error during removing module
V3:
Changes since v3:
- Delete the custom plane property.
- Delete the custom fourcc modifiers.
- Adjust the calculation mode of hdmi pixclock.
- Add match data for dc8200 driver.
- Adjust some magic values.
- Add a simple encoder for dsi output.
V4:
Changes since v4:
- Delete the display subsystem module as all crtcs and planes are a driver.
- Delete the custom struct, directly use the drm struct data.
- Tidy up the inno hdmi public interface.
- Add a simple encoder for dsi output.
keith (10):
dt-bindings: display: Add YAML schema for JH7110 display pipeline
drm/bridge: add common api for inno hdmi
drm/rockchip:hdmi: migrate to use inno-hdmi bridge driver
drm/vs: Add hardware funcs for vs.
drm/vs: add vs mode config init
drm/vs: add vs plane api
drm/vs: add ctrc fun
drm/vs: add vs drm master driver
drm/vs: Innosilicon HDMI support
drm/vs: add simple dsi encoder
.../display/bridge/innosilicon,inno-hdmi.yaml | 49 +
.../display/rockchip/rockchip,inno-hdmi.yaml | 27 +-
.../starfive/starfive,dsi-encoder.yaml | 92 ++
.../starfive/starfive,jh7110-dc8200.yaml | 169 +++
.../starfive/starfive,jh7110-inno-hdmi.yaml | 75 ++
.../soc/starfive/starfive,jh7110-syscon.yaml | 1 +
MAINTAINERS | 11 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
.../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 +++++++++
.../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 ++
drivers/gpu/drm/rockchip/Kconfig | 1 +
drivers/gpu/drm/rockchip/Makefile | 2 +-
drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 517 ++++++++
.../{inno_hdmi.h => inno_hdmi-rockchip.h} | 45 -
drivers/gpu/drm/rockchip/inno_hdmi.c | 1073 -----------------
drivers/gpu/drm/verisilicon/Kconfig | 23 +
drivers/gpu/drm/verisilicon/Makefile | 11 +
.../gpu/drm/verisilicon/inno_hdmi-starfive.c | 481 ++++++++
.../gpu/drm/verisilicon/inno_hdmi-starfive.h | 152 +++
drivers/gpu/drm/verisilicon/vs_crtc.c | 241 ++++
drivers/gpu/drm/verisilicon/vs_crtc.h | 17 +
drivers/gpu/drm/verisilicon/vs_dc_hw.c | 1060 ++++++++++++++++
drivers/gpu/drm/verisilicon/vs_dc_hw.h | 493 ++++++++
drivers/gpu/drm/verisilicon/vs_drv.c | 721 +++++++++++
drivers/gpu/drm/verisilicon/vs_drv.h | 98 ++
drivers/gpu/drm/verisilicon/vs_modeset.c | 36 +
drivers/gpu/drm/verisilicon/vs_modeset.h | 10 +
drivers/gpu/drm/verisilicon/vs_plane.c | 487 ++++++++
drivers/gpu/drm/verisilicon/vs_plane.h | 26 +
drivers/gpu/drm/verisilicon/vs_simple_enc.c | 190 +++
drivers/gpu/drm/verisilicon/vs_simple_enc.h | 25 +
drivers/gpu/drm/verisilicon/vs_type.h | 84 ++
include/drm/bridge/inno_hdmi.h | 69 ++
38 files changed, 5840 insertions(+), 1144 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.yaml
create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,dsi-encoder.yaml
create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,jh7110-dc8200.yaml
create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,jh7110-inno-hdmi.yaml
create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
rename drivers/gpu/drm/rockchip/{inno_hdmi.h => inno_hdmi-rockchip.h} (85%)
delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c
create mode 100644 drivers/gpu/drm/verisilicon/Kconfig
create mode 100644 drivers/gpu/drm/verisilicon/Makefile
create mode 100644 drivers/gpu/drm/verisilicon/inno_hdmi-starfive.c
create mode 100644 drivers/gpu/drm/verisilicon/inno_hdmi-starfive.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_simple_enc.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_simple_enc.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_type.h
create mode 100644 include/drm/bridge/inno_hdmi.h
--
2.27.0
Add INNO common api so that it can be used by vendor
drivers which implement vendor specific extensions to Innosilicon HDMI.
Signed-off-by: keith <[email protected]>
---
MAINTAINERS | 2 +
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
.../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 ++++++++++++++++++
.../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 +++
include/drm/bridge/inno_hdmi.h | 69 ++
8 files changed, 766 insertions(+)
create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
create mode 100644 include/drm/bridge/inno_hdmi.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8881652bb8b6..cf2d66f88a83 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7155,6 +7155,8 @@ S: Maintained
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.yaml
F: Documentation/devicetree/bindings/display/starfive/
+F: drivers/gpu/drm/bridge/innosilicon/
+F: include/drm/bridge/inno_hdmi.h
DRM DRIVER FOR SYNAPTICS R63353 PANELS
M: Michael Trimarchi <[email protected]>
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index c621be1a99a8..59fcdb810125 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -415,6 +415,8 @@ source "drivers/gpu/drm/bridge/cadence/Kconfig"
source "drivers/gpu/drm/bridge/imx/Kconfig"
+source "drivers/gpu/drm/bridge/innosilicon/Kconfig"
+
source "drivers/gpu/drm/bridge/synopsys/Kconfig"
endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 7df87b582dca..cca7400566b2 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -40,4 +40,5 @@ obj-$(CONFIG_DRM_ITE_IT66121) += ite-it66121.o
obj-y += analogix/
obj-y += cadence/
obj-y += imx/
+obj-y += innosilicon/
obj-y += synopsys/
diff --git a/drivers/gpu/drm/bridge/innosilicon/Kconfig b/drivers/gpu/drm/bridge/innosilicon/Kconfig
new file mode 100644
index 000000000000..73dbed3b1c4d
--- /dev/null
+++ b/drivers/gpu/drm/bridge/innosilicon/Kconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config DRM_INNO_HDMI
+ tristate
+ help
+ Support the common interface which is part of the INNO
+ Designware HDMI block.
diff --git a/drivers/gpu/drm/bridge/innosilicon/Makefile b/drivers/gpu/drm/bridge/innosilicon/Makefile
new file mode 100644
index 000000000000..3b3a961ab9fb
--- /dev/null
+++ b/drivers/gpu/drm/bridge/innosilicon/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_DRM_INNO_HDMI) += inno-hdmi.o
diff --git a/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c b/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
new file mode 100644
index 000000000000..2378ce06a876
--- /dev/null
+++ b/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
@@ -0,0 +1,587 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Zheng Yang <[email protected]>
+ * Yakir Yang <[email protected]>
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+#include <drm/bridge/inno_hdmi.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "inno-hdmi.h"
+
+struct inno_hdmi_i2c {
+ struct i2c_adapter adap;
+
+ u8 ddc_addr;
+ u8 segment_addr;
+
+ struct mutex lock; /* For i2c operation. */
+ struct completion cmp;
+};
+
+struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
+{
+ return container_of(connector, struct inno_hdmi, connector);
+}
+EXPORT_SYMBOL_GPL(connector_to_inno_hdmi);
+
+u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
+{
+ return readl_relaxed(hdmi->regs + (offset) * 0x04);
+}
+EXPORT_SYMBOL_GPL(hdmi_readb);
+
+void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
+{
+ writel_relaxed(val, hdmi->regs + (offset) * 0x04);
+}
+EXPORT_SYMBOL_GPL(hdmi_writeb);
+
+void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, u32 msk, u32 val)
+{
+ u8 temp = hdmi_readb(hdmi, offset) & ~msk;
+
+ temp |= val & msk;
+ hdmi_writeb(hdmi, offset, temp);
+}
+EXPORT_SYMBOL_GPL(hdmi_modb);
+
+void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate)
+{
+ unsigned long long ddc_bus_freq = rate >> 2;
+
+ do_div(ddc_bus_freq, HDMI_SCL_RATE);
+
+ hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
+ hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
+
+ /* Clear the EDID interrupt flag and mute the interrupt */
+ hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
+ hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_i2c_init);
+
+void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
+{
+ if (enable)
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
+ else
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_sys_power);
+
+static enum drm_connector_status
+inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+
+ return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
+ connector_status_connected : connector_status_disconnected;
+}
+
+static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
+{
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+ const struct drm_edid *drm_edid;
+ int ret = 0;
+
+ if (!hdmi->ddc)
+ return 0;
+
+ drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
+ drm_edid_connector_update(connector, drm_edid);
+ ret = drm_edid_connector_add_modes(connector);
+ drm_edid_free(drm_edid);
+
+ return ret;
+}
+
+static enum drm_mode_status
+inno_hdmi_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode)
+{
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+
+ const struct inno_hdmi_plat_data *pdata = hdmi->plat_data;
+ enum drm_mode_status mode_status = MODE_OK;
+
+ if (pdata->mode_valid)
+ mode_status = pdata->mode_valid(connector, mode);
+
+ return mode_status;
+}
+
+static void
+inno_hdmi_connector_destroy_state(struct drm_connector *connector,
+ struct drm_connector_state *state)
+{
+ struct inno_hdmi_connector_state *inno_conn_state =
+ to_inno_hdmi_conn_state(state);
+
+ __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base);
+ kfree(inno_conn_state);
+}
+
+static void inno_hdmi_connector_reset(struct drm_connector *connector)
+{
+ struct inno_hdmi_connector_state *inno_conn_state;
+
+ if (connector->state) {
+ inno_hdmi_connector_destroy_state(connector, connector->state);
+ connector->state = NULL;
+ }
+
+ inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL);
+ if (!inno_conn_state)
+ return;
+
+ __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base);
+
+ inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
+ inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
+ inno_conn_state->rgb_limited_range = false;
+}
+
+static struct drm_connector_state *
+inno_hdmi_connector_duplicate_state(struct drm_connector *connector)
+{
+ struct inno_hdmi_connector_state *inno_conn_state;
+
+ if (WARN_ON(!connector->state))
+ return NULL;
+
+ inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state),
+ sizeof(*inno_conn_state), GFP_KERNEL);
+
+ if (!inno_conn_state)
+ return NULL;
+
+ __drm_atomic_helper_connector_duplicate_state(connector,
+ &inno_conn_state->base);
+
+ return &inno_conn_state->base;
+}
+
+static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = inno_hdmi_connector_detect,
+ .reset = inno_hdmi_connector_reset,
+ .atomic_duplicate_state = inno_hdmi_connector_duplicate_state,
+ .atomic_destroy_state = inno_hdmi_connector_destroy_state,
+};
+
+static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
+ .get_modes = inno_hdmi_connector_get_modes,
+ .mode_valid = inno_hdmi_connector_mode_valid,
+};
+
+static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi,
+ struct drm_encoder *encoder)
+{
+ struct device *dev = hdmi->dev;
+ const struct inno_hdmi_plat_data *pdata = hdmi->plat_data;
+
+ if (RK3128_HDMI == pdata->soc_type || RK3036_HDMI == pdata->soc_type)
+ drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+
+ /*
+ * If we failed to find the CRTC(s) which this encoder is
+ * supposed to be connected to, it's because the CRTC has
+ * not been registered yet. Defer probing, and hope that
+ * the required CRTC is added later.
+ */
+ if (encoder->possible_crtcs == 0)
+ return -EPROBE_DEFER;
+
+ drm_encoder_helper_add(encoder, pdata->helper_private);
+
+ hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
+
+ drm_connector_helper_add(&hdmi->connector,
+ &inno_hdmi_connector_helper_funcs);
+
+ drmm_connector_init(drm, &hdmi->connector,
+ &inno_hdmi_connector_funcs,
+ DRM_MODE_CONNECTOR_HDMIA,
+ hdmi->ddc);
+
+ drm_connector_attach_encoder(&hdmi->connector, encoder);
+
+ return 0;
+}
+
+static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
+{
+ struct inno_hdmi_i2c *i2c = hdmi->i2c;
+ u8 stat;
+
+ stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
+ if (!(stat & m_INT_EDID_READY))
+ return IRQ_NONE;
+
+ /* Clear HDMI EDID interrupt flag */
+ hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
+
+ complete(&i2c->cmp);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
+{
+ struct inno_hdmi *hdmi = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ u8 interrupt;
+
+ if (hdmi->i2c)
+ ret = inno_hdmi_i2c_irq(hdmi);
+
+ interrupt = hdmi_readb(hdmi, HDMI_STATUS);
+ if (interrupt & m_INT_HOTPLUG) {
+ hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
+ ret = IRQ_WAKE_THREAD;
+ }
+
+ return ret;
+}
+
+static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
+{
+ struct inno_hdmi *hdmi = dev_id;
+
+ drm_helper_hpd_irq_event(hdmi->connector.dev);
+
+ return IRQ_HANDLED;
+}
+
+static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
+{
+ int length = msgs->len;
+ u8 *buf = msgs->buf;
+ int ret;
+
+ ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
+ if (!ret)
+ return -EAGAIN;
+
+ while (length--)
+ *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
+
+ return 0;
+}
+
+static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
+{
+ /*
+ * The DDC module only support read EDID message, so
+ * we assume that each word write to this i2c adapter
+ * should be the offset of EDID word address.
+ */
+ if (msgs->len != 1 || (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
+ return -EINVAL;
+
+ reinit_completion(&hdmi->i2c->cmp);
+
+ if (msgs->addr == DDC_SEGMENT_ADDR)
+ hdmi->i2c->segment_addr = msgs->buf[0];
+ if (msgs->addr == DDC_ADDR)
+ hdmi->i2c->ddc_addr = msgs->buf[0];
+
+ /* Set edid fifo first addr */
+ hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
+
+ /* Set edid word address 0x00/0x80 */
+ hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
+
+ /* Set edid segment pointer */
+ hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
+
+ return 0;
+}
+
+static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
+ struct i2c_msg *msgs, int num)
+{
+ struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
+ struct inno_hdmi_i2c *i2c = hdmi->i2c;
+ int i, ret = 0;
+
+ mutex_lock(&i2c->lock);
+
+ /* Clear the EDID interrupt flag and unmute the interrupt */
+ hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
+ hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
+
+ for (i = 0; i < num; i++) {
+ DRM_DEV_DEBUG(hdmi->dev,
+ "xfer: num: %d/%d, len: %d, flags: %#x\n",
+ i + 1, num, msgs[i].len, msgs[i].flags);
+
+ if (msgs[i].flags & I2C_M_RD)
+ ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
+ else
+ ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
+
+ if (ret < 0)
+ break;
+ }
+
+ if (!ret)
+ ret = num;
+
+ /* Mute HDMI EDID interrupt */
+ hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
+
+ mutex_unlock(&i2c->lock);
+
+ return ret;
+}
+
+static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm inno_hdmi_algorithm = {
+ .master_xfer = inno_hdmi_i2c_xfer,
+ .functionality = inno_hdmi_i2c_func,
+};
+
+static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
+{
+ struct i2c_adapter *adap;
+ struct inno_hdmi_i2c *i2c;
+ int ret;
+
+ i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
+ if (!i2c)
+ return ERR_PTR(-ENOMEM);
+
+ mutex_init(&i2c->lock);
+ init_completion(&i2c->cmp);
+
+ adap = &i2c->adap;
+ adap->owner = THIS_MODULE;
+ adap->dev.parent = hdmi->dev;
+ adap->dev.of_node = hdmi->dev->of_node;
+ adap->algo = &inno_hdmi_algorithm;
+ strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
+ i2c_set_adapdata(adap, hdmi);
+
+ ret = i2c_add_adapter(adap);
+ if (ret) {
+ dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
+ devm_kfree(hdmi->dev, i2c);
+ return ERR_PTR(ret);
+ }
+
+ hdmi->i2c = i2c;
+
+ DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
+
+ return adap;
+}
+
+int inno_hdmi_bind(struct drm_device *drm, struct inno_hdmi *hdmi, struct drm_encoder *encoder)
+{
+ int ret, irq;
+ struct platform_device *pdev = to_platform_device(hdmi->dev);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = irq;
+ return ret;
+ }
+
+ hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
+ if (IS_ERR(hdmi->ddc)) {
+ ret = PTR_ERR(hdmi->ddc);
+ hdmi->ddc = NULL;
+ return ret;
+ }
+
+ ret = inno_hdmi_register(drm, hdmi, encoder);
+ if (ret)
+ goto err_put_adapter;
+
+ /* Unmute hotplug interrupt */
+ hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
+
+ ret = devm_request_threaded_irq(hdmi->dev, irq, inno_hdmi_hardirq,
+ inno_hdmi_irq, IRQF_SHARED,
+ dev_name(hdmi->dev), hdmi);
+ if (ret)
+ goto err_put_adapter;
+
+ return ret;
+err_put_adapter:
+ i2c_put_adapter(hdmi->ddc);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_bind);
+
+static void inno_hdmi_disable_frame(struct inno_hdmi *hdmi,
+ enum hdmi_infoframe_type type)
+{
+ struct drm_connector *connector = &hdmi->connector;
+
+ if (type != HDMI_INFOFRAME_TYPE_AVI) {
+ drm_err(connector->dev,
+ "Unsupported infoframe type: %u\n", type);
+ return;
+ }
+
+ hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI);
+}
+
+static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi,
+ union hdmi_infoframe *frame, enum hdmi_infoframe_type type)
+{
+ struct drm_connector *connector = &hdmi->connector;
+ u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
+ ssize_t rc, i;
+
+ if (type != HDMI_INFOFRAME_TYPE_AVI) {
+ drm_err(connector->dev,
+ "Unsupported infoframe type: %u\n", type);
+ return 0;
+ }
+
+ inno_hdmi_disable_frame(hdmi, type);
+
+ rc = hdmi_infoframe_pack(frame, packed_frame,
+ sizeof(packed_frame));
+ if (rc < 0)
+ return rc;
+
+ for (i = 0; i < rc; i++)
+ hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
+ packed_frame[i]);
+
+ return 0;
+}
+
+int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi, struct drm_display_mode *mode)
+{
+ struct drm_connector *connector = &hdmi->connector;
+ struct drm_connector_state *conn_state = connector->state;
+ struct inno_hdmi_connector_state *inno_conn_state =
+ to_inno_hdmi_conn_state(conn_state);
+ union hdmi_infoframe frame;
+ int rc;
+
+ rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
+ &hdmi->connector,
+ mode);
+ if (rc) {
+ inno_hdmi_disable_frame(hdmi, HDMI_INFOFRAME_TYPE_AVI);
+ return rc;
+ }
+
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444)
+ frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
+ else if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV422)
+ frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
+ else
+ frame.avi.colorspace = HDMI_COLORSPACE_RGB;
+
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
+ drm_hdmi_avi_infoframe_quant_range(&frame.avi,
+ connector, mode,
+ inno_conn_state->rgb_limited_range ?
+ HDMI_QUANTIZATION_RANGE_LIMITED :
+ HDMI_QUANTIZATION_RANGE_FULL);
+ } else {
+ frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
+ frame.avi.ycc_quantization_range =
+ HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
+ }
+
+ return inno_hdmi_upload_frame(hdmi, &frame, HDMI_INFOFRAME_TYPE_AVI);
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_config_video_avi);
+
+int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, struct drm_display_mode *mode)
+{
+ int value;
+
+ /* Set detail external video timing polarity and interlace mode */
+ value = v_EXTERANL_VIDEO(1);
+ if (hdmi->plat_data->soc_type == STARFIVE_HDMI) {
+ value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
+ v_HSYNC_POLARITY_SF(1) : v_HSYNC_POLARITY_SF(0);
+ value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
+ v_VSYNC_POLARITY_SF(1) : v_VSYNC_POLARITY_SF(0);
+ } else {
+ value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
+ v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
+ value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
+ v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
+ }
+ value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
+ v_INETLACE(1) : v_INETLACE(0);
+ hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
+
+ /* Set detail external video timing */
+ value = mode->htotal;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
+
+ value = mode->htotal - mode->hdisplay;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
+
+ value = mode->htotal - mode->hsync_start;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
+
+ value = mode->hsync_end - mode->hsync_start;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
+
+ value = mode->vtotal;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
+
+ value = mode->vtotal - mode->vdisplay;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
+
+ value = mode->vtotal - mode->vsync_start;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
+
+ value = mode->vsync_end - mode->vsync_start;
+ hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
+
+ if (hdmi->plat_data->soc_type == STARFIVE_HDMI)
+ return 0;
+
+ hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
+ hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
+ hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_config_video_timing);
+
+MODULE_DESCRIPTION("INNO HDMI transmitter driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:inno-hdmi");
diff --git a/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h b/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
new file mode 100644
index 000000000000..233077cfb136
--- /dev/null
+++ b/drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Zheng Yang <[email protected]>
+ * Yakir Yang <[email protected]>
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __INNO_H__
+#define __INNO_H__
+
+#define DDC_SEGMENT_ADDR 0x30
+
+#define HDMI_SCL_RATE (100 * 1000)
+#define DDC_BUS_FREQ_L 0x4b
+#define DDC_BUS_FREQ_H 0x4c
+
+#define HDMI_SYS_CTRL 0x00
+#define m_RST_ANALOG (1 << 6)
+#define v_RST_ANALOG (0 << 6)
+#define v_NOT_RST_ANALOG (1 << 6)
+#define m_RST_DIGITAL (1 << 5)
+#define v_RST_DIGITAL (0 << 5)
+#define v_NOT_RST_DIGITAL (1 << 5)
+#define m_REG_CLK_INV (1 << 4)
+#define v_REG_CLK_NOT_INV (0 << 4)
+#define v_REG_CLK_INV (1 << 4)
+#define m_VCLK_INV (1 << 3)
+#define v_VCLK_NOT_INV (0 << 3)
+#define v_VCLK_INV (1 << 3)
+#define m_REG_CLK_SOURCE (1 << 2)
+#define v_REG_CLK_SOURCE_TMDS (0 << 2)
+#define v_REG_CLK_SOURCE_SYS (1 << 2)
+#define m_POWER (1 << 1)
+#define v_PWR_ON (0 << 1)
+#define v_PWR_OFF (1 << 1)
+#define m_INT_POL (1 << 0)
+#define v_INT_POL_HIGH 1
+#define v_INT_POL_LOW 0
+
+#define HDMI_VIDEO_TIMING_CTL 0x08
+#define v_HSYNC_POLARITY(n) ((n) << 3)
+#define v_VSYNC_POLARITY(n) ((n) << 2)
+#define v_VSYNC_POLARITY_SF(n) ((n) << 3)
+#define v_HSYNC_POLARITY_SF(n) ((n) << 2)
+#define v_INETLACE(n) ((n) << 1)
+#define v_EXTERANL_VIDEO(n) ((n) << 0)
+
+#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
+#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
+#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
+#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
+#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
+#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
+#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
+#define HDMI_VIDEO_EXT_HDURATION_H 0x10
+#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
+#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
+#define HDMI_VIDEO_EXT_VBLANK 0x13
+#define HDMI_VIDEO_EXT_VDELAY 0x14
+#define HDMI_VIDEO_EXT_VDURATION 0x15
+
+#define HDMI_EDID_SEGMENT_POINTER 0x4d
+#define HDMI_EDID_WORD_ADDR 0x4e
+#define HDMI_EDID_FIFO_OFFSET 0x4f
+#define HDMI_EDID_FIFO_ADDR 0x50
+
+#define HDMI_INTERRUPT_MASK1 0xc0
+#define HDMI_INTERRUPT_STATUS1 0xc1
+#define m_INT_ACTIVE_VSYNC (1 << 5)
+#define m_INT_EDID_READY (1 << 2)
+
+#define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f
+enum {
+ INFOFRAME_VSI = 0x05,
+ INFOFRAME_AVI = 0x06,
+ INFOFRAME_AAI = 0x08,
+};
+
+#define HDMI_CONTROL_PACKET_ADDR 0xa0
+#define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11
+
+#define HDMI_STATUS 0xc8
+#define m_HOTPLUG (1 << 7)
+#define m_MASK_INT_HOTPLUG (1 << 5)
+#define m_INT_HOTPLUG (1 << 1)
+#define v_MASK_INT_HOTPLUG(n) (((n) & 0x1) << 5)
+
+#define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7
+#define v_FEEDBACK_DIV_LOW(n) ((n) & 0xff)
+#define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8
+#define v_FEEDBACK_DIV_HIGH(n) ((n) & 1)
+
+#define HDMI_PHY_PRE_DIV_RATIO 0xed
+#define v_PRE_DIV_RATIO(n) ((n) & 0x1f)
+
+#endif /* __INNO_H__ */
diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h
new file mode 100644
index 000000000000..bc865f5343ce
--- /dev/null
+++ b/include/drm/bridge/inno_hdmi.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __INNO_COMMON_HDMI__
+#define __INNO_COMMON_HDMI__
+
+#include <drm/drm_connector.h>
+#include <drm/drm_encoder.h>
+
+struct inno_hdmi_connector_state {
+ struct drm_connector_state base;
+ unsigned int enc_out_format;
+ unsigned int colorimetry;
+ bool rgb_limited_range;
+};
+
+enum inno_hdmi_devtype {
+ RK3036_HDMI,
+ RK3128_HDMI,
+ STARFIVE_HDMI,
+};
+
+#define to_inno_hdmi_conn_state(conn_state) \
+ container_of_const(conn_state, struct inno_hdmi_connector_state, base)
+
+struct inno_hdmi_phy_config {
+ unsigned long pixelclock;
+ u8 pre_emphasis;
+ u8 voltage_level_control;
+};
+
+struct inno_hdmi_plat_data {
+ enum inno_hdmi_devtype soc_type;
+
+ /* Platform-specific mode validation*/
+ enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
+ struct drm_display_mode *mode);
+ /* Platform-specific encoder helper funcs*/
+ const struct drm_encoder_helper_funcs *helper_private;
+
+ /* Platform-specific phy_configs Optional*/
+ struct inno_hdmi_phy_config *phy_configs;
+ struct inno_hdmi_phy_config *default_phy_config;
+};
+
+struct inno_hdmi {
+ struct device *dev;
+ void __iomem *regs;
+
+ struct drm_connector connector;
+ struct inno_hdmi_i2c *i2c;
+ struct i2c_adapter *ddc;
+ const struct inno_hdmi_plat_data *plat_data;
+};
+
+u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset);
+void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val);
+void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, u32 msk, u32 val);
+
+struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector);
+void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate);
+int inno_hdmi_bind(struct drm_device *drm, struct inno_hdmi *hdmi, struct drm_encoder *encoder);
+void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable);
+int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi, struct drm_display_mode *mode);
+int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, struct drm_display_mode *mode);
+
+#endif /* __INNO_COMMON_HDMI__ */
--
2.27.0
add hardware base api for vs drm
Signed-off-by: keith <[email protected]>
---
MAINTAINERS | 1 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/verisilicon/Kconfig | 13 +
drivers/gpu/drm/verisilicon/Makefile | 5 +
drivers/gpu/drm/verisilicon/vs_dc_hw.c | 1060 ++++++++++++++++++++++++
drivers/gpu/drm/verisilicon/vs_dc_hw.h | 493 +++++++++++
drivers/gpu/drm/verisilicon/vs_type.h | 84 ++
8 files changed, 1659 insertions(+)
create mode 100644 drivers/gpu/drm/verisilicon/Kconfig
create mode 100644 drivers/gpu/drm/verisilicon/Makefile
create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.c
create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.h
create mode 100644 drivers/gpu/drm/verisilicon/vs_type.h
diff --git a/MAINTAINERS b/MAINTAINERS
index cf2d66f88a83..9cb376f76f74 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7156,6 +7156,7 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.yaml
F: Documentation/devicetree/bindings/display/starfive/
F: drivers/gpu/drm/bridge/innosilicon/
+F: drivers/gpu/drm/verisilicon
F: include/drm/bridge/inno_hdmi.h
DRM DRIVER FOR SYNAPTICS R63353 PANELS
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 026444eeb5c6..5413d87ef1d6 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -423,6 +423,8 @@ source "drivers/gpu/drm/sprd/Kconfig"
source "drivers/gpu/drm/imagination/Kconfig"
+source "drivers/gpu/drm/verisilicon/Kconfig"
+
config DRM_HYPERV
tristate "DRM Support for Hyper-V synthetic video device"
depends on DRM && PCI && MMU && HYPERV
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index f9ca4f8fa6c5..cb27092b1672 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -219,3 +219,4 @@ obj-y += solomon/
obj-$(CONFIG_DRM_SPRD) += sprd/
obj-$(CONFIG_DRM_LOONGSON) += loongson/
obj-$(CONFIG_DRM_POWERVR) += imagination/
+obj-$(CONFIG_DRM_VERISILICON_DC8200) += verisilicon/
diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig
new file mode 100644
index 000000000000..2d733f93439e
--- /dev/null
+++ b/drivers/gpu/drm/verisilicon/Kconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0
+config DRM_VERISILICON_DC8200
+ tristate "DRM Support for VeriSilicon DC8200"
+ depends on DRM
+ select DRM_KMS_HELPER
+ select DRM_GEM_DMA_HELPER
+ select CMA
+ select DMA_CMA
+ help
+ Choose this option if you have a VeriSilicon DC8200 chipset.
+ This driver provides VeriSilicon kernel mode
+ setting and buffer management. It does not
+ provide 2D or 3D acceleration.
diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile
new file mode 100644
index 000000000000..7da54b259940
--- /dev/null
+++ b/drivers/gpu/drm/verisilicon/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+vs_drm-objs := vs_dc_hw.o
+
+obj-$(CONFIG_DRM_VERISILICON_DC8200) += vs_drm.o
diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.c b/drivers/gpu/drm/verisilicon/vs_dc_hw.c
new file mode 100644
index 000000000000..69f020f8352f
--- /dev/null
+++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.c
@@ -0,0 +1,1060 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
+ */
+
+#include <linux/bits.h>
+#include <linux/io.h>
+#include <linux/media-bus-format.h>
+//#include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_fb_dma_helper.h>
+
+#include "vs_dc_hw.h"
+
+static const u32 horkernel[] = {
+ 0x00000000, 0x20000000, 0x00002000, 0x00000000,
+ 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000,
+ 0x00000000, 0x00000000, 0x181f0000, 0x000027e1,
+ 0x00000000, 0x00000000, 0x00000000, 0x2b981468,
+ 0x00000000, 0x00000000, 0x00000000, 0x10f00000,
+ 0x00002f10, 0x00000000, 0x00000000, 0x00000000,
+ 0x32390dc7, 0x00000000, 0x00000000, 0x00000000,
+ 0x0af50000, 0x0000350b, 0x00000000, 0x00000000,
+ 0x00000000, 0x3781087f, 0x00000000, 0x00000000,
+ 0x00000000, 0x06660000, 0x0000399a, 0x00000000,
+ 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000,
+ 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4,
+ 0x00000000, 0x00000000, 0x00000000, 0x3de1021f,
+ 0x00000000, 0x00000000, 0x00000000, 0x01470000,
+ 0x00003eb9, 0x00000000, 0x00000000, 0x00000000,
+ 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000,
+ 0x00480000, 0x00003fb8, 0x00000000, 0x00000000,
+ 0x00000000, 0x3fef0011, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00004000, 0x00000000,
+ 0x00000000, 0x00000000, 0x20002000, 0x00000000,
+ 0x00000000, 0x00000000, 0x1c030000, 0x000023fd,
+ 0x00000000, 0x00000000, 0x00000000, 0x27e1181f,
+ 0x00000000, 0x00000000, 0x00000000, 0x14680000,
+ 0x00002b98, 0x00000000, 0x00000000, 0x00000000,
+ 0x2f1010f0, 0x00000000, 0x00000000, 0x00000000,
+ 0x0dc70000, 0x00003239, 0x00000000, 0x00000000,
+ 0x00000000, 0x350b0af5, 0x00000000, 0x00000000,
+ 0x00000000, 0x087f0000, 0x00003781, 0x00000000,
+ 0x00000000, 0x00000000, 0x399a0666, 0x00000000,
+ 0x00000000, 0x00000000, 0x04a70000, 0x00003b59,
+ 0x00000000, 0x00000000, 0x00000000, 0x3cc4033c,
+ 0x00000000, 0x00000000, 0x00000000, 0x021f0000,
+};
+
+#define H_COEF_SIZE ARRAY_SIZE(horkernel)
+
+static const u32 verkernel[] = {
+ 0x00000000, 0x20000000, 0x00002000, 0x00000000,
+ 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000,
+ 0x00000000, 0x00000000, 0x181f0000, 0x000027e1,
+ 0x00000000, 0x00000000, 0x00000000, 0x2b981468,
+ 0x00000000, 0x00000000, 0x00000000, 0x10f00000,
+ 0x00002f10, 0x00000000, 0x00000000, 0x00000000,
+ 0x32390dc7, 0x00000000, 0x00000000, 0x00000000,
+ 0x0af50000, 0x0000350b, 0x00000000, 0x00000000,
+ 0x00000000, 0x3781087f, 0x00000000, 0x00000000,
+ 0x00000000, 0x06660000, 0x0000399a, 0x00000000,
+ 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000,
+ 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4,
+ 0x00000000, 0x00000000, 0x00000000, 0x3de1021f,
+ 0x00000000, 0x00000000, 0x00000000, 0x01470000,
+ 0x00003eb9, 0x00000000, 0x00000000, 0x00000000,
+ 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000,
+ 0x00480000, 0x00003fb8, 0x00000000, 0x00000000,
+ 0x00000000, 0x3fef0011, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00004000, 0x00000000,
+ 0xcdcd0000, 0xfdfdfdfd, 0xabababab, 0xabababab,
+ 0x00000000, 0x00000000, 0x5ff5f456, 0x000f5f58,
+ 0x02cc6c78, 0x02cc0c28, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+ 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
+};
+
+#define V_COEF_SIZE ARRAY_SIZE(verkernel)
+
+/*
+ * RGB 709->2020 conversion parameters
+ */
+static const u16 RGB2RGB[RGB_TO_RGB_TABLE_SIZE] = {
+ 10279, 5395, 709,
+ 1132, 15065, 187,
+ 269, 1442, 14674
+};
+
+/*
+ * YUV601 to RGB conversion parameters
+ * YUV2RGB[0] - [8] : C0 - C8;
+ * YUV2RGB[9] - [11]: D0 - D2;
+ * YUV2RGB[12] - [13]: Y clamp min & max calue;
+ * YUV2RGB[14] - [15]: UV clamp min & max calue;
+ */
+static const s32 YUV601_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
+ 1196, 0, 1640, 1196,
+ -404, -836, 1196, 2076,
+ 0, -916224, 558336, -1202944,
+ 64, 940, 64, 960
+};
+
+/*
+ * YUV709 to RGB conversion parameters
+ * YUV2RGB[0] - [8] : C0 - C8;
+ * YUV2RGB[9] - [11]: D0 - D2;
+ * YUV2RGB[12] - [13]: Y clamp min & max calue;
+ * YUV2RGB[14] - [15]: UV clamp min & max calue;
+ */
+static s32 YUV709_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
+ 1196, 0, 1844, 1196,
+ -220, -548, 1196, 2172,
+ 0, -1020672, 316672, -1188608,
+ 64, 940, 64, 960
+};
+
+/*
+ * YUV2020 to RGB conversion parameters
+ * YUV2RGB[0] - [8] : C0 - C8;
+ * YUV2RGB[9] - [11]: D0 - D2;
+ * YUV2RGB[12] - [13]: Y clamp min & max calue;
+ * YUV2RGB[14] - [15]: UV clamp min & max calue;
+ */
+static s32 YUV2020_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
+ 1196, 0, 1724, 1196,
+ -192, -668, 1196, 2200,
+ 0, -959232, 363776, -1202944,
+ 64, 940, 64, 960
+};
+
+/*
+ * RGB to YUV2020 conversion parameters
+ * RGB2YUV[0] - [8] : C0 - C8;
+ * RGB2YUV[9] - [11]: D0 - D2;
+ */
+static s16 RGB2YUV[RGB_TO_YUV_TABLE_SIZE] = {
+ 230, 594, 52,
+ -125, -323, 448,
+ 448, -412, -36,
+ 64, 512, 512
+};
+
+/* one is for primary plane and the other is for all overlay planes */
+static const struct dc_hw_plane_reg dc_plane_reg[] = {
+ {
+ .y_address = DC_FRAMEBUFFER_ADDRESS,
+ .u_address = DC_FRAMEBUFFER_U_ADDRESS,
+ .v_address = DC_FRAMEBUFFER_V_ADDRESS,
+ .y_stride = DC_FRAMEBUFFER_STRIDE,
+ .u_stride = DC_FRAMEBUFFER_U_STRIDE,
+ .v_stride = DC_FRAMEBUFFER_V_STRIDE,
+ .size = DC_FRAMEBUFFER_SIZE,
+ .top_left = DC_FRAMEBUFFER_TOP_LEFT,
+ .bottom_right = DC_FRAMEBUFFER_BOTTOM_RIGHT,
+ .scale_factor_x = DC_FRAMEBUFFER_SCALE_FACTOR_X,
+ .scale_factor_y = DC_FRAMEBUFFER_SCALE_FACTOR_Y,
+ .h_filter_coef_index = DC_FRAMEBUFFER_H_FILTER_COEF_INDEX,
+ .h_filter_coef_data = DC_FRAMEBUFFER_H_FILTER_COEF_DATA,
+ .v_filter_coef_index = DC_FRAMEBUFFER_V_FILTER_COEF_INDEX,
+ .v_filter_coef_data = DC_FRAMEBUFFER_V_FILTER_COEF_DATA,
+ .init_offset = DC_FRAMEBUFFER_INIT_OFFSET,
+ .color_key = DC_FRAMEBUFFER_COLOR_KEY,
+ .color_key_high = DC_FRAMEBUFFER_COLOR_KEY_HIGH,
+ .clear_value = DC_FRAMEBUFFER_CLEAR_VALUE,
+ .color_table_index = DC_FRAMEBUFFER_COLOR_TABLE_INDEX,
+ .color_table_data = DC_FRAMEBUFFER_COLOR_TABLE_DATA,
+ .scale_config = DC_FRAMEBUFFER_SCALE_CONFIG,
+ .water_mark = DC_FRAMEBUFFER_WATER_MARK,
+ .degamma_index = DC_FRAMEBUFFER_DEGAMMA_INDEX,
+ .degamma_data = DC_FRAMEBUFFER_DEGAMMA_DATA,
+ .degamma_ex_data = DC_FRAMEBUFFER_DEGAMMA_EX_DATA,
+ .src_global_color = DC_FRAMEBUFFER_SRC_GLOBAL_COLOR,
+ .dst_global_color = DC_FRAMEBUFFER_DST_GLOBAL_COLOR,
+ .blend_config = DC_FRAMEBUFFER_BLEND_CONFIG,
+ .roi_origin = DC_FRAMEBUFFER_ROI_ORIGIN,
+ .roi_size = DC_FRAMEBUFFER_ROI_SIZE,
+ .yuv_to_rgb_coef0 = DC_FRAMEBUFFER_YUVTORGB_COEF0,
+ .yuv_to_rgb_coef1 = DC_FRAMEBUFFER_YUVTORGB_COEF1,
+ .yuv_to_rgb_coef2 = DC_FRAMEBUFFER_YUVTORGB_COEF2,
+ .yuv_to_rgb_coef3 = DC_FRAMEBUFFER_YUVTORGB_COEF3,
+ .yuv_to_rgb_coef4 = DC_FRAMEBUFFER_YUVTORGB_COEF4,
+ .yuv_to_rgb_coefd0 = DC_FRAMEBUFFER_YUVTORGB_COEFD0,
+ .yuv_to_rgb_coefd1 = DC_FRAMEBUFFER_YUVTORGB_COEFD1,
+ .yuv_to_rgb_coefd2 = DC_FRAMEBUFFER_YUVTORGB_COEFD2,
+ .y_clamp_bound = DC_FRAMEBUFFER_Y_CLAMP_BOUND,
+ .uv_clamp_bound = DC_FRAMEBUFFER_UV_CLAMP_BOUND,
+ .rgb_to_rgb_coef0 = DC_FRAMEBUFFER_RGBTORGB_COEF0,
+ .rgb_to_rgb_coef1 = DC_FRAMEBUFFER_RGBTORGB_COEF1,
+ .rgb_to_rgb_coef2 = DC_FRAMEBUFFER_RGBTORGB_COEF2,
+ .rgb_to_rgb_coef3 = DC_FRAMEBUFFER_RGBTORGB_COEF3,
+ .rgb_to_rgb_coef4 = DC_FRAMEBUFFER_RGBTORGB_COEF4,
+ },
+ {
+ .y_address = DC_OVERLAY_ADDRESS,
+ .u_address = DC_OVERLAY_U_ADDRESS,
+ .v_address = DC_OVERLAY_V_ADDRESS,
+ .y_stride = DC_OVERLAY_STRIDE,
+ .u_stride = DC_OVERLAY_U_STRIDE,
+ .v_stride = DC_OVERLAY_V_STRIDE,
+ .size = DC_OVERLAY_SIZE,
+ .top_left = DC_OVERLAY_TOP_LEFT,
+ .bottom_right = DC_OVERLAY_BOTTOM_RIGHT,
+ .scale_factor_x = DC_OVERLAY_SCALE_FACTOR_X,
+ .scale_factor_y = DC_OVERLAY_SCALE_FACTOR_Y,
+ .h_filter_coef_index = DC_OVERLAY_H_FILTER_COEF_INDEX,
+ .h_filter_coef_data = DC_OVERLAY_H_FILTER_COEF_DATA,
+ .v_filter_coef_index = DC_OVERLAY_V_FILTER_COEF_INDEX,
+ .v_filter_coef_data = DC_OVERLAY_V_FILTER_COEF_DATA,
+ .init_offset = DC_OVERLAY_INIT_OFFSET,
+ .color_key = DC_OVERLAY_COLOR_KEY,
+ .color_key_high = DC_OVERLAY_COLOR_KEY_HIGH,
+ .clear_value = DC_OVERLAY_CLEAR_VALUE,
+ .color_table_index = DC_OVERLAY_COLOR_TABLE_INDEX,
+ .color_table_data = DC_OVERLAY_COLOR_TABLE_DATA,
+ .scale_config = DC_OVERLAY_SCALE_CONFIG,
+ .water_mark = DC_OVERLAY_WATER_MARK,
+ .degamma_index = DC_OVERLAY_DEGAMMA_INDEX,
+ .degamma_data = DC_OVERLAY_DEGAMMA_DATA,
+ .degamma_ex_data = DC_OVERLAY_DEGAMMA_EX_DATA,
+ .src_global_color = DC_OVERLAY_SRC_GLOBAL_COLOR,
+ .dst_global_color = DC_OVERLAY_DST_GLOBAL_COLOR,
+ .blend_config = DC_OVERLAY_BLEND_CONFIG,
+ .roi_origin = DC_OVERLAY_ROI_ORIGIN,
+ .roi_size = DC_OVERLAY_ROI_SIZE,
+ .yuv_to_rgb_coef0 = DC_OVERLAY_YUVTORGB_COEF0,
+ .yuv_to_rgb_coef1 = DC_OVERLAY_YUVTORGB_COEF1,
+ .yuv_to_rgb_coef2 = DC_OVERLAY_YUVTORGB_COEF2,
+ .yuv_to_rgb_coef3 = DC_OVERLAY_YUVTORGB_COEF3,
+ .yuv_to_rgb_coef4 = DC_OVERLAY_YUVTORGB_COEF4,
+ .yuv_to_rgb_coefd0 = DC_OVERLAY_YUVTORGB_COEFD0,
+ .yuv_to_rgb_coefd1 = DC_OVERLAY_YUVTORGB_COEFD1,
+ .yuv_to_rgb_coefd2 = DC_OVERLAY_YUVTORGB_COEFD2,
+ .y_clamp_bound = DC_OVERLAY_Y_CLAMP_BOUND,
+ .uv_clamp_bound = DC_OVERLAY_UV_CLAMP_BOUND,
+ .rgb_to_rgb_coef0 = DC_OVERLAY_RGBTORGB_COEF0,
+ .rgb_to_rgb_coef1 = DC_OVERLAY_RGBTORGB_COEF1,
+ .rgb_to_rgb_coef2 = DC_OVERLAY_RGBTORGB_COEF2,
+ .rgb_to_rgb_coef3 = DC_OVERLAY_RGBTORGB_COEF3,
+ .rgb_to_rgb_coef4 = DC_OVERLAY_RGBTORGB_COEF4,
+ },
+};
+
+static inline u32 hi_read(struct dc_hw *hw, u32 reg)
+{
+ return readl(hw->hi_base + reg);
+}
+
+static inline void hi_write(struct dc_hw *hw, u32 reg, u32 value)
+{
+ writel(value, hw->hi_base + reg);
+}
+
+static inline void dc_write(struct dc_hw *hw, u32 reg, u32 value)
+{
+ writel(value, hw->reg_base + reg - DC_REG_BASE);
+}
+
+static inline u32 dc_read(struct dc_hw *hw, u32 reg)
+{
+ u32 value = readl(hw->reg_base + reg - DC_REG_BASE);
+
+ return value;
+}
+
+static inline void dc_set_clear(struct dc_hw *hw, u32 reg, u32 set, u32 clear)
+{
+ u32 value = dc_read(hw, reg);
+
+ value &= ~clear;
+ value |= set;
+ dc_write(hw, reg, value);
+}
+
+static void load_default_filter(struct dc_hw *hw,
+ const struct dc_hw_plane_reg *reg, u32 offset)
+{
+ u8 i;
+
+ dc_write(hw, reg->scale_config + offset, 0x33);
+ dc_write(hw, reg->init_offset + offset, 0x80008000);
+ dc_write(hw, reg->h_filter_coef_index + offset, 0x00);
+ for (i = 0; i < H_COEF_SIZE; i++)
+ dc_write(hw, reg->h_filter_coef_data + offset, horkernel[i]);
+
+ dc_write(hw, reg->v_filter_coef_index + offset, 0x00);
+ for (i = 0; i < V_COEF_SIZE; i++)
+ dc_write(hw, reg->v_filter_coef_data + offset, verkernel[i]);
+}
+
+static void load_rgb_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg,
+ u32 offset, const u16 *table)
+{
+ dc_write(hw, reg->rgb_to_rgb_coef0 + offset, table[0] | (table[1] << 16));
+ dc_write(hw, reg->rgb_to_rgb_coef1 + offset, table[2] | (table[3] << 16));
+ dc_write(hw, reg->rgb_to_rgb_coef2 + offset, table[4] | (table[5] << 16));
+ dc_write(hw, reg->rgb_to_rgb_coef3 + offset, table[6] | (table[7] << 16));
+ dc_write(hw, reg->rgb_to_rgb_coef4 + offset, table[8]);
+}
+
+static void load_yuv_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg,
+ u32 offset, const s32 *table)
+{
+ dc_write(hw, reg->yuv_to_rgb_coef0 + offset,
+ (0xFFFF & table[0]) | (table[1] << 16));
+ dc_write(hw, reg->yuv_to_rgb_coef1 + offset,
+ (0xFFFF & table[2]) | (table[3] << 16));
+ dc_write(hw, reg->yuv_to_rgb_coef2 + offset,
+ (0xFFFF & table[4]) | (table[5] << 16));
+ dc_write(hw, reg->yuv_to_rgb_coef3 + offset,
+ (0xFFFF & table[6]) | (table[7] << 16));
+ dc_write(hw, reg->yuv_to_rgb_coef4 + offset, table[8]);
+ dc_write(hw, reg->yuv_to_rgb_coefd0 + offset, table[9]);
+ dc_write(hw, reg->yuv_to_rgb_coefd1 + offset, table[10]);
+ dc_write(hw, reg->yuv_to_rgb_coefd2 + offset, table[11]);
+ dc_write(hw, reg->y_clamp_bound + offset, table[12] | (table[13] << 16));
+ dc_write(hw, reg->uv_clamp_bound + offset, table[14] | (table[15] << 16));
+}
+
+static void load_rgb_to_yuv(struct dc_hw *hw, u32 offset, s16 *table)
+{
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF0 + offset,
+ table[0] | (table[1] << 16));
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF1 + offset,
+ table[2] | (table[3] << 16));
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF2 + offset,
+ table[4] | (table[5] << 16));
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF3 + offset,
+ table[6] | (table[7] << 16));
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF4 + offset, table[8]);
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD0 + offset, table[9]);
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD1 + offset, table[10]);
+ dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD2 + offset, table[11]);
+}
+
+static int update_vs_format(u32 drm_format)
+{
+ u8 f = FORMAT_A8R8G8B8;
+
+ switch (drm_format) {
+ case DRM_FORMAT_XRGB4444:
+ case DRM_FORMAT_RGBX4444:
+ case DRM_FORMAT_XBGR4444:
+ case DRM_FORMAT_BGRX4444:
+ f = FORMAT_X4R4G4B4;
+ break;
+ case DRM_FORMAT_ARGB4444:
+ case DRM_FORMAT_RGBA4444:
+ case DRM_FORMAT_ABGR4444:
+ case DRM_FORMAT_BGRA4444:
+ f = FORMAT_A4R4G4B4;
+ break;
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_RGBX5551:
+ case DRM_FORMAT_XBGR1555:
+ case DRM_FORMAT_BGRX5551:
+ f = FORMAT_X1R5G5B5;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ case DRM_FORMAT_RGBA5551:
+ case DRM_FORMAT_ABGR1555:
+ case DRM_FORMAT_BGRA5551:
+ f = FORMAT_A1R5G5B5;
+ break;
+ case DRM_FORMAT_RGB565:
+ case DRM_FORMAT_BGR565:
+ f = FORMAT_R5G6B5;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_BGRX8888:
+ f = FORMAT_X8R8G8B8;
+ break;
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_BGRA8888:
+ f = FORMAT_A8R8G8B8;
+ break;
+ case DRM_FORMAT_YUYV:
+ case DRM_FORMAT_YVYU:
+ f = FORMAT_YUY2;
+ break;
+ case DRM_FORMAT_UYVY:
+ case DRM_FORMAT_VYUY:
+ f = FORMAT_UYVY;
+ break;
+ case DRM_FORMAT_YUV420:
+ case DRM_FORMAT_YVU420:
+ f = FORMAT_YV12;
+ break;
+ case DRM_FORMAT_NV21:
+ f = FORMAT_NV12;
+ break;
+ case DRM_FORMAT_NV16:
+ case DRM_FORMAT_NV61:
+ f = FORMAT_NV16;
+ break;
+ case DRM_FORMAT_P010:
+ f = FORMAT_P010;
+ break;
+ case DRM_FORMAT_ARGB2101010:
+ case DRM_FORMAT_RGBA1010102:
+ case DRM_FORMAT_ABGR2101010:
+ case DRM_FORMAT_BGRA1010102:
+ f = FORMAT_A2R10G10B10;
+ break;
+ case DRM_FORMAT_NV12:
+ f = FORMAT_NV12;
+ break;
+ case DRM_FORMAT_YUV444:
+ f = FORMAT_YUV444;
+ break;
+ default:
+ break;
+ }
+
+ return f;
+}
+
+int dc_hw_init(struct vs_dc *dc)
+{
+ u8 i, id, panel_num, layer_num;
+ struct dc_hw *hw = &dc->hw;
+ u32 offset;
+
+ layer_num = hw->info->layer_num;
+ for (i = 0; i < layer_num; i++) {
+ id = dc->planes[i].id;
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ hw->reg[i] = dc_plane_reg[0];
+ else
+ hw->reg[i] = dc_plane_reg[1];
+
+ load_default_filter(hw, &hw->reg[i], dc->planes[i].offset);
+ load_rgb_to_rgb(hw, &hw->reg[i], dc->planes[i].offset, RGB2RGB);
+ }
+
+ panel_num = hw->info->panel_num;
+ for (i = 0; i < panel_num; i++) {
+ offset = i << 2;
+
+ load_rgb_to_yuv(hw, offset, RGB2YUV);
+ dc_write(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0x111);
+
+ offset = i ? DC_CURSOR_OFFSET : 0;
+ dc_write(hw, DC_CURSOR_BACKGROUND + offset, 0x00FFFFFF);
+ dc_write(hw, DC_CURSOR_FOREGROUND + offset, 0x00AAAAAA);
+ }
+
+ return 0;
+}
+
+void dc_hw_disable_plane(struct vs_dc *dc, u8 id)
+{
+ struct dc_hw *hw = &dc->hw;
+
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + dc->planes[id].offset,
+ PRIMARY_EN(false), PRIMARY_EN_MASK);
+ else
+ dc_set_clear(hw, DC_OVERLAY_CONFIG + dc->planes[id].offset,
+ OVERLAY_FB_EN(false), OVERLAY_FB_EN_MASK);
+}
+
+static int update_cursor_size(uint32_t crtc_w)
+{
+ u8 size_type;
+
+ switch (crtc_w) {
+ case 32:
+ size_type = CURSOR_SIZE_32X32;
+ break;
+ case 64:
+ size_type = CURSOR_SIZE_64X64;
+ break;
+ default:
+ size_type = CURSOR_SIZE_32X32;
+ break;
+ }
+
+ return size_type;
+}
+
+void dc_hw_update_cursor(struct dc_hw *hw, u8 id, dma_addr_t dma_addr,
+ u32 crtc_w, u32 crtc_x, u32 crtc_y,
+ s32 hotspot_x, s32 hotspot_y)
+{
+ u32 offset, size;
+
+ offset = id ? DC_CURSOR_OFFSET : 0;
+ size = update_cursor_size(crtc_w);
+
+ dc_write(hw, DC_CURSOR_ADDRESS + offset,
+ dma_addr);
+ dc_write(hw, DC_CURSOR_LOCATION + offset,
+ X_LCOTION(crtc_x) |
+ Y_LCOTION(crtc_y));
+ dc_set_clear(hw, DC_CURSOR_CONFIG + offset,
+ CURSOR_HOT_X(hotspot_x) |
+ CURSOR_HOT_y(hotspot_y) |
+ CURSOR_SIZE(size) |
+ CURSOR_VALID(1) |
+ CURSOR_TRIG_FETCH(1) |
+ CURSOR_FORMAT(CURSOR_FORMAT_A8R8G8B8),
+ CURSOR_HOT_X_MASK |
+ CURSOR_HOT_y_MASK |
+ CURSOR_SIZE_MASK |
+ CURSOR_VALID_MASK |
+ CURSOR_TRIG_FETCH_MASK |
+ CURSOR_FORMAT_MASK);
+}
+
+void dc_hw_disable_cursor(struct dc_hw *hw, u8 id)
+{
+ u32 offset = 0;
+
+ offset = id ? DC_CURSOR_OFFSET : 0;
+ dc_set_clear(hw, DC_CURSOR_CONFIG + offset, CURSOR_VALID(1), CURSOR_FORMAT_MASK);
+}
+
+void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index,
+ u16 r, u16 g, u16 b)
+{
+ if (index >= hw->info->gamma_size)
+ return;
+
+ hw->gamma[id].gamma[index][0] = r;
+ hw->gamma[id].gamma[index][1] = g;
+ hw->gamma[id].gamma[index][2] = b;
+}
+
+void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable)
+{
+ u32 value;
+
+ if (enable) {
+ dc_write(hw, DC_DISPLAY_GAMMA_EX_INDEX + (id << 2), 0x00);
+ for (int i = 0; i < GAMMA_EX_SIZE; i++) {
+ value = hw->gamma[id].gamma[i][2] |
+ (hw->gamma[id].gamma[i][1] << 12);
+ dc_write(hw, DC_DISPLAY_GAMMA_EX_DATA + (id << 2), value);
+ dc_write(hw, DC_DISPLAY_GAMMA_EX_ONE_DATA + (id << 2),
+ hw->gamma[id].gamma[i][0]);
+ }
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (id << 2), PANEL_GAMMA_EN, 0);
+ } else {
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (id << 2), 0, PANEL_GAMMA_EN);
+ }
+}
+
+void dc_hw_enable(struct dc_hw *hw, int id, struct drm_display_mode *mode,
+ u8 encoder_type, u32 output_fmt)
+{
+ u32 dp_cfg, dpi_cfg, offset = id << 2;
+ bool is_yuv = false;
+
+ if (encoder_type != DRM_MODE_ENCODER_DSI) {
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ dp_cfg = 0;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ dp_cfg = 1;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ dp_cfg = 2;
+ break;
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ dp_cfg = 3;
+ break;
+ case MEDIA_BUS_FMT_UYVY8_1X16:
+ dp_cfg = 2 << 4;
+ is_yuv = true;
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ dp_cfg = 4 << 4;
+ is_yuv = true;
+ break;
+ case MEDIA_BUS_FMT_UYVY10_1X20:
+ dp_cfg = 8 << 4;
+ is_yuv = true;
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ dp_cfg = 10 << 4;
+ is_yuv = true;
+ break;
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ dp_cfg = 12 << 4;
+ is_yuv = true;
+ break;
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ dp_cfg = 13 << 4;
+ is_yuv = true;
+ break;
+ default:
+ dp_cfg = 2;
+ break;
+ }
+ if (is_yuv)
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, PANEL_RGB2YUV_EN, 0);
+ else
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, PANEL_RGB2YUV_EN);
+ dc_write(hw, DC_DISPLAY_DP_CONFIG + offset, dp_cfg | DP_SELECT);
+ }
+
+ if (hw->out[id] == OUT_DPI)
+ dc_set_clear(hw, DC_DISPLAY_DP_CONFIG + offset, 0, DP_SELECT);
+
+ switch (output_fmt) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ dpi_cfg = 0;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ dpi_cfg = 3;
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ dpi_cfg = 4;
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ dpi_cfg = 5;
+ break;
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ dpi_cfg = 6;
+ break;
+ default:
+ dpi_cfg = 5;
+ break;
+ }
+ dc_write(hw, DC_DISPLAY_DPI_CONFIG + offset, dpi_cfg);
+
+ if (id == 0)
+ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, PANEL0_EN | TWO_PANEL_EN);
+ else
+ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, PANEL1_EN | TWO_PANEL_EN);
+
+ dc_write(hw, DC_DISPLAY_H + offset,
+ H_ACTIVE_LEN(mode->hdisplay) |
+ H_TOTAL_LEN(mode->htotal));
+
+ dc_write(hw, DC_DISPLAY_H_SYNC + offset,
+ H_SYNC_START_LEN(mode->hsync_start) |
+ H_SYNC_END_LEN(mode->hsync_end) |
+ H_POLARITY_LEN(mode->flags & DRM_MODE_FLAG_PHSYNC ? 0 : 1) |
+ H_PLUS_LEN(1));
+
+ dc_write(hw, DC_DISPLAY_V + offset,
+ V_ACTIVE_LEN(mode->vdisplay) |
+ V_TOTAL_LEN(mode->vtotal));
+
+ dc_write(hw, DC_DISPLAY_V_SYNC + offset,
+ V_SYNC_START_LEN(mode->vsync_start) |
+ V_SYNC_END_LEN(mode->vsync_end) |
+ V_POLARITY_LEN(mode->flags & DRM_MODE_FLAG_PVSYNC ? 0 : 1) |
+ V_PLUS_LEN(1));
+
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, PANEL_OUTPUT_EN, 0);
+ dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(id), SYNC_EN);
+}
+
+void dc_hw_disable(struct dc_hw *hw, int id)
+{
+ u32 offset = id << 2;
+
+ if (hw->out[id] == OUT_DPI)
+ dc_set_clear(hw, DC_DISPLAY_DP_CONFIG + offset, 0, DP_SELECT);
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, PANEL_OUTPUT_EN);
+ dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(id) | TWO_PANEL_EN);
+}
+
+void dc_hw_enable_interrupt(struct dc_hw *hw)
+{
+ hi_write(hw, AQ_INTR_ENBL, 0xFFFFFFFF);
+}
+
+void dc_hw_disable_interrupt(struct dc_hw *hw)
+{
+ hi_write(hw, AQ_INTR_ENBL, 0);
+}
+
+u32 dc_hw_get_interrupt(struct dc_hw *hw)
+{
+ return hi_read(hw, AQ_INTR_ACKNOWLEDGE);
+}
+
+void dc_hw_enable_shadow_register(struct vs_dc *dc, bool enable)
+{
+ u32 i, offset;
+ struct dc_hw *hw = &dc->hw;
+ u8 id, layer_num = hw->info->layer_num;
+ u8 panel_num = hw->info->panel_num;
+
+ for (i = 0; i < layer_num; i++) {
+ id = dc->planes[i].id;
+ offset = dc->planes[i].offset;
+ if (enable) {
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
+ PRIMARY_SHADOW_EN, 0);
+ else
+ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
+ OVERLAY_SHADOW_EN, 0);
+ } else {
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
+ 0, PRIMARY_SHADOW_EN);
+ else
+ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
+ 0, OVERLAY_SHADOW_EN);
+ }
+ }
+
+ for (i = 0; i < panel_num; i++) {
+ offset = i << 2;
+ if (enable)
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, 0, PANEL_SHADOW_EN);
+ else
+ dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, PANEL_SHADOW_EN, 0);
+ }
+}
+
+void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id)
+{
+ if (out <= OUT_DP)
+ hw->out[id] = out;
+}
+
+static inline u8 to_vs_yuv_color_space(u32 color_space)
+{
+ u8 cs;
+
+ switch (color_space) {
+ case DRM_COLOR_YCBCR_BT601:
+ cs = COLOR_SPACE_601;
+ break;
+ case DRM_COLOR_YCBCR_BT709:
+ cs = COLOR_SPACE_709;
+ break;
+ case DRM_COLOR_YCBCR_BT2020:
+ cs = COLOR_SPACE_2020;
+ break;
+ default:
+ cs = COLOR_SPACE_601;
+ break;
+ }
+
+ return cs;
+}
+
+static inline u8 update_uv_swizzle(u32 format)
+{
+ u8 uv_swizzle = 0;
+
+ switch (format) {
+ case DRM_FORMAT_YVYU:
+ case DRM_FORMAT_VYUY:
+ case DRM_FORMAT_NV21:
+ case DRM_FORMAT_NV61:
+ uv_swizzle = 1;
+ break;
+ default:
+ break;
+ }
+
+ return uv_swizzle;
+}
+
+static inline u8 update_swizzle(u32 format)
+{
+ u8 swizzle = SWIZZLE_ARGB;
+
+ switch (format) {
+ case DRM_FORMAT_RGBX4444:
+ case DRM_FORMAT_RGBA4444:
+ case DRM_FORMAT_RGBX5551:
+ case DRM_FORMAT_RGBA5551:
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_RGBA1010102:
+ swizzle = SWIZZLE_RGBA;
+ break;
+ case DRM_FORMAT_XBGR4444:
+ case DRM_FORMAT_ABGR4444:
+ case DRM_FORMAT_XBGR1555:
+ case DRM_FORMAT_ABGR1555:
+ case DRM_FORMAT_BGR565:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ case DRM_FORMAT_ABGR2101010:
+ swizzle = SWIZZLE_ABGR;
+ break;
+ case DRM_FORMAT_BGRX4444:
+ case DRM_FORMAT_BGRA4444:
+ case DRM_FORMAT_BGRX5551:
+ case DRM_FORMAT_BGRA5551:
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ case DRM_FORMAT_BGRA1010102:
+ swizzle = SWIZZLE_BGRA;
+ break;
+ default:
+ break;
+ }
+
+ return swizzle;
+}
+
+static inline u8 to_vs_rotation(unsigned int rotation)
+{
+ u8 rot;
+
+ switch (rotation & DRM_MODE_REFLECT_MASK) {
+ case DRM_MODE_REFLECT_X:
+ rot = FLIP_X;
+ return rot;
+ case DRM_MODE_REFLECT_Y:
+ rot = FLIP_Y;
+ return rot;
+ case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
+ rot = FLIP_XY;
+ return rot;
+ default:
+ break;
+ }
+
+ switch (rotation & DRM_MODE_ROTATE_MASK) {
+ case DRM_MODE_ROTATE_0:
+ rot = ROT_0;
+ break;
+ case DRM_MODE_ROTATE_90:
+ rot = ROT_90;
+ break;
+ case DRM_MODE_ROTATE_180:
+ rot = ROT_180;
+ break;
+ case DRM_MODE_ROTATE_270:
+ rot = ROT_270;
+ break;
+ default:
+ rot = ROT_0;
+ break;
+ }
+
+ return rot;
+}
+
+void plane_hw_update_format_colorspace(struct vs_dc *dc, u32 format,
+ enum drm_color_encoding encoding, u8 id, bool is_yuv)
+{
+ u32 offset = dc->planes[id].offset;
+ struct dc_hw *hw = &dc->hw;
+
+ if (is_yuv) {
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
+ PRIMARY_YUVCLAMP_EN, PRIMARY_RGB2RGB_EN);
+ else
+ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
+ OVERLAY_CLAMP_EN, OVERLAY_RGB2RGB_EN);
+
+ switch (to_vs_yuv_color_space(encoding)) {
+ case COLOR_SPACE_601:
+ load_yuv_to_rgb(hw, &hw->reg[id], offset, YUV601_2RGB);
+ break;
+ case COLOR_SPACE_709:
+ load_yuv_to_rgb(hw, &hw->reg[id], offset, YUV709_2RGB);
+ break;
+ case COLOR_SPACE_2020:
+ load_yuv_to_rgb(hw, &hw->reg[id], offset, YUV2020_2RGB);
+ break;
+ default:
+ break;
+ }
+ } else {
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
+ PRIMARY_RGB2RGB_EN, PRIMARY_YUVCLAMP_EN);
+ else
+ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
+ OVERLAY_RGB2RGB_EN, OVERLAY_CLAMP_EN);
+ }
+}
+
+void plane_hw_update_address(struct vs_dc *dc, u8 id, u32 format, dma_addr_t *dma_addr,
+ struct drm_framebuffer *drm_fb, struct drm_rect *src)
+{
+ u32 offset = dc->planes[id].offset;
+ struct dc_hw *hw = &dc->hw;
+
+ dc_write(hw, hw->reg[id].y_address + offset, dma_addr[0]);
+ dc_write(hw, hw->reg[id].u_address + offset,
+ format == DRM_FORMAT_YVU420 ?
+ dma_addr[2] : dma_addr[1]);
+ dc_write(hw, hw->reg[id].v_address + offset,
+ format == DRM_FORMAT_YVU420 ?
+ dma_addr[1] : dma_addr[2]);
+ dc_write(hw, hw->reg[id].y_stride + offset, drm_fb->pitches[0]);
+ dc_write(hw, hw->reg[id].u_stride + offset,
+ format == DRM_FORMAT_YVU420 ?
+ drm_fb->pitches[2] : drm_fb->pitches[1]);
+ dc_write(hw, hw->reg[id].v_stride + offset,
+ format == DRM_FORMAT_YVU420 ?
+ drm_fb->pitches[1] : drm_fb->pitches[2]);
+ dc_write(hw, hw->reg[id].size + offset,
+ FB_SIZE(drm_rect_width(src) >> 16, drm_rect_height(src) >> 16));
+}
+
+void plane_hw_update_format(struct vs_dc *dc, u32 format, enum drm_color_encoding encoding,
+ unsigned int rotation, bool visible, unsigned int zpos,
+ u8 id, u8 display_id)
+{
+ u32 offset = dc->planes[id].offset;
+ struct dc_hw *hw = &dc->hw;
+
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) {
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset,
+ PRIMARY_FORMAT(update_vs_format(format)) |
+ PRIMARY_UV_SWIZ(update_uv_swizzle(format)) |
+ PRIMARY_SWIZ(update_swizzle(format)) |
+ PRIMARY_TILE(DRM_FORMAT_MOD_LINEAR) |
+ PRIMARY_YUV_COLOR(to_vs_yuv_color_space(encoding)) |
+ PRIMARY_ROTATION(to_vs_rotation(rotation)),
+ PRIMARY_FORMAT_MASK |
+ PRIMARY_UV_SWIZ_MASK |
+ PRIMARY_SWIZ_MASK |
+ PRIMARY_TILE_MASK |
+ PRIMARY_YUV_COLOR_MASK |
+ PRIMARY_ROTATION_MASK |
+ PRIMARY_CLEAR_EN_MASK);
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
+ PRIMARY_DECODER_EN(false) |
+ PRIMARY_EN(visible) |
+ PRIMARY_ZPOS(zpos) |
+ PRIMARY_CHANNEL(display_id),
+ PRIMARY_DECODER_EN_EN_MASK |
+ PRIMARY_EN_MASK |
+ PRIMARY_ZPOS_MASK |
+ PRIMARY_CHANNEL_MASK);
+ } else {
+ dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
+ OVERLAY_FB_EN(visible) |
+ OVERLAY_FORMAT(update_vs_format(format)) |
+ OVERLAY_UV_SWIZ(update_uv_swizzle(format)) |
+ OVERLAY_SWIZ(update_swizzle(format)) |
+ OVERLAY_TILE(DRM_FORMAT_MOD_LINEAR) |
+ OVERLAY_YUV_COLOR(to_vs_yuv_color_space(encoding)) |
+ OVERLAY_ROTATION(to_vs_rotation(rotation)),
+ OVERLAY_DEC_EN_MASK |
+ OVERLAY_CLEAR_EN_MASK |
+ OVERLAY_FB_EN_MASK |
+ OVERLAY_FORMAT_MASK |
+ OVERLAY_UV_SWIZ_MASK |
+ OVERLAY_SWIZ_MASK |
+ OVERLAY_TILE_MASK |
+ OVERLAY_YUV_COLOR_MASK |
+ OVERLAY_ROTATION_MASK);
+
+ dc_set_clear(hw, DC_OVERLAY_CONFIG_EX + offset,
+ OVERLAY_LAYER_SEL(zpos) |
+ OVERLAY_PANEL_SEL(display_id),
+ OVERLAY_LAYER_SEL_MASK |
+ OVERLAY_PANEL_SEL_MASK);
+ }
+}
+
+static u32 calc_factor(u32 src, u32 dest)
+{
+ u32 factor = 1 << 16;
+
+ if (src > 1 && dest > 1)
+ factor = ((src - 1) << 16) / (dest - 1);
+
+ return factor;
+}
+
+void plane_hw_update_scale(struct vs_dc *dc, struct drm_rect *src, struct drm_rect *dst,
+ u8 id, u8 display_id, unsigned int rotation)
+{
+ u32 offset = dc->planes[id].offset;
+ struct dc_hw *hw = &dc->hw;
+
+ int dst_w = drm_rect_width(dst);
+ int dst_h = drm_rect_height(dst);
+ int src_w, src_h, temp;
+ u32 scale_factor_x;
+ u32 scale_factor_y;
+ bool enable_scale = false;
+
+ src_w = drm_rect_width(src) >> 16;
+ src_h = drm_rect_height(src) >> 16;
+
+ if (drm_rotation_90_or_270(rotation)) {
+ temp = src_w;
+ src_w = src_h;
+ src_h = temp;
+ }
+
+ if (src_w != dst_w) {
+ scale_factor_x = calc_factor(src_w, dst_w);
+ enable_scale = true;
+ } else {
+ scale_factor_x = 1 << 16;
+ }
+ if (src_h != dst_h) {
+ scale_factor_y = calc_factor(src_h, dst_h);
+ enable_scale = true;
+ } else {
+ scale_factor_y = 1 << 16;
+ }
+ if (enable_scale) {
+ dc_write(hw, hw->reg[id].scale_factor_x + offset, scale_factor_x);
+ dc_write(hw, hw->reg[id].scale_factor_y + offset, scale_factor_y);
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset, PRIMARY_SCALE_EN, 0);
+ else
+ dc_set_clear(hw, DC_OVERLAY_SCALE_CONFIG + offset, OVERLAY_SCALE_EN, 0);
+ } else {
+ if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
+ dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset, 0, PRIMARY_SCALE_EN);
+ else
+ dc_set_clear(hw, DC_OVERLAY_SCALE_CONFIG + offset, 0, OVERLAY_SCALE_EN);
+ }
+
+ dc_write(hw, hw->reg[id].top_left + offset, X_POS(dst->x1) | Y_POS(dst->y1));
+ dc_write(hw, hw->reg[id].bottom_right + offset, X_POS(dst->x2) | Y_POS(dst->y2));
+}
+
+void plane_hw_update_blend(struct vs_dc *dc, u16 alpha,
+ u16 pixel_blend_mode, u8 id, u8 display_id)
+{
+ u32 offset = dc->planes[id].offset;
+ struct dc_hw *hw = &dc->hw;
+
+ dc_write(hw, hw->reg[id].src_global_color + offset, PRIMARY_ALPHA_LEN(alpha >> 8));
+ dc_write(hw, hw->reg[id].dst_global_color + offset, PRIMARY_ALPHA_LEN(alpha >> 8));
+ switch (pixel_blend_mode) {
+ case DRM_MODE_BLEND_PREMULTI:
+ dc_write(hw, hw->reg[id].blend_config + offset, BLEND_PREMULTI);
+ break;
+ case DRM_MODE_BLEND_COVERAGE:
+ dc_write(hw, hw->reg[id].blend_config + offset, BLEND_COVERAGE);
+ break;
+ case DRM_MODE_BLEND_PIXEL_NONE:
+ dc_write(hw, hw->reg[id].blend_config + offset, BLEND_PIXEL_NONE);
+ break;
+ default:
+ break;
+ }
+}
diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.h b/drivers/gpu/drm/verisilicon/vs_dc_hw.h
new file mode 100644
index 000000000000..63d8d153f57f
--- /dev/null
+++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.h
@@ -0,0 +1,493 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
+ */
+
+#ifndef __VS_DC_HW_H__
+#define __VS_DC_HW_H__
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <drm/drm_atomic.h>
+
+#include "vs_type.h"
+
+#define UPDATE(x, h, l) FIELD_PREP(GENMASK(h, l), x)
+
+#define AQ_INTR_ACKNOWLEDGE 0x0010
+#define AQ_INTR_ENBL 0x0014
+#define DC_HW_REVISION 0x0024
+#define DC_HW_CHIP_CID 0x0030
+
+#define DC_REG_BASE 0x0800
+#define DC_REG_RANGE 0x2000
+#define DC_SEC_REG_OFFSET 0x100000
+
+#define DC_FRAMEBUFFER_CONFIG 0x1518
+# define PRIMARY_FORMAT(x) ((x) << 26)
+# define PRIMARY_FORMAT_MASK GENMASK(31, 26)
+# define PRIMARY_UV_SWIZ(x) ((x) << 25)
+# define PRIMARY_UV_SWIZ_MASK GENMASK(25, 25)
+# define PRIMARY_SWIZ(x) ((x) << 23)
+# define PRIMARY_SWIZ_MASK GENMASK(24, 23)
+# define PRIMARY_SCALE_EN BIT(12)
+# define PRIMARY_TILE(x) ((x) << 17)
+# define PRIMARY_TILE_MASK GENMASK(21, 17)
+# define PRIMARY_YUV_COLOR(x) ((x) << 14)
+# define PRIMARY_YUV_COLOR_MASK GENMASK(16, 14)
+# define PRIMARY_ROTATION(x) ((x) << 11)
+# define PRIMARY_ROTATION_MASK GENMASK(13, 11)
+# define PRIMARY_CLEAR_EN(x) ((x) << 8)
+# define PRIMARY_CLEAR_EN_MASK GENMASK(8, 8)
+
+#define DC_FRAMEBUFFER_CONFIG_EX 0x1CC0
+# define PRIMARY_CHANNEL(x) ((x) << 19)
+# define PRIMARY_CHANNEL_MASK GENMASK(19, 19)
+# define PRIMARY_ZPOS(x) ((x) << 16)
+# define PRIMARY_ZPOS_MASK GENMASK(18, 16)
+# define PRIMARY_EN(x) ((x) << 13)
+# define PRIMARY_EN_MASK GENMASK(13, 13)
+# define PRIMARY_SHADOW_EN BIT(12)
+# define PRIMARY_YUVCLAMP_EN BIT(8)
+# define PRIMARY_RGB2RGB_EN BIT(6)
+# define PRIMARY_SYNC1_EN BIT(4)
+# define PRIMARY_SYNC0_EN BIT(3)
+# define PRIMARY_DECODER_EN(x) ((x) << 1)
+# define PRIMARY_DECODER_EN_EN_MASK GENMASK(1, 1)
+
+#define DC_FRAMEBUFFER_SCALE_CONFIG 0x1520
+#define DC_FRAMEBUFFER_TOP_LEFT 0x24D8
+#define X_POS(x) (x)
+#define Y_POS(x) ((x) << 15)
+
+#define DC_FRAMEBUFFER_BOTTOM_RIGHT 0x24E0
+#define DC_FRAMEBUFFER_ADDRESS 0x1400
+#define DC_FRAMEBUFFER_U_ADDRESS 0x1530
+#define DC_FRAMEBUFFER_V_ADDRESS 0x1538
+#define DC_FRAMEBUFFER_STRIDE 0x1408
+#define DC_FRAMEBUFFER_U_STRIDE 0x1800
+#define DC_FRAMEBUFFER_V_STRIDE 0x1808
+#define DC_FRAMEBUFFER_SIZE 0x1810
+#define FB_SIZE(w, h) ((w) | ((h) << 15))
+
+#define DC_FRAMEBUFFER_SCALE_FACTOR_X 0x1828
+#define DC_FRAMEBUFFER_SCALE_FACTOR_Y 0x1830
+#define DC_FRAMEBUFFER_H_FILTER_COEF_INDEX 0x1838
+#define DC_FRAMEBUFFER_H_FILTER_COEF_DATA 0x1A00
+#define DC_FRAMEBUFFER_V_FILTER_COEF_INDEX 0x1A08
+#define DC_FRAMEBUFFER_V_FILTER_COEF_DATA 0x1A10
+#define DC_FRAMEBUFFER_INIT_OFFSET 0x1A20
+#define DC_FRAMEBUFFER_COLOR_KEY 0x1508
+#define DC_FRAMEBUFFER_COLOR_KEY_HIGH 0x1510
+#define DC_FRAMEBUFFER_CLEAR_VALUE 0x1A18
+#define DC_FRAMEBUFFER_COLOR_TABLE_INDEX 0x1818
+#define DC_FRAMEBUFFER_COLOR_TABLE_DATA 0x1820
+#define DC_FRAMEBUFFER_BG_COLOR 0x1528
+#define DC_FRAMEBUFFER_ROI_ORIGIN 0x1CB0
+#define DC_FRAMEBUFFER_ROI_SIZE 0x1CB8
+#define DC_FRAMEBUFFER_WATER_MARK 0x1CE8
+#define DC_FRAMEBUFFER_DEGAMMA_INDEX 0x1D88
+#define DC_FRAMEBUFFER_DEGAMMA_DATA 0x1D90
+#define DC_FRAMEBUFFER_DEGAMMA_EX_DATA 0x1D98
+#define DC_FRAMEBUFFER_YUVTORGB_COEF0 0x1DA0
+#define DC_FRAMEBUFFER_YUVTORGB_COEF1 0x1DA8
+#define DC_FRAMEBUFFER_YUVTORGB_COEF2 0x1DB0
+#define DC_FRAMEBUFFER_YUVTORGB_COEF3 0x1DB8
+#define DC_FRAMEBUFFER_YUVTORGB_COEF4 0x1E00
+#define DC_FRAMEBUFFER_YUVTORGB_COEFD0 0x1E08
+#define DC_FRAMEBUFFER_YUVTORGB_COEFD1 0x1E10
+#define DC_FRAMEBUFFER_YUVTORGB_COEFD2 0x1E18
+#define DC_FRAMEBUFFER_Y_CLAMP_BOUND 0x1E88
+#define DC_FRAMEBUFFER_UV_CLAMP_BOUND 0x1E90
+#define DC_FRAMEBUFFER_RGBTORGB_COEF0 0x1E20
+#define DC_FRAMEBUFFER_RGBTORGB_COEF1 0x1E28
+#define DC_FRAMEBUFFER_RGBTORGB_COEF2 0x1E30
+#define DC_FRAMEBUFFER_RGBTORGB_COEF3 0x1E38
+#define DC_FRAMEBUFFER_RGBTORGB_COEF4 0x1E40
+#define DC_FRAMEBUFFER_BLEND_CONFIG 0x2510
+# define BLEND_PREMULTI 0x3450
+# define BLEND_COVERAGE 0x3950
+# define BLEND_PIXEL_NONE 0x3548
+
+#define DC_FRAMEBUFFER_SRC_GLOBAL_COLOR 0x2500
+# define PRIMARY_ALPHA_LEN(x) ((x) << 24)
+
+#define DC_FRAMEBUFFER_DST_GLOBAL_COLOR 0x2508
+
+#define DC_OVERLAY_CONFIG 0x1540
+# define OVERLAY_SHADOW_EN BIT(31)
+# define OVERLAY_CLAMP_EN BIT(30)
+# define OVERLAY_RGB2RGB_EN BIT(29)
+# define OVERLAY_DEC_EN(x) ((x) << 27)
+# define OVERLAY_DEC_EN_MASK GENMASK(27, 27)
+# define OVERLAY_CLEAR_EN(x) ((x) << 25)
+# define OVERLAY_CLEAR_EN_MASK GENMASK(25, 25)
+# define OVERLAY_FB_EN(x) ((x) << 24)
+# define OVERLAY_FB_EN_MASK GENMASK(24, 24)
+# define OVERLAY_FORMAT(x) ((x) << 16)
+# define OVERLAY_FORMAT_MASK GENMASK(21, 16)
+# define OVERLAY_UV_SWIZ(x) ((x) << 15)
+# define OVERLAY_UV_SWIZ_MASK GENMASK(15, 15)
+# define OVERLAY_SWIZ(x) ((x) << 13)
+# define OVERLAY_SWIZ_MASK GENMASK(14, 13)
+# define OVERLAY_TILE(x) ((x) << 8)
+# define OVERLAY_TILE_MASK GENMASK(12, 8)
+# define OVERLAY_YUV_COLOR(x) ((x) << 5)
+# define OVERLAY_YUV_COLOR_MASK GENMASK(7, 5)
+# define OVERLAY_ROTATION(x) ((x) << 2)
+# define OVERLAY_ROTATION_MASK GENMASK(4, 2)
+
+#define DC_OVERLAY_CONFIG_EX 0x2540
+# define OVERLAY_LAYER_SEL(x) ((x) << 0)
+# define OVERLAY_LAYER_SEL_MASK GENMASK(2, 0)
+# define OVERLAY_PANEL_SEL(x) ((x) << 3)
+# define OVERLAY_PANEL_SEL_MASK GENMASK(3, 3)
+
+#define DC_OVERLAY_SCALE_CONFIG 0x1C00
+# define OVERLAY_SCALE_EN BIT(8)
+
+#define DC_OVERLAY_BLEND_CONFIG 0x1580
+#define DC_OVERLAY_TOP_LEFT 0x1640
+#define DC_OVERLAY_BOTTOM_RIGHT 0x1680
+#define DC_OVERLAY_ADDRESS 0x15C0
+#define DC_OVERLAY_U_ADDRESS 0x1840
+#define DC_OVERLAY_V_ADDRESS 0x1880
+#define DC_OVERLAY_STRIDE 0x1600
+#define DC_OVERLAY_U_STRIDE 0x18C0
+#define DC_OVERLAY_V_STRIDE 0x1900
+#define DC_OVERLAY_SIZE 0x17C0
+#define DC_OVERLAY_SCALE_FACTOR_X 0x1A40
+#define DC_OVERLAY_SCALE_FACTOR_Y 0x1A80
+#define DC_OVERLAY_H_FILTER_COEF_INDEX 0x1AC0
+#define DC_OVERLAY_H_FILTER_COEF_DATA 0x1B00
+#define DC_OVERLAY_V_FILTER_COEF_INDEX 0x1B40
+#define DC_OVERLAY_V_FILTER_COEF_DATA 0x1B80
+#define DC_OVERLAY_INIT_OFFSET 0x1BC0
+#define DC_OVERLAY_COLOR_KEY 0x1740
+#define DC_OVERLAY_COLOR_KEY_HIGH 0x1780
+#define DC_OVERLAY_CLEAR_VALUE 0x1940
+#define DC_OVERLAY_COLOR_TABLE_INDEX 0x1980
+#define DC_OVERLAY_COLOR_TABLE_DATA 0x19C0
+#define DC_OVERLAY_SRC_GLOBAL_COLOR 0x16C0
+# define OVERLAY_ALPHA_LEN(x) ((x) << 24)
+
+#define DC_OVERLAY_DST_GLOBAL_COLOR 0x1700
+#define DC_OVERLAY_ROI_ORIGIN 0x1D00
+#define DC_OVERLAY_ROI_SIZE 0x1D40
+#define DC_OVERLAY_WATER_MARK 0x1DC0
+#define DC_OVERLAY_DEGAMMA_INDEX 0x2200
+#define DC_OVERLAY_DEGAMMA_DATA 0x2240
+#define DC_OVERLAY_DEGAMMA_EX_DATA 0x2280
+#define DC_OVERLAY_YUVTORGB_COEF0 0x1EC0
+#define DC_OVERLAY_YUVTORGB_COEF1 0x1F00
+#define DC_OVERLAY_YUVTORGB_COEF2 0x1F40
+#define DC_OVERLAY_YUVTORGB_COEF3 0x1F80
+#define DC_OVERLAY_YUVTORGB_COEF4 0x1FC0
+#define DC_OVERLAY_YUVTORGB_COEFD0 0x2000
+#define DC_OVERLAY_YUVTORGB_COEFD1 0x2040
+#define DC_OVERLAY_YUVTORGB_COEFD2 0x2080
+#define DC_OVERLAY_Y_CLAMP_BOUND 0x22C0
+#define DC_OVERLAY_UV_CLAMP_BOUND 0x2300
+#define DC_OVERLAY_RGBTORGB_COEF0 0x20C0
+#define DC_OVERLAY_RGBTORGB_COEF1 0x2100
+#define DC_OVERLAY_RGBTORGB_COEF2 0x2140
+#define DC_OVERLAY_RGBTORGB_COEF3 0x2180
+#define DC_OVERLAY_RGBTORGB_COEF4 0x21C0
+
+#define DC_CURSOR_CONFIG 0x1468
+# define CURSOR_HOT_X(x) ((x) << 16)
+# define CURSOR_HOT_X_MASK GENMASK(23, 16)
+# define CURSOR_HOT_y(x) ((x) << 8)
+# define CURSOR_HOT_y_MASK GENMASK(15, 8)
+# define CURSOR_SIZE(x) ((x) << 5)
+# define CURSOR_SIZE_MASK GENMASK(7, 5)
+# define CURSOR_VALID(x) ((x) << 3)
+# define CURSOR_VALID_MASK GENMASK(3, 3)
+# define CURSOR_TRIG_FETCH(x) ((x) << 2)
+# define CURSOR_TRIG_FETCH_MASK GENMASK(2, 2)
+# define CURSOR_FORMAT(x) ((x) << 0)
+# define CURSOR_FORMAT_MASK GENMASK(1, 0)
+# define CURSOR_FORMAT_DISABLE 0
+# define CURSOR_FORMAT_MARK 1
+# define CURSOR_FORMAT_A8R8G8B8 2
+
+#define DC_CURSOR_ADDRESS 0x146C
+#define DC_CURSOR_LOCATION 0x1470
+# define X_LCOTION(x) (x)
+# define Y_LCOTION(x) ((x) << 16)
+
+#define DC_CURSOR_BACKGROUND 0x1474
+#define DC_CURSOR_FOREGROUND 0x1478
+#define DC_CURSOR_CLK_GATING 0x1484
+#define DC_CURSOR_CONFIG_EX 0x24E8
+#define DC_CURSOR_OFFSET 0x1080
+
+#define DC_DISPLAY_DITHER_CONFIG 0x1410
+#define DC_DISPLAY_PANEL_CONFIG 0x1418
+# define PANEL_RGB2YUV_EN BIT(16)
+# define PANEL_GAMMA_EN BIT(13)
+# define PANEL_OUTPUT_EN BIT(12)
+
+#define DC_DISPLAY_PANEL_CONFIG_EX 0x2518
+# define PANEL_SHADOW_EN BIT(0)
+
+#define DC_DISPLAY_DITHER_TABLE_LOW 0x1420
+#define DC_DISPLAY_DITHER_TABLE_HIGH 0x1428
+#define DC_DISPLAY_H 0x1430
+# define H_ACTIVE_LEN(x) (x)
+# define H_TOTAL_LEN(x) ((x) << 16)
+
+#define DC_DISPLAY_H_SYNC 0x1438
+# define H_SYNC_START_LEN(x) (x)
+# define H_SYNC_END_LEN(x) ((x) << 15)
+# define H_PLUS_LEN(x) ((x) << 30)
+# define H_POLARITY_LEN(x) ((x) << 31)
+
+#define DC_DISPLAY_V 0x1440
+# define V_ACTIVE_LEN(x) (x)
+# define V_TOTAL_LEN(x) ((x) << 16)
+
+#define DC_DISPLAY_V_SYNC 0x1448
+# define V_SYNC_START_LEN(x) (x)
+# define V_SYNC_END_LEN(x) ((x) << 15)
+# define V_PLUS_LEN(x) ((x) << 30)
+# define V_POLARITY_LEN(x) ((x) << 31)
+
+#define DC_DISPLAY_CURRENT_LOCATION 0x1450
+#define DC_DISPLAY_GAMMA_INDEX 0x1458
+#define DC_DISPLAY_GAMMA_DATA 0x1460
+#define DC_DISPLAY_INT 0x147C
+#define DC_DISPLAY_INT_ENABLE 0x1480
+#define DC_DISPLAY_DBI_CONFIG 0x1488
+#define DC_DISPLAY_GENERAL_CONFIG 0x14B0
+#define DC_DISPLAY_DPI_CONFIG 0x14B8
+#define DC_DISPLAY_PANEL_START 0x1CCC
+# define PANEL0_EN BIT(0)
+# define PANEL1_EN BIT(1)
+# define TWO_PANEL_EN BIT(2)
+# define SYNC_EN BIT(3)
+
+#define DC_DISPLAY_DEBUG_COUNTER_SELECT 0x14D0
+#define DC_DISPLAY_DEBUG_COUNTER_VALUE 0x14D8
+#define DC_DISPLAY_DP_CONFIG 0x1CD0
+# define DP_SELECT BIT(3)
+
+#define DC_DISPLAY_GAMMA_EX_INDEX 0x1CF0
+#define DC_DISPLAY_GAMMA_EX_DATA 0x1CF8
+#define DC_DISPLAY_GAMMA_EX_ONE_DATA 0x1D80
+#define DC_DISPLAY_RGBTOYUV_COEF0 0x1E48
+#define DC_DISPLAY_RGBTOYUV_COEF1 0x1E50
+#define DC_DISPLAY_RGBTOYUV_COEF2 0x1E58
+#define DC_DISPLAY_RGBTOYUV_COEF3 0x1E60
+#define DC_DISPLAY_RGBTOYUV_COEF4 0x1E68
+#define DC_DISPLAY_RGBTOYUV_COEFD0 0x1E70
+#define DC_DISPLAY_RGBTOYUV_COEFD1 0x1E78
+#define DC_DISPLAY_RGBTOYUV_COEFD2 0x1E80
+
+#define DC_CLK_GATTING 0x1A28
+#define DC_QOS_CONFIG 0x1A38
+
+#define DC_TRANSPARENCY_OPAQUE 0x00
+#define DC_TRANSPARENCY_KEY 0x02
+#define DC_DISPLAY_DITHERTABLE_LOW 0x7B48F3C0
+#define DC_DISPLAY_DITHERTABLE_HIGH 0x596AD1E2
+
+#define DC_TILE_MODE4X4 0x15
+
+#define GAMMA_SIZE 256
+#define GAMMA_EX_SIZE 300
+#define DEGAMMA_SIZE 260
+
+#define RGB_TO_RGB_TABLE_SIZE 9
+#define YUV_TO_RGB_TABLE_SIZE 16
+#define RGB_TO_YUV_TABLE_SIZE 12
+
+#define DC_LAYER_NUM 6
+#define DC_DISPLAY_NUM 2
+#define DC_CURSOR_NUM 2
+
+enum dc_hw_plane_id {
+ PRIMARY_PLANE_0,
+ OVERLAY_PLANE_0,
+ OVERLAY_PLANE_1,
+ PRIMARY_PLANE_1,
+ OVERLAY_PLANE_2,
+ OVERLAY_PLANE_3,
+ CURSOR_PLANE_0,
+ CURSOR_PLANE_1,
+ PLANE_NUM
+};
+
+enum dc_hw_color_format {
+ FORMAT_X4R4G4B4,
+ FORMAT_A4R4G4B4,
+ FORMAT_X1R5G5B5,
+ FORMAT_A1R5G5B5,
+ FORMAT_R5G6B5,
+ FORMAT_X8R8G8B8,
+ FORMAT_A8R8G8B8,
+ FORMAT_YUY2,
+ FORMAT_UYVY,
+ FORMAT_INDEX8,
+ FORMAT_MONOCHROME,
+ FORMAT_YV12 = 0xf,
+ FORMAT_A8,
+ FORMAT_NV12,
+ FORMAT_NV16,
+ FORMAT_RG16,
+ FORMAT_R8,
+ FORMAT_NV12_10BIT,
+ FORMAT_A2R10G10B10,
+ FORMAT_NV16_10BIT,
+ FORMAT_INDEX1,
+ FORMAT_INDEX2,
+ FORMAT_INDEX4,
+ FORMAT_P010,
+ FORMAT_YUV444,
+ FORMAT_YUV444_10BIT,
+};
+
+enum dc_hw_yuv_color_space {
+ COLOR_SPACE_601 = 0,
+ COLOR_SPACE_709 = 1,
+ COLOR_SPACE_2020 = 3,
+};
+
+enum dc_hw_rotation {
+ ROT_0 = 0,
+ ROT_90 = 4,
+ ROT_180 = 5,
+ ROT_270 = 6,
+ FLIP_X = 1,
+ FLIP_Y = 2,
+ FLIP_XY = 3,
+};
+
+enum dc_hw_swizzle {
+ SWIZZLE_ARGB = 0,
+ SWIZZLE_RGBA,
+ SWIZZLE_ABGR,
+ SWIZZLE_BGRA,
+};
+
+enum dc_hw_out {
+ OUT_DPI,
+ OUT_DP,
+};
+
+enum dc_hw_cursor_size {
+ CURSOR_SIZE_32X32 = 0,
+ CURSOR_SIZE_64X64,
+};
+
+struct dc_hw_plane_reg {
+ u32 y_address;
+ u32 u_address;
+ u32 v_address;
+ u32 y_stride;
+ u32 u_stride;
+ u32 v_stride;
+ u32 size;
+ u32 top_left;
+ u32 bottom_right;
+ u32 scale_factor_x;
+ u32 scale_factor_y;
+ u32 h_filter_coef_index;
+ u32 h_filter_coef_data;
+ u32 v_filter_coef_index;
+ u32 v_filter_coef_data;
+ u32 init_offset;
+ u32 color_key;
+ u32 color_key_high;
+ u32 clear_value;
+ u32 color_table_index;
+ u32 color_table_data;
+ u32 scale_config;
+ u32 water_mark;
+ u32 degamma_index;
+ u32 degamma_data;
+ u32 degamma_ex_data;
+ u32 src_global_color;
+ u32 dst_global_color;
+ u32 blend_config;
+ u32 roi_origin;
+ u32 roi_size;
+ u32 yuv_to_rgb_coef0;
+ u32 yuv_to_rgb_coef1;
+ u32 yuv_to_rgb_coef2;
+ u32 yuv_to_rgb_coef3;
+ u32 yuv_to_rgb_coef4;
+ u32 yuv_to_rgb_coefd0;
+ u32 yuv_to_rgb_coefd1;
+ u32 yuv_to_rgb_coefd2;
+ u32 y_clamp_bound;
+ u32 uv_clamp_bound;
+ u32 rgb_to_rgb_coef0;
+ u32 rgb_to_rgb_coef1;
+ u32 rgb_to_rgb_coef2;
+ u32 rgb_to_rgb_coef3;
+ u32 rgb_to_rgb_coef4;
+};
+
+struct dc_hw_gamma {
+ u16 gamma[GAMMA_EX_SIZE][3];
+};
+
+struct dc_hw_read {
+ u32 reg;
+ u32 value;
+};
+
+struct dc_hw {
+ enum dc_hw_out out[DC_DISPLAY_NUM];
+ void *hi_base;
+ void *reg_base;
+ struct dc_hw_plane_reg reg[DC_LAYER_NUM];
+
+ struct dc_hw_gamma gamma[DC_DISPLAY_NUM];
+ struct vs_dc_info *info;
+};
+
+struct vs_dc_plane {
+ enum dc_hw_plane_id id;
+ u32 offset;
+};
+
+struct vs_dc {
+ struct vs_crtc *crtc[DC_DISPLAY_NUM];
+ struct dc_hw hw;
+
+ struct vs_dc_plane planes[PLANE_NUM];
+};
+
+int dc_hw_init(struct vs_dc *dc);
+void dc_hw_disable_plane(struct vs_dc *dc, u8 id);
+void dc_hw_update_cursor(struct dc_hw *hw, u8 id, dma_addr_t dma_addr,
+ u32 crtc_w, u32 crtc_x, u32 crtc_y,
+ s32 hotspot_x, int32_t hotspot_y);
+void dc_hw_disable_cursor(struct dc_hw *hw, u8 id);
+void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index,
+ u16 r, u16 g, u16 b);
+void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable);
+void dc_hw_enable(struct dc_hw *hw, int id, struct drm_display_mode *mode,
+ u8 encoder_type, u32 output_fmt);
+void dc_hw_disable(struct dc_hw *hw, int id);
+void dc_hw_enable_interrupt(struct dc_hw *hw);
+void dc_hw_disable_interrupt(struct dc_hw *hw);
+u32 dc_hw_get_interrupt(struct dc_hw *hw);
+void dc_hw_enable_shadow_register(struct vs_dc *dc, bool enable);
+void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id);
+void dc_hw_commit(struct dc_hw *hw);
+void plane_hw_update_format_colorspace(struct vs_dc *dc, u32 format,
+ enum drm_color_encoding encoding, u8 id, bool is_yuv);
+void plane_hw_update_address(struct vs_dc *dc, u8 id, u32 format, dma_addr_t *dma_addr,
+ struct drm_framebuffer *drm_fb, struct drm_rect *src);
+void plane_hw_update_format(struct vs_dc *dc, u32 format, enum drm_color_encoding encoding,
+ unsigned int rotation, bool visible, unsigned int zpos,
+ u8 id, u8 display_id);
+void plane_hw_update_scale(struct vs_dc *dc, struct drm_rect *src, struct drm_rect *dst,
+ u8 id, u8 display_id, unsigned int rotation);
+void plane_hw_update_blend(struct vs_dc *dc, u16 alpha, u16 pixel_blend_mode,
+ u8 id, u8 display_id);
+
+#endif /* __VS_DC_HW_H__ */
diff --git a/drivers/gpu/drm/verisilicon/vs_type.h b/drivers/gpu/drm/verisilicon/vs_type.h
new file mode 100644
index 000000000000..30ccc2eda48b
--- /dev/null
+++ b/drivers/gpu/drm/verisilicon/vs_type.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
+ */
+
+#ifndef __VS_TYPE_H__
+#define __VS_TYPE_H__
+
+#include <drm/drm_plane.h>
+
+struct vs_plane_primary_info {
+ u8 id;
+ unsigned int num_formats;
+ const u32 *formats;
+ u8 num_modifiers;
+ const u64 *modifiers;
+ unsigned int min_width;
+ unsigned int min_height;
+ unsigned int max_width;
+ unsigned int max_height;
+ unsigned int rotation;
+ unsigned int color_encoding;
+
+ int min_scale; /* 16.16 fixed point */
+ int max_scale; /* 16.16 fixed point */
+
+ u8 zpos;
+
+};
+
+struct vs_plane_overlay_info {
+ u8 id;
+ unsigned int num_formats;
+ const u32 *formats;
+ u8 num_modifiers;
+ const u64 *modifiers;
+ unsigned int min_width;
+ unsigned int min_height;
+ unsigned int max_width;
+ unsigned int max_height;
+ unsigned int rotation;
+ unsigned int color_encoding;
+
+ int min_scale; /* 16.16 fixed point */
+ int max_scale; /* 16.16 fixed point */
+
+ u8 zpos;
+
+};
+
+struct vs_plane_cursor_info {
+ u8 id;
+ unsigned int num_formats;
+ const u32 *formats;
+ unsigned int min_width;
+ unsigned int min_height;
+ unsigned int max_width;
+ unsigned int max_height;
+ u8 zpos;
+
+};
+
+struct vs_dc_info {
+ const char *name;
+
+ u8 panel_num;
+
+ /* planes */
+ u8 layer_num;
+ u8 primary_num;
+ u8 overlay_num;
+ u8 cursor_num;
+ const struct vs_plane_primary_info *primary;
+ const struct vs_plane_overlay_info *overlay;
+ const struct vs_plane_cursor_info *cursor;
+
+ /* 0 means no gamma LUT */
+ u16 gamma_size;
+ u8 gamma_bits;
+
+ u16 pitch_alignment;
+};
+
+#endif /* __VS_TYPE_H__ */
--
2.27.0
Add the ROCKCHIP inno hdmi driver that uses the Inno DesignWare
HDMI TX bridge and remove the old separate one.
Signed-off-by: keith <[email protected]>
---
drivers/gpu/drm/rockchip/Kconfig | 1 +
drivers/gpu/drm/rockchip/Makefile | 2 +-
drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 517 ++++++++
.../{inno_hdmi.h => inno_hdmi-rockchip.h} | 45 -
drivers/gpu/drm/rockchip/inno_hdmi.c | 1073 -----------------
5 files changed, 519 insertions(+), 1119 deletions(-)
create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
rename drivers/gpu/drm/rockchip/{inno_hdmi.h => inno_hdmi-rockchip.h} (85%)
delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 1bf3e2829cd0..cc6cfd5a30d6 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -74,6 +74,7 @@ config ROCKCHIP_DW_MIPI_DSI
config ROCKCHIP_INNO_HDMI
bool "Rockchip specific extensions for Innosilicon HDMI"
+ select DRM_INNO_HDMI
help
This selects support for Rockchip SoC specific extensions
for the Innosilicon HDMI driver. If you want to enable
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index 3ff7b21c0414..4b2d0cba8db3 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -12,7 +12,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
-rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
+rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi-rockchip.o
rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o
rockchipdrm-$(CONFIG_ROCKCHIP_RK3066_HDMI) += rk3066_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
new file mode 100644
index 000000000000..69d0e913e13b
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
@@ -0,0 +1,517 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Zheng Yang <[email protected]>
+ * Yakir Yang <[email protected]>
+ */
+
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/hdmi.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+#include <drm/bridge/inno_hdmi.h>
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_of.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "rockchip_drm_drv.h"
+
+#include "inno_hdmi-rockchip.h"
+
+#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
+
+struct rk_inno_hdmi {
+ struct rockchip_encoder encoder;
+ struct inno_hdmi inno_hdmi;
+ struct clk *pclk;
+ struct clk *refclk;
+};
+
+static struct inno_hdmi *rk_encoder_to_inno_hdmi(struct drm_encoder *encoder)
+{
+ struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
+ struct rk_inno_hdmi *rk_hdmi = container_of(rkencoder, struct rk_inno_hdmi, encoder);
+
+ return &rk_hdmi->inno_hdmi;
+}
+
+enum {
+ CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
+ CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
+ CSC_RGB_0_255_TO_RGB_16_235_8BIT,
+};
+
+static const char coeff_csc[][24] = {
+ /*
+ * RGB2YUV:601 SD mode:
+ * Cb = -0.291G - 0.148R + 0.439B + 128
+ * Y = 0.504G + 0.257R + 0.098B + 16
+ * Cr = -0.368G + 0.439R - 0.071B + 128
+ */
+ {
+ 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
+ 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
+ 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
+ },
+ /*
+ * RGB2YUV:709 HD mode:
+ * Cb = - 0.338G - 0.101R + 0.439B + 128
+ * Y = 0.614G + 0.183R + 0.062B + 16
+ * Cr = - 0.399G + 0.439R - 0.040B + 128
+ */
+ {
+ 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
+ 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
+ 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
+ },
+ /*
+ * RGB[0:255]2RGB[16:235]:
+ * R' = R x (235-16)/255 + 16;
+ * G' = G x (235-16)/255 + 16;
+ * B' = B x (235-16)/255 + 16;
+ */
+ {
+ 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
+ 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
+ },
+};
+
+static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
+ { 74250000, 0x3f, 0xbb },
+ { 165000000, 0x6f, 0xbb },
+ { ~0UL, 0x00, 0x00 }
+};
+
+static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
+ { 74250000, 0x3f, 0xaa },
+ { 165000000, 0x5f, 0xaa },
+ { ~0UL, 0x00, 0x00 }
+};
+
+static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
+ unsigned long pixelclk)
+{
+ const struct inno_hdmi_phy_config *phy_configs = hdmi->plat_data->phy_configs;
+ int i;
+
+ for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
+ if (pixelclk <= phy_configs[i].pixelclock)
+ return i;
+ }
+
+ DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
+ pixelclk);
+
+ return -EINVAL;
+}
+
+static void inno_hdmi_standby(struct inno_hdmi *hdmi)
+{
+ inno_hdmi_sys_power(hdmi, false);
+
+ hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
+};
+
+static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
+ unsigned long mpixelclock)
+{
+ struct inno_hdmi_phy_config *phy_config;
+ int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
+
+ if (ret < 0) {
+ phy_config = hdmi->plat_data->default_phy_config;
+ DRM_DEV_ERROR(hdmi->dev,
+ "Using default phy configuration for TMDS rate %lu",
+ mpixelclock);
+ } else {
+ phy_config = &hdmi->plat_data->phy_configs[ret];
+ }
+
+ inno_hdmi_sys_power(hdmi, false);
+
+ hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
+ hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
+ hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
+ hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
+ hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
+ hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
+
+ inno_hdmi_sys_power(hdmi, true);
+};
+
+static void inno_hdmi_reset(struct inno_hdmi *hdmi)
+{
+ u32 val;
+ u32 msk;
+
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
+ udelay(100);
+
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
+ udelay(100);
+
+ msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
+ val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
+ hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
+
+ inno_hdmi_standby(hdmi);
+}
+
+static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
+{
+ struct drm_connector *connector = &hdmi->connector;
+ struct drm_connector_state *conn_state = connector->state;
+ struct inno_hdmi_connector_state *inno_conn_state =
+ to_inno_hdmi_conn_state(conn_state);
+ int c0_c2_change = 0;
+ int csc_enable = 0;
+ int csc_mode = 0;
+ int auto_csc = 0;
+ int value;
+ int i;
+
+ /* Input video mode is SDR RGB24bit, data enable signal from external */
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
+ v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
+
+ /* Input color hardcode to RGB, and output color hardcode to RGB888 */
+ value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
+ v_VIDEO_OUTPUT_COLOR(0) |
+ v_VIDEO_INPUT_CSP(0);
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
+
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
+ if (inno_conn_state->rgb_limited_range) {
+ csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
+ auto_csc = AUTO_CSC_DISABLE;
+ c0_c2_change = C0_C2_CHANGE_DISABLE;
+ csc_enable = v_CSC_ENABLE;
+
+ } else {
+ value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
+
+ hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
+ m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
+ v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
+ v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
+ return 0;
+ }
+ } else {
+ if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
+ csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
+ auto_csc = AUTO_CSC_DISABLE;
+ c0_c2_change = C0_C2_CHANGE_DISABLE;
+ csc_enable = v_CSC_ENABLE;
+ }
+ } else {
+ if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
+ csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
+ auto_csc = AUTO_CSC_DISABLE;
+ c0_c2_change = C0_C2_CHANGE_DISABLE;
+ csc_enable = v_CSC_ENABLE;
+ }
+ }
+ }
+
+ for (i = 0; i < 24; i++)
+ hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
+ coeff_csc[csc_mode][i]);
+
+ value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
+ hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
+ hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
+ m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
+ v_VIDEO_C0_C2_SWAP(c0_c2_change));
+
+ return 0;
+}
+
+static int inno_hdmi_setup(struct inno_hdmi *hdmi,
+ struct drm_display_mode *mode)
+{
+ struct drm_display_info *display = &hdmi->connector.display_info;
+ unsigned long mpixelclock = mode->clock * 1000;
+
+ /* Mute video and audio output */
+ hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
+ v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
+
+ /* Set HDMI Mode */
+ hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
+ v_HDMI_DVI(display->is_hdmi));
+
+ inno_hdmi_config_video_timing(hdmi, mode);
+
+ inno_hdmi_config_video_csc(hdmi);
+
+ if (display->is_hdmi)
+ inno_hdmi_config_video_avi(hdmi, mode);
+
+ /*
+ * When IP controller have configured to an accurate video
+ * timing, then the TMDS clock source would be switched to
+ * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
+ * clock rate, and reconfigure the DDC clock.
+ */
+ inno_hdmi_i2c_init(hdmi, mpixelclock);
+
+ /* Unmute video and audio output */
+ hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
+ v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
+
+ inno_hdmi_power_up(hdmi, mpixelclock);
+
+ return 0;
+}
+
+static enum drm_mode_status rk_inno_hdmi_connector_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode)
+{
+ struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
+ struct rk_inno_hdmi *rk_hdmi = dev_get_drvdata(hdmi->dev);
+
+ unsigned long mpixelclk, max_tolerance;
+ long rounded_refclk;
+
+ /* No support for double-clock modes */
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_BAD;
+
+ mpixelclk = mode->clock * 1000;
+
+ if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
+ return MODE_CLOCK_LOW;
+
+ if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
+ return MODE_CLOCK_HIGH;
+
+ if (rk_hdmi->refclk) {
+ rounded_refclk = clk_round_rate(rk_hdmi->refclk, mpixelclk);
+ if (rounded_refclk < 0)
+ return MODE_BAD;
+
+ /* Vesa DMT standard mentions +/- 0.5% max tolerance */
+ max_tolerance = mpixelclk / 200;
+ if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
+ return MODE_NOCLOCK;
+ }
+
+ return MODE_OK;
+}
+
+static void rk_inno_hdmi_encoder_enable(struct drm_encoder *encoder,
+ struct drm_atomic_state *state)
+{
+ struct inno_hdmi *hdmi = rk_encoder_to_inno_hdmi(encoder);
+ struct drm_connector_state *conn_state;
+ struct drm_crtc_state *crtc_state;
+
+ conn_state = drm_atomic_get_new_connector_state(state, &hdmi->connector);
+ if (WARN_ON(!conn_state))
+ return;
+
+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
+ if (WARN_ON(!crtc_state))
+ return;
+
+ inno_hdmi_setup(hdmi, &crtc_state->adjusted_mode);
+}
+
+static void rk_inno_hdmi_encoder_disable(struct drm_encoder *encoder,
+ struct drm_atomic_state *state)
+{
+ struct inno_hdmi *hdmi = rk_encoder_to_inno_hdmi(encoder);
+
+ inno_hdmi_standby(hdmi);
+}
+
+static int
+rk_inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_display_mode *mode = &crtc_state->adjusted_mode;
+ u8 vic = drm_match_cea_mode(mode);
+ struct inno_hdmi_connector_state *inno_conn_state =
+ to_inno_hdmi_conn_state(conn_state);
+
+ s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+
+ if (vic == 6 || vic == 7 ||
+ vic == 21 || vic == 22 ||
+ vic == 2 || vic == 3 ||
+ vic == 17 || vic == 18)
+ inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
+ else
+ inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
+
+ inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
+ inno_conn_state->rgb_limited_range =
+ drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
+
+ return rk_inno_hdmi_connector_mode_valid(conn_state->connector,
+ &crtc_state->adjusted_mode) == MODE_OK ? 0 : -EINVAL;
+}
+
+static const struct drm_encoder_helper_funcs rk_inno_encoder_helper_funcs = {
+ .atomic_check = rk_inno_hdmi_encoder_atomic_check,
+ .atomic_enable = rk_inno_hdmi_encoder_enable,
+ .atomic_disable = rk_inno_hdmi_encoder_disable,
+};
+
+static int rk_inno_hdmi_bind(struct device *dev, struct device *master, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct drm_device *drm = data;
+ struct inno_hdmi *hdmi;
+ int ret;
+ struct rk_inno_hdmi *rk_hdmi;
+
+ rk_hdmi = devm_kzalloc(dev, sizeof(*rk_hdmi), GFP_KERNEL);
+ if (!rk_hdmi)
+ return -ENOMEM;
+ hdmi = &rk_hdmi->inno_hdmi;
+
+ hdmi->dev = dev;
+ hdmi->plat_data = (struct inno_hdmi_plat_data *)of_device_get_match_data(dev);
+
+ hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(hdmi->regs))
+ return PTR_ERR(hdmi->regs);
+
+ rk_hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
+ if (IS_ERR(rk_hdmi->pclk)) {
+ DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
+ return PTR_ERR(rk_hdmi->pclk);
+ }
+
+ ret = clk_prepare_enable(rk_hdmi->pclk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev,
+ "Cannot enable HDMI pclk clock: %d\n", ret);
+ return ret;
+ }
+
+ rk_hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref");
+ if (IS_ERR(rk_hdmi->refclk)) {
+ DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n");
+ ret = PTR_ERR(rk_hdmi->refclk);
+ goto err_disable_pclk;
+ }
+
+ ret = clk_prepare_enable(rk_hdmi->refclk);
+ if (ret) {
+ DRM_DEV_ERROR(hdmi->dev,
+ "Cannot enable HDMI reference clock: %d\n", ret);
+ goto err_disable_pclk;
+ }
+
+ inno_hdmi_reset(hdmi);
+ /*
+ * When the controller isn't configured to an accurate
+ * video timing and there is no reference clock available,
+ * then the TMDS clock source would be switched to PCLK_HDMI,
+ * so we need to init the TMDS rate to PCLK rate, and
+ * reconfigure the DDC clock.
+ */
+ if (rk_hdmi->refclk)
+ inno_hdmi_i2c_init(hdmi, clk_get_rate(rk_hdmi->refclk));
+ else
+ inno_hdmi_i2c_init(hdmi, clk_get_rate(rk_hdmi->pclk));
+
+ ret = inno_hdmi_bind(drm, hdmi, &rk_hdmi->encoder.encoder);
+ if (ret)
+ goto err_cleanup_hdmi;
+
+ dev_set_drvdata(dev, rk_hdmi);
+
+ return 0;
+
+err_cleanup_hdmi:
+ rk_hdmi->encoder.encoder.funcs->destroy(&rk_hdmi->encoder.encoder);
+ clk_disable_unprepare(rk_hdmi->refclk);
+err_disable_pclk:
+ clk_disable_unprepare(rk_hdmi->pclk);
+ return ret;
+}
+
+static void rk_inno_hdmi_unbind(struct device *dev, struct device *master, void *data)
+{
+ struct rk_inno_hdmi *rk_hdmi = dev_get_drvdata(dev);
+ struct inno_hdmi *hdmi = &rk_hdmi->inno_hdmi;
+
+ rk_hdmi->encoder.encoder.funcs->destroy(&rk_hdmi->encoder.encoder);
+ i2c_put_adapter(hdmi->ddc);
+ clk_disable_unprepare(rk_hdmi->refclk);
+ clk_disable_unprepare(rk_hdmi->pclk);
+}
+
+static const struct component_ops inno_hdmi_ops = {
+ .bind = rk_inno_hdmi_bind,
+ .unbind = rk_inno_hdmi_unbind,
+};
+
+static int inno_hdmi_probe(struct platform_device *pdev)
+{
+ return component_add(&pdev->dev, &inno_hdmi_ops);
+}
+
+static void inno_hdmi_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &inno_hdmi_ops);
+}
+
+static const struct inno_hdmi_plat_data rk3036_inno_info = {
+ .soc_type = RK3036_HDMI,
+ .mode_valid = rk_inno_hdmi_connector_mode_valid,
+ .helper_private = &rk_inno_encoder_helper_funcs,
+ .phy_configs = rk3036_hdmi_phy_configs,
+ .default_phy_config = &rk3036_hdmi_phy_configs[1],
+};
+
+static const struct inno_hdmi_plat_data rk3128_inno_info = {
+ .soc_type = RK3128_HDMI,
+ .mode_valid = rk_inno_hdmi_connector_mode_valid,
+ .helper_private = &rk_inno_encoder_helper_funcs,
+ .phy_configs = rk3128_hdmi_phy_configs,
+ .default_phy_config = &rk3128_hdmi_phy_configs[1],
+};
+
+static const struct of_device_id inno_hdmi_dt_ids[] = {
+ { .compatible = "rockchip,rk3036-inno-hdmi",
+ .data = &rk3036_inno_info,
+ },
+ { .compatible = "rockchip,rk3128-inno-hdmi",
+ .data = &rk3128_inno_info,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
+
+struct platform_driver inno_hdmi_driver = {
+ .probe = inno_hdmi_probe,
+ .remove_new = inno_hdmi_remove,
+ .driver = {
+ .name = "innohdmi-rockchip",
+ .of_match_table = inno_hdmi_dt_ids,
+ },
+};
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.h b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h
similarity index 85%
rename from drivers/gpu/drm/rockchip/inno_hdmi.h
rename to drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h
index a7edf3559e60..c90458d75378 100644
--- a/drivers/gpu/drm/rockchip/inno_hdmi.h
+++ b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.h
@@ -8,12 +8,6 @@
#ifndef __INNO_HDMI_H__
#define __INNO_HDMI_H__
-#define DDC_SEGMENT_ADDR 0x30
-
-#define HDMI_SCL_RATE (100*1000)
-#define DDC_BUS_FREQ_L 0x4b
-#define DDC_BUS_FREQ_H 0x4c
-
#define HDMI_SYS_CTRL 0x00
#define m_RST_ANALOG (1 << 6)
#define v_RST_ANALOG (0 << 6)
@@ -98,26 +92,6 @@ enum {
#define v_AUDIO_MUTE(n) (n << 1)
#define v_VIDEO_MUTE(n) (n << 0)
-#define HDMI_VIDEO_TIMING_CTL 0x08
-#define v_HSYNC_POLARITY(n) (n << 3)
-#define v_VSYNC_POLARITY(n) (n << 2)
-#define v_INETLACE(n) (n << 1)
-#define v_EXTERANL_VIDEO(n) (n << 0)
-
-#define HDMI_VIDEO_EXT_HTOTAL_L 0x09
-#define HDMI_VIDEO_EXT_HTOTAL_H 0x0a
-#define HDMI_VIDEO_EXT_HBLANK_L 0x0b
-#define HDMI_VIDEO_EXT_HBLANK_H 0x0c
-#define HDMI_VIDEO_EXT_HDELAY_L 0x0d
-#define HDMI_VIDEO_EXT_HDELAY_H 0x0e
-#define HDMI_VIDEO_EXT_HDURATION_L 0x0f
-#define HDMI_VIDEO_EXT_HDURATION_H 0x10
-#define HDMI_VIDEO_EXT_VTOTAL_L 0x11
-#define HDMI_VIDEO_EXT_VTOTAL_H 0x12
-#define HDMI_VIDEO_EXT_VBLANK 0x13
-#define HDMI_VIDEO_EXT_VDELAY 0x14
-#define HDMI_VIDEO_EXT_VDURATION 0x15
-
#define HDMI_VIDEO_CSC_COEF 0x18
#define HDMI_AUDIO_CTRL1 0x35
@@ -202,14 +176,6 @@ enum {
#define HDMI_AUDIO_CTS_M 0x46
#define HDMI_AUDIO_CTS_L 0x47
-#define HDMI_DDC_CLK_L 0x4b
-#define HDMI_DDC_CLK_H 0x4c
-
-#define HDMI_EDID_SEGMENT_POINTER 0x4d
-#define HDMI_EDID_WORD_ADDR 0x4e
-#define HDMI_EDID_FIFO_OFFSET 0x4f
-#define HDMI_EDID_FIFO_ADDR 0x50
-
#define HDMI_PACKET_SEND_MANUAL 0x9c
#define HDMI_PACKET_SEND_AUTO 0x9d
#define m_PACKET_GCP_EN (1 << 7)
@@ -254,23 +220,12 @@ enum {
#define m_HDMI_DVI (1 << 1)
#define v_HDMI_DVI(n) (n << 1)
-#define HDMI_INTERRUPT_MASK1 0xc0
-#define HDMI_INTERRUPT_STATUS1 0xc1
-#define m_INT_ACTIVE_VSYNC (1 << 5)
-#define m_INT_EDID_READY (1 << 2)
-
#define HDMI_INTERRUPT_MASK2 0xc2
#define HDMI_INTERRUPT_STATUS2 0xc3
#define m_INT_HDCP_ERR (1 << 7)
#define m_INT_BKSV_FLAG (1 << 6)
#define m_INT_HDCP_OK (1 << 4)
-#define HDMI_STATUS 0xc8
-#define m_HOTPLUG (1 << 7)
-#define m_MASK_INT_HOTPLUG (1 << 5)
-#define m_INT_HOTPLUG (1 << 1)
-#define v_MASK_INT_HOTPLUG(n) ((n & 0x1) << 5)
-
#define HDMI_COLORBAR 0xc9
#define HDMI_PHY_SYNC 0xce
diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c
deleted file mode 100644
index 3df2cfcf9998..000000000000
--- a/drivers/gpu/drm/rockchip/inno_hdmi.c
+++ /dev/null
@@ -1,1073 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
- * Zheng Yang <[email protected]>
- * Yakir Yang <[email protected]>
- */
-
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/hdmi.h>
-#include <linux/mod_devicetable.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-
-#include <drm/drm_atomic.h>
-#include <drm/drm_atomic_helper.h>
-#include <drm/drm_edid.h>
-#include <drm/drm_of.h>
-#include <drm/drm_probe_helper.h>
-#include <drm/drm_simple_kms_helper.h>
-
-#include "rockchip_drm_drv.h"
-
-#include "inno_hdmi.h"
-
-#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
-
-struct inno_hdmi_phy_config {
- unsigned long pixelclock;
- u8 pre_emphasis;
- u8 voltage_level_control;
-};
-
-struct inno_hdmi_variant {
- struct inno_hdmi_phy_config *phy_configs;
- struct inno_hdmi_phy_config *default_phy_config;
-};
-
-struct inno_hdmi_i2c {
- struct i2c_adapter adap;
-
- u8 ddc_addr;
- u8 segment_addr;
-
- struct mutex lock;
- struct completion cmp;
-};
-
-struct inno_hdmi {
- struct device *dev;
-
- struct clk *pclk;
- struct clk *refclk;
- void __iomem *regs;
-
- struct drm_connector connector;
- struct rockchip_encoder encoder;
-
- struct inno_hdmi_i2c *i2c;
- struct i2c_adapter *ddc;
-
- const struct inno_hdmi_variant *variant;
-};
-
-struct inno_hdmi_connector_state {
- struct drm_connector_state base;
- unsigned int enc_out_format;
- unsigned int colorimetry;
- bool rgb_limited_range;
-};
-
-static struct inno_hdmi *encoder_to_inno_hdmi(struct drm_encoder *encoder)
-{
- struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
-
- return container_of(rkencoder, struct inno_hdmi, encoder);
-}
-
-static struct inno_hdmi *connector_to_inno_hdmi(struct drm_connector *connector)
-{
- return container_of(connector, struct inno_hdmi, connector);
-}
-
-#define to_inno_hdmi_conn_state(conn_state) \
- container_of_const(conn_state, struct inno_hdmi_connector_state, base)
-
-enum {
- CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
- CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
- CSC_RGB_0_255_TO_RGB_16_235_8BIT,
-};
-
-static const char coeff_csc[][24] = {
- /*
- * RGB2YUV:601 SD mode:
- * Cb = -0.291G - 0.148R + 0.439B + 128
- * Y = 0.504G + 0.257R + 0.098B + 16
- * Cr = -0.368G + 0.439R - 0.071B + 128
- */
- {
- 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
- 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
- 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
- },
- /*
- * RGB2YUV:709 HD mode:
- * Cb = - 0.338G - 0.101R + 0.439B + 128
- * Y = 0.614G + 0.183R + 0.062B + 16
- * Cr = - 0.399G + 0.439R - 0.040B + 128
- */
- {
- 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
- 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
- 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
- },
- /*
- * RGB[0:255]2RGB[16:235]:
- * R' = R x (235-16)/255 + 16;
- * G' = G x (235-16)/255 + 16;
- * B' = B x (235-16)/255 + 16;
- */
- {
- 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
- 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
- 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
- },
-};
-
-static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
- { 74250000, 0x3f, 0xbb },
- { 165000000, 0x6f, 0xbb },
- { ~0UL, 0x00, 0x00 }
-};
-
-static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
- { 74250000, 0x3f, 0xaa },
- { 165000000, 0x5f, 0xaa },
- { ~0UL, 0x00, 0x00 }
-};
-
-static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
- unsigned long pixelclk)
-{
- const struct inno_hdmi_phy_config *phy_configs =
- hdmi->variant->phy_configs;
- int i;
-
- for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
- if (pixelclk <= phy_configs[i].pixelclock)
- return i;
- }
-
- DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
- pixelclk);
-
- return -EINVAL;
-}
-
-static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
-{
- return readl_relaxed(hdmi->regs + (offset) * 0x04);
-}
-
-static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
-{
- writel_relaxed(val, hdmi->regs + (offset) * 0x04);
-}
-
-static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset,
- u32 msk, u32 val)
-{
- u8 temp = hdmi_readb(hdmi, offset) & ~msk;
-
- temp |= val & msk;
- hdmi_writeb(hdmi, offset, temp);
-}
-
-static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate)
-{
- unsigned long long ddc_bus_freq = rate >> 2;
-
- do_div(ddc_bus_freq, HDMI_SCL_RATE);
-
- hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
- hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
-
- /* Clear the EDID interrupt flag and mute the interrupt */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
- hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
-}
-
-static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable)
-{
- if (enable)
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON);
- else
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF);
-}
-
-static void inno_hdmi_standby(struct inno_hdmi *hdmi)
-{
- inno_hdmi_sys_power(hdmi, false);
-
- hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
-};
-
-static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
- unsigned long mpixelclock)
-{
- struct inno_hdmi_phy_config *phy_config;
- int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
-
- if (ret < 0) {
- phy_config = hdmi->variant->default_phy_config;
- DRM_DEV_ERROR(hdmi->dev,
- "Using default phy configuration for TMDS rate %lu",
- mpixelclock);
- } else {
- phy_config = &hdmi->variant->phy_configs[ret];
- }
-
- inno_hdmi_sys_power(hdmi, false);
-
- hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
- hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
- hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
- hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
- hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
- hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
-
- inno_hdmi_sys_power(hdmi, true);
-};
-
-static void inno_hdmi_reset(struct inno_hdmi *hdmi)
-{
- u32 val;
- u32 msk;
-
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
- udelay(100);
-
- hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
- udelay(100);
-
- msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
- val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
- hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
-
- inno_hdmi_standby(hdmi);
-}
-
-static void inno_hdmi_disable_frame(struct inno_hdmi *hdmi,
- enum hdmi_infoframe_type type)
-{
- struct drm_connector *connector = &hdmi->connector;
-
- if (type != HDMI_INFOFRAME_TYPE_AVI) {
- drm_err(connector->dev,
- "Unsupported infoframe type: %u\n", type);
- return;
- }
-
- hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI);
-}
-
-static int inno_hdmi_upload_frame(struct inno_hdmi *hdmi,
- union hdmi_infoframe *frame, enum hdmi_infoframe_type type)
-{
- struct drm_connector *connector = &hdmi->connector;
- u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
- ssize_t rc, i;
-
- if (type != HDMI_INFOFRAME_TYPE_AVI) {
- drm_err(connector->dev,
- "Unsupported infoframe type: %u\n", type);
- return 0;
- }
-
- inno_hdmi_disable_frame(hdmi, type);
-
- rc = hdmi_infoframe_pack(frame, packed_frame,
- sizeof(packed_frame));
- if (rc < 0)
- return rc;
-
- for (i = 0; i < rc; i++)
- hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i,
- packed_frame[i]);
-
- return 0;
-}
-
-static int inno_hdmi_config_video_avi(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- struct drm_connector *connector = &hdmi->connector;
- struct drm_connector_state *conn_state = connector->state;
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(conn_state);
- union hdmi_infoframe frame;
- int rc;
-
- rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
- &hdmi->connector,
- mode);
- if (rc) {
- inno_hdmi_disable_frame(hdmi, HDMI_INFOFRAME_TYPE_AVI);
- return rc;
- }
-
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444)
- frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
- else if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV422)
- frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
- else
- frame.avi.colorspace = HDMI_COLORSPACE_RGB;
-
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
- drm_hdmi_avi_infoframe_quant_range(&frame.avi,
- connector, mode,
- inno_conn_state->rgb_limited_range ?
- HDMI_QUANTIZATION_RANGE_LIMITED :
- HDMI_QUANTIZATION_RANGE_FULL);
- } else {
- frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
- frame.avi.ycc_quantization_range =
- HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
- }
-
- return inno_hdmi_upload_frame(hdmi, &frame, HDMI_INFOFRAME_TYPE_AVI);
-}
-
-static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
-{
- struct drm_connector *connector = &hdmi->connector;
- struct drm_connector_state *conn_state = connector->state;
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(conn_state);
- int c0_c2_change = 0;
- int csc_enable = 0;
- int csc_mode = 0;
- int auto_csc = 0;
- int value;
- int i;
-
- /* Input video mode is SDR RGB24bit, data enable signal from external */
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
- v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
-
- /* Input color hardcode to RGB, and output color hardcode to RGB888 */
- value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
- v_VIDEO_OUTPUT_COLOR(0) |
- v_VIDEO_INPUT_CSP(0);
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
-
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
- if (inno_conn_state->rgb_limited_range) {
- csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
- auto_csc = AUTO_CSC_DISABLE;
- c0_c2_change = C0_C2_CHANGE_DISABLE;
- csc_enable = v_CSC_ENABLE;
-
- } else {
- value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
-
- hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
- m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
- v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
- v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
- return 0;
- }
- } else {
- if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
- csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
- auto_csc = AUTO_CSC_DISABLE;
- c0_c2_change = C0_C2_CHANGE_DISABLE;
- csc_enable = v_CSC_ENABLE;
- }
- } else {
- if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
- csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
- auto_csc = AUTO_CSC_DISABLE;
- c0_c2_change = C0_C2_CHANGE_DISABLE;
- csc_enable = v_CSC_ENABLE;
- }
- }
- }
-
- for (i = 0; i < 24; i++)
- hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
- coeff_csc[csc_mode][i]);
-
- value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
- hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
- hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
- m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
- v_VIDEO_C0_C2_SWAP(c0_c2_change));
-
- return 0;
-}
-
-static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- int value;
-
- /* Set detail external video timing polarity and interlace mode */
- value = v_EXTERANL_VIDEO(1);
- value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
- v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0);
- value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
- v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0);
- value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
- v_INETLACE(1) : v_INETLACE(0);
- hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value);
-
- /* Set detail external video timing */
- value = mode->htotal;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF);
-
- value = mode->htotal - mode->hdisplay;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF);
-
- value = mode->htotal - mode->hsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF);
-
- value = mode->hsync_end - mode->hsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF);
-
- value = mode->vtotal;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF);
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF);
-
- value = mode->vtotal - mode->vdisplay;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF);
-
- value = mode->vtotal - mode->vsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF);
-
- value = mode->vsync_end - mode->vsync_start;
- hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF);
-
- hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e);
- hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c);
- hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01);
-
- return 0;
-}
-
-static int inno_hdmi_setup(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- struct drm_display_info *display = &hdmi->connector.display_info;
- unsigned long mpixelclock = mode->clock * 1000;
-
- /* Mute video and audio output */
- hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
- v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
-
- /* Set HDMI Mode */
- hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
- v_HDMI_DVI(display->is_hdmi));
-
- inno_hdmi_config_video_timing(hdmi, mode);
-
- inno_hdmi_config_video_csc(hdmi);
-
- if (display->is_hdmi)
- inno_hdmi_config_video_avi(hdmi, mode);
-
- /*
- * When IP controller have configured to an accurate video
- * timing, then the TMDS clock source would be switched to
- * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
- * clock rate, and reconfigure the DDC clock.
- */
- inno_hdmi_i2c_init(hdmi, mpixelclock);
-
- /* Unmute video and audio output */
- hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
- v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
-
- inno_hdmi_power_up(hdmi, mpixelclock);
-
- return 0;
-}
-
-static enum drm_mode_status inno_hdmi_display_mode_valid(struct inno_hdmi *hdmi,
- struct drm_display_mode *mode)
-{
- unsigned long mpixelclk, max_tolerance;
- long rounded_refclk;
-
- /* No support for double-clock modes */
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
- return MODE_BAD;
-
- mpixelclk = mode->clock * 1000;
-
- if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK)
- return MODE_CLOCK_LOW;
-
- if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0)
- return MODE_CLOCK_HIGH;
-
- if (hdmi->refclk) {
- rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk);
- if (rounded_refclk < 0)
- return MODE_BAD;
-
- /* Vesa DMT standard mentions +/- 0.5% max tolerance */
- max_tolerance = mpixelclk / 200;
- if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance)
- return MODE_NOCLOCK;
- }
-
- return MODE_OK;
-}
-
-static void inno_hdmi_encoder_enable(struct drm_encoder *encoder,
- struct drm_atomic_state *state)
-{
- struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
- struct drm_connector_state *conn_state;
- struct drm_crtc_state *crtc_state;
-
- conn_state = drm_atomic_get_new_connector_state(state, &hdmi->connector);
- if (WARN_ON(!conn_state))
- return;
-
- crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
- if (WARN_ON(!crtc_state))
- return;
-
- inno_hdmi_setup(hdmi, &crtc_state->adjusted_mode);
-}
-
-static void inno_hdmi_encoder_disable(struct drm_encoder *encoder,
- struct drm_atomic_state *state)
-{
- struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
-
- inno_hdmi_standby(hdmi);
-}
-
-static int
-inno_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
- struct drm_crtc_state *crtc_state,
- struct drm_connector_state *conn_state)
-{
- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
- struct inno_hdmi *hdmi = encoder_to_inno_hdmi(encoder);
- struct drm_display_mode *mode = &crtc_state->adjusted_mode;
- u8 vic = drm_match_cea_mode(mode);
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(conn_state);
-
- s->output_mode = ROCKCHIP_OUT_MODE_P888;
- s->output_type = DRM_MODE_CONNECTOR_HDMIA;
-
- if (vic == 6 || vic == 7 ||
- vic == 21 || vic == 22 ||
- vic == 2 || vic == 3 ||
- vic == 17 || vic == 18)
- inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_601;
- else
- inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
-
- inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
- inno_conn_state->rgb_limited_range =
- drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED;
-
- return inno_hdmi_display_mode_valid(hdmi,
- &crtc_state->adjusted_mode) == MODE_OK ? 0 : -EINVAL;
-}
-
-static struct drm_encoder_helper_funcs inno_hdmi_encoder_helper_funcs = {
- .atomic_check = inno_hdmi_encoder_atomic_check,
- .atomic_enable = inno_hdmi_encoder_enable,
- .atomic_disable = inno_hdmi_encoder_disable,
-};
-
-static enum drm_connector_status
-inno_hdmi_connector_detect(struct drm_connector *connector, bool force)
-{
- struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
-
- return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ?
- connector_status_connected : connector_status_disconnected;
-}
-
-static int inno_hdmi_connector_get_modes(struct drm_connector *connector)
-{
- struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
- const struct drm_edid *drm_edid;
- int ret = 0;
-
- if (!hdmi->ddc)
- return 0;
-
- drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
- drm_edid_connector_update(connector, drm_edid);
- ret = drm_edid_connector_add_modes(connector);
- drm_edid_free(drm_edid);
-
- return ret;
-}
-
-static enum drm_mode_status
-inno_hdmi_connector_mode_valid(struct drm_connector *connector,
- struct drm_display_mode *mode)
-{
- struct inno_hdmi *hdmi = connector_to_inno_hdmi(connector);
-
- return inno_hdmi_display_mode_valid(hdmi, mode);
-}
-
-static void inno_hdmi_connector_destroy(struct drm_connector *connector)
-{
- drm_connector_unregister(connector);
- drm_connector_cleanup(connector);
-}
-
-static void
-inno_hdmi_connector_destroy_state(struct drm_connector *connector,
- struct drm_connector_state *state)
-{
- struct inno_hdmi_connector_state *inno_conn_state =
- to_inno_hdmi_conn_state(state);
-
- __drm_atomic_helper_connector_destroy_state(&inno_conn_state->base);
- kfree(inno_conn_state);
-}
-
-static void inno_hdmi_connector_reset(struct drm_connector *connector)
-{
- struct inno_hdmi_connector_state *inno_conn_state;
-
- if (connector->state) {
- inno_hdmi_connector_destroy_state(connector, connector->state);
- connector->state = NULL;
- }
-
- inno_conn_state = kzalloc(sizeof(*inno_conn_state), GFP_KERNEL);
- if (!inno_conn_state)
- return;
-
- __drm_atomic_helper_connector_reset(connector, &inno_conn_state->base);
-
- inno_conn_state->colorimetry = HDMI_COLORIMETRY_ITU_709;
- inno_conn_state->enc_out_format = HDMI_COLORSPACE_RGB;
- inno_conn_state->rgb_limited_range = false;
-}
-
-static struct drm_connector_state *
-inno_hdmi_connector_duplicate_state(struct drm_connector *connector)
-{
- struct inno_hdmi_connector_state *inno_conn_state;
-
- if (WARN_ON(!connector->state))
- return NULL;
-
- inno_conn_state = kmemdup(to_inno_hdmi_conn_state(connector->state),
- sizeof(*inno_conn_state), GFP_KERNEL);
-
- if (!inno_conn_state)
- return NULL;
-
- __drm_atomic_helper_connector_duplicate_state(connector,
- &inno_conn_state->base);
-
- return &inno_conn_state->base;
-}
-
-static const struct drm_connector_funcs inno_hdmi_connector_funcs = {
- .fill_modes = drm_helper_probe_single_connector_modes,
- .detect = inno_hdmi_connector_detect,
- .destroy = inno_hdmi_connector_destroy,
- .reset = inno_hdmi_connector_reset,
- .atomic_duplicate_state = inno_hdmi_connector_duplicate_state,
- .atomic_destroy_state = inno_hdmi_connector_destroy_state,
-};
-
-static struct drm_connector_helper_funcs inno_hdmi_connector_helper_funcs = {
- .get_modes = inno_hdmi_connector_get_modes,
- .mode_valid = inno_hdmi_connector_mode_valid,
-};
-
-static int inno_hdmi_register(struct drm_device *drm, struct inno_hdmi *hdmi)
-{
- struct drm_encoder *encoder = &hdmi->encoder.encoder;
- struct device *dev = hdmi->dev;
-
- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
-
- /*
- * If we failed to find the CRTC(s) which this encoder is
- * supposed to be connected to, it's because the CRTC has
- * not been registered yet. Defer probing, and hope that
- * the required CRTC is added later.
- */
- if (encoder->possible_crtcs == 0)
- return -EPROBE_DEFER;
-
- drm_encoder_helper_add(encoder, &inno_hdmi_encoder_helper_funcs);
- drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
-
- hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
-
- drm_connector_helper_add(&hdmi->connector,
- &inno_hdmi_connector_helper_funcs);
- drm_connector_init_with_ddc(drm, &hdmi->connector,
- &inno_hdmi_connector_funcs,
- DRM_MODE_CONNECTOR_HDMIA,
- hdmi->ddc);
-
- drm_connector_attach_encoder(&hdmi->connector, encoder);
-
- return 0;
-}
-
-static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi)
-{
- struct inno_hdmi_i2c *i2c = hdmi->i2c;
- u8 stat;
-
- stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1);
- if (!(stat & m_INT_EDID_READY))
- return IRQ_NONE;
-
- /* Clear HDMI EDID interrupt flag */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
-
- complete(&i2c->cmp);
-
- return IRQ_HANDLED;
-}
-
-static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id)
-{
- struct inno_hdmi *hdmi = dev_id;
- irqreturn_t ret = IRQ_NONE;
- u8 interrupt;
-
- if (hdmi->i2c)
- ret = inno_hdmi_i2c_irq(hdmi);
-
- interrupt = hdmi_readb(hdmi, HDMI_STATUS);
- if (interrupt & m_INT_HOTPLUG) {
- hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG);
- ret = IRQ_WAKE_THREAD;
- }
-
- return ret;
-}
-
-static irqreturn_t inno_hdmi_irq(int irq, void *dev_id)
-{
- struct inno_hdmi *hdmi = dev_id;
-
- drm_helper_hpd_irq_event(hdmi->connector.dev);
-
- return IRQ_HANDLED;
-}
-
-static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
-{
- int length = msgs->len;
- u8 *buf = msgs->buf;
- int ret;
-
- ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10);
- if (!ret)
- return -EAGAIN;
-
- while (length--)
- *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR);
-
- return 0;
-}
-
-static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs)
-{
- /*
- * The DDC module only support read EDID message, so
- * we assume that each word write to this i2c adapter
- * should be the offset of EDID word address.
- */
- if ((msgs->len != 1) ||
- ((msgs->addr != DDC_ADDR) && (msgs->addr != DDC_SEGMENT_ADDR)))
- return -EINVAL;
-
- reinit_completion(&hdmi->i2c->cmp);
-
- if (msgs->addr == DDC_SEGMENT_ADDR)
- hdmi->i2c->segment_addr = msgs->buf[0];
- if (msgs->addr == DDC_ADDR)
- hdmi->i2c->ddc_addr = msgs->buf[0];
-
- /* Set edid fifo first addr */
- hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00);
-
- /* Set edid word address 0x00/0x80 */
- hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
-
- /* Set edid segment pointer */
- hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
-
- return 0;
-}
-
-static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap,
- struct i2c_msg *msgs, int num)
-{
- struct inno_hdmi *hdmi = i2c_get_adapdata(adap);
- struct inno_hdmi_i2c *i2c = hdmi->i2c;
- int i, ret = 0;
-
- mutex_lock(&i2c->lock);
-
- /* Clear the EDID interrupt flag and unmute the interrupt */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY);
- hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY);
-
- for (i = 0; i < num; i++) {
- DRM_DEV_DEBUG(hdmi->dev,
- "xfer: num: %d/%d, len: %d, flags: %#x\n",
- i + 1, num, msgs[i].len, msgs[i].flags);
-
- if (msgs[i].flags & I2C_M_RD)
- ret = inno_hdmi_i2c_read(hdmi, &msgs[i]);
- else
- ret = inno_hdmi_i2c_write(hdmi, &msgs[i]);
-
- if (ret < 0)
- break;
- }
-
- if (!ret)
- ret = num;
-
- /* Mute HDMI EDID interrupt */
- hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0);
-
- mutex_unlock(&i2c->lock);
-
- return ret;
-}
-
-static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
-{
- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
-}
-
-static const struct i2c_algorithm inno_hdmi_algorithm = {
- .master_xfer = inno_hdmi_i2c_xfer,
- .functionality = inno_hdmi_i2c_func,
-};
-
-static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
-{
- struct i2c_adapter *adap;
- struct inno_hdmi_i2c *i2c;
- int ret;
-
- i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
- if (!i2c)
- return ERR_PTR(-ENOMEM);
-
- mutex_init(&i2c->lock);
- init_completion(&i2c->cmp);
-
- adap = &i2c->adap;
- adap->owner = THIS_MODULE;
- adap->dev.parent = hdmi->dev;
- adap->dev.of_node = hdmi->dev->of_node;
- adap->algo = &inno_hdmi_algorithm;
- strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
- i2c_set_adapdata(adap, hdmi);
-
- ret = i2c_add_adapter(adap);
- if (ret) {
- dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
- devm_kfree(hdmi->dev, i2c);
- return ERR_PTR(ret);
- }
-
- hdmi->i2c = i2c;
-
- DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
-
- return adap;
-}
-
-static int inno_hdmi_bind(struct device *dev, struct device *master,
- void *data)
-{
- struct platform_device *pdev = to_platform_device(dev);
- struct drm_device *drm = data;
- struct inno_hdmi *hdmi;
- const struct inno_hdmi_variant *variant;
- int irq;
- int ret;
-
- hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
- if (!hdmi)
- return -ENOMEM;
-
- hdmi->dev = dev;
-
- variant = of_device_get_match_data(hdmi->dev);
- if (!variant)
- return -EINVAL;
-
- hdmi->variant = variant;
-
- hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(hdmi->regs))
- return PTR_ERR(hdmi->regs);
-
- hdmi->pclk = devm_clk_get(hdmi->dev, "pclk");
- if (IS_ERR(hdmi->pclk)) {
- DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI pclk clk\n");
- return PTR_ERR(hdmi->pclk);
- }
-
- ret = clk_prepare_enable(hdmi->pclk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev,
- "Cannot enable HDMI pclk clock: %d\n", ret);
- return ret;
- }
-
- hdmi->refclk = devm_clk_get_optional(hdmi->dev, "ref");
- if (IS_ERR(hdmi->refclk)) {
- DRM_DEV_ERROR(hdmi->dev, "Unable to get HDMI reference clock\n");
- ret = PTR_ERR(hdmi->refclk);
- goto err_disable_pclk;
- }
-
- ret = clk_prepare_enable(hdmi->refclk);
- if (ret) {
- DRM_DEV_ERROR(hdmi->dev,
- "Cannot enable HDMI reference clock: %d\n", ret);
- goto err_disable_pclk;
- }
-
- irq = platform_get_irq(pdev, 0);
- if (irq < 0) {
- ret = irq;
- goto err_disable_clk;
- }
-
- inno_hdmi_reset(hdmi);
-
- hdmi->ddc = inno_hdmi_i2c_adapter(hdmi);
- if (IS_ERR(hdmi->ddc)) {
- ret = PTR_ERR(hdmi->ddc);
- hdmi->ddc = NULL;
- goto err_disable_clk;
- }
-
- /*
- * When the controller isn't configured to an accurate
- * video timing and there is no reference clock available,
- * then the TMDS clock source would be switched to PCLK_HDMI,
- * so we need to init the TMDS rate to PCLK rate, and
- * reconfigure the DDC clock.
- */
- if (hdmi->refclk)
- inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk));
- else
- inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk));
-
- ret = inno_hdmi_register(drm, hdmi);
- if (ret)
- goto err_put_adapter;
-
- dev_set_drvdata(dev, hdmi);
-
- /* Unmute hotplug interrupt */
- hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1));
-
- ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq,
- inno_hdmi_irq, IRQF_SHARED,
- dev_name(dev), hdmi);
- if (ret < 0)
- goto err_cleanup_hdmi;
-
- return 0;
-err_cleanup_hdmi:
- hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
-err_put_adapter:
- i2c_put_adapter(hdmi->ddc);
-err_disable_clk:
- clk_disable_unprepare(hdmi->refclk);
-err_disable_pclk:
- clk_disable_unprepare(hdmi->pclk);
- return ret;
-}
-
-static void inno_hdmi_unbind(struct device *dev, struct device *master,
- void *data)
-{
- struct inno_hdmi *hdmi = dev_get_drvdata(dev);
-
- hdmi->connector.funcs->destroy(&hdmi->connector);
- hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
-
- i2c_put_adapter(hdmi->ddc);
- clk_disable_unprepare(hdmi->refclk);
- clk_disable_unprepare(hdmi->pclk);
-}
-
-static const struct component_ops inno_hdmi_ops = {
- .bind = inno_hdmi_bind,
- .unbind = inno_hdmi_unbind,
-};
-
-static int inno_hdmi_probe(struct platform_device *pdev)
-{
- return component_add(&pdev->dev, &inno_hdmi_ops);
-}
-
-static void inno_hdmi_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &inno_hdmi_ops);
-}
-
-static const struct inno_hdmi_variant rk3036_inno_hdmi_variant = {
- .phy_configs = rk3036_hdmi_phy_configs,
- .default_phy_config = &rk3036_hdmi_phy_configs[1],
-};
-
-static const struct inno_hdmi_variant rk3128_inno_hdmi_variant = {
- .phy_configs = rk3128_hdmi_phy_configs,
- .default_phy_config = &rk3128_hdmi_phy_configs[1],
-};
-
-static const struct of_device_id inno_hdmi_dt_ids[] = {
- { .compatible = "rockchip,rk3036-inno-hdmi",
- .data = &rk3036_inno_hdmi_variant,
- },
- { .compatible = "rockchip,rk3128-inno-hdmi",
- .data = &rk3128_inno_hdmi_variant,
- },
- {},
-};
-MODULE_DEVICE_TABLE(of, inno_hdmi_dt_ids);
-
-struct platform_driver inno_hdmi_driver = {
- .probe = inno_hdmi_probe,
- .remove_new = inno_hdmi_remove,
- .driver = {
- .name = "innohdmi-rockchip",
- .of_match_table = inno_hdmi_dt_ids,
- },
-};
--
2.27.0
On 21/05/2024 12:58, keith wrote:
> Verisilicon/DC8200 display controller IP has 2 display pipes and each
> pipe support a primary plane and a cursor plane .
> In addition, there are four overlay planes as two display pipes common resources.
>
> The first display pipe is bound to the inno HDMI encoder.
> The second display pipe is bound to a simple encoder, which is used to
> find dsi bridge by dts node.
>
> Patch 1 adds YAML schema for JH7110 display pipeline.
>
> Patches 2 to 3 add inno common api and match the ROCKCHIP inno hdmi driver
> by calling the common api.
> The collating public interface is based on ROCKCHIP inno hdmi,
> and it can be resused by JH7110 inno hdmi.
> Those common api are tested on rk-3128 SDK, which kernel version is 4.x.
> step1, make sure the process is consistent with the latest kernel version.
> step2, just remove the interface and add a common interface.
>
> Patches 4 to 8 add kms driver for dc8200 display controller.
>
> Patch 9 adds inno hdmi support for JH7110 display pipeline.
>
> Patch 10 adds a simple encoder.
>
> This patchset should be applied on next branch.
>
Please fix your clock, so this patchset does not appear +4h in the
future and on top of other patches...
Best regards,
Krzysztof
Hi Alex,
Am Dienstag, 21. Mai 2024, 12:58:07 CEST schrieb keith:
> Verisilicon/DC8200 display controller IP has 2 display pipes and each
> pipe support a primary plane and a cursor plane .
> In addition, there are four overlay planes as two display pipes common resources.
>
> The first display pipe is bound to the inno HDMI encoder.
> The second display pipe is bound to a simple encoder, which is used to
> find dsi bridge by dts node.
>
> Patch 1 adds YAML schema for JH7110 display pipeline.
>
> Patches 2 to 3 add inno common api and match the ROCKCHIP inno hdmi driver
> by calling the common api.
> The collating public interface is based on ROCKCHIP inno hdmi,
> and it can be resused by JH7110 inno hdmi.
> Those common api are tested on rk-3128 SDK, which kernel version is 4.x.
as you were working on the rk3128-inno-hdmi variant recently
and I don't really have a rk3036 or rk3128 in working condition
right now, could you give this series a try.
For reference, the full series is at lore:
https://lore.kernel.org/dri-devel/[email protected]/
and generalizes the inno-hdmi driver into the bridge model we
have in a number of other places already.
Thanks
Heiko
> step1, make sure the process is consistent with the latest kernel version.
> step2, just remove the interface and add a common interface.
>
> Patches 4 to 8 add kms driver for dc8200 display controller.
>
> Patch 9 adds inno hdmi support for JH7110 display pipeline.
>
> Patch 10 adds a simple encoder.
>
> This patchset should be applied on next branch.
>
> V1:
> Changes since v1:
> - Further standardize the yaml file.
> - Dts naming convention improved.
> - Fix the problem of compiling and loading ko files.
> - Use drm new api to automatically manage resources.
> - Drop vs_crtc_funcs&vs_plane_funcs, subdivide the plane's help interface.
> - Reduce the modifiers unused.
> - Optimize the hdmi driver code
>
> V2:
> Changes since v2:
> - fix the error about checking the yaml file.
> - match drm driver GEM DMA API.
> - Delete the custom crtc property .
> - hdmi use drmm_ new api to automatically manage resources.
> - update the modifiers comments.
> - enabling KASAN, fix the error during removing module
>
> V3:
> Changes since v3:
> - Delete the custom plane property.
> - Delete the custom fourcc modifiers.
> - Adjust the calculation mode of hdmi pixclock.
> - Add match data for dc8200 driver.
> - Adjust some magic values.
> - Add a simple encoder for dsi output.
>
> V4:
> Changes since v4:
> - Delete the display subsystem module as all crtcs and planes are a driver.
> - Delete the custom struct, directly use the drm struct data.
> - Tidy up the inno hdmi public interface.
> - Add a simple encoder for dsi output.
>
> keith (10):
> dt-bindings: display: Add YAML schema for JH7110 display pipeline
> drm/bridge: add common api for inno hdmi
> drm/rockchip:hdmi: migrate to use inno-hdmi bridge driver
> drm/vs: Add hardware funcs for vs.
> drm/vs: add vs mode config init
> drm/vs: add vs plane api
> drm/vs: add ctrc fun
> drm/vs: add vs drm master driver
> drm/vs: Innosilicon HDMI support
> drm/vs: add simple dsi encoder
>
> .../display/bridge/innosilicon,inno-hdmi.yaml | 49 +
> .../display/rockchip/rockchip,inno-hdmi.yaml | 27 +-
> .../starfive/starfive,dsi-encoder.yaml | 92 ++
> .../starfive/starfive,jh7110-dc8200.yaml | 169 +++
> .../starfive/starfive,jh7110-inno-hdmi.yaml | 75 ++
> .../soc/starfive/starfive,jh7110-syscon.yaml | 1 +
> MAINTAINERS | 11 +
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
> drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
> .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 +++++++++
> .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 ++
> drivers/gpu/drm/rockchip/Kconfig | 1 +
> drivers/gpu/drm/rockchip/Makefile | 2 +-
> drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 517 ++++++++
> .../{inno_hdmi.h => inno_hdmi-rockchip.h} | 45 -
> drivers/gpu/drm/rockchip/inno_hdmi.c | 1073 -----------------
> drivers/gpu/drm/verisilicon/Kconfig | 23 +
> drivers/gpu/drm/verisilicon/Makefile | 11 +
> .../gpu/drm/verisilicon/inno_hdmi-starfive.c | 481 ++++++++
> .../gpu/drm/verisilicon/inno_hdmi-starfive.h | 152 +++
> drivers/gpu/drm/verisilicon/vs_crtc.c | 241 ++++
> drivers/gpu/drm/verisilicon/vs_crtc.h | 17 +
> drivers/gpu/drm/verisilicon/vs_dc_hw.c | 1060 ++++++++++++++++
> drivers/gpu/drm/verisilicon/vs_dc_hw.h | 493 ++++++++
> drivers/gpu/drm/verisilicon/vs_drv.c | 721 +++++++++++
> drivers/gpu/drm/verisilicon/vs_drv.h | 98 ++
> drivers/gpu/drm/verisilicon/vs_modeset.c | 36 +
> drivers/gpu/drm/verisilicon/vs_modeset.h | 10 +
> drivers/gpu/drm/verisilicon/vs_plane.c | 487 ++++++++
> drivers/gpu/drm/verisilicon/vs_plane.h | 26 +
> drivers/gpu/drm/verisilicon/vs_simple_enc.c | 190 +++
> drivers/gpu/drm/verisilicon/vs_simple_enc.h | 25 +
> drivers/gpu/drm/verisilicon/vs_type.h | 84 ++
> include/drm/bridge/inno_hdmi.h | 69 ++
> 38 files changed, 5840 insertions(+), 1144 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.yaml
> create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,dsi-encoder.yaml
> create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,jh7110-dc8200.yaml
> create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,jh7110-inno-hdmi.yaml
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
> create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
> rename drivers/gpu/drm/rockchip/{inno_hdmi.h => inno_hdmi-rockchip.h} (85%)
> delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c
> create mode 100644 drivers/gpu/drm/verisilicon/Kconfig
> create mode 100644 drivers/gpu/drm/verisilicon/Makefile
> create mode 100644 drivers/gpu/drm/verisilicon/inno_hdmi-starfive.c
> create mode 100644 drivers/gpu/drm/verisilicon/inno_hdmi-starfive.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_simple_enc.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_simple_enc.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_type.h
> create mode 100644 include/drm/bridge/inno_hdmi.h
>
>
On 21/05/2024 12:58, keith wrote:
> Add INNO common api so that it can be used by vendor
> drivers which implement vendor specific extensions to Innosilicon HDMI.
>
> Signed-off-by: keith <[email protected]>
> ---
> MAINTAINERS | 2 +
> +}
> +
> +static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter)
> +{
> + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm inno_hdmi_algorithm = {
> + .master_xfer = inno_hdmi_i2c_xfer,
> + .functionality = inno_hdmi_i2c_func,
> +};
> +
> +static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
> +{
> + struct i2c_adapter *adap;
> + struct inno_hdmi_i2c *i2c;
> + int ret;
> +
> + i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
> + if (!i2c)
> + return ERR_PTR(-ENOMEM);
> +
> + mutex_init(&i2c->lock);
> + init_completion(&i2c->cmp);
> +
> + adap = &i2c->adap;
> + adap->owner = THIS_MODULE;
> + adap->dev.parent = hdmi->dev;
> + adap->dev.of_node = hdmi->dev->of_node;
> + adap->algo = &inno_hdmi_algorithm;
> + strscpy(adap->name, "Inno HDMI", sizeof(adap->name));
> + i2c_set_adapdata(adap, hdmi);
> +
> + ret = i2c_add_adapter(adap);
> + if (ret) {
> + dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
> + devm_kfree(hdmi->dev, i2c);
Hm, why freeing? That's a devm. You don't free other pieces in bind paths...
> + return ERR_PTR(ret);
> + }
> +
> + hdmi->i2c = i2c;
> +
> + DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
Please do not print simple success messages. Tracing tells you this and
driver should be quiet in typical cases.
You have also some weird tabs instead of spaces here and there... like
before 'encoder' arguments. This is needs some basic style check.
Best regards,
Krzysztof
Hi Heiko,
Am 21.05.24 um 10:03 schrieb Heiko Stübner:
> Hi Alex,
>
> Am Dienstag, 21. Mai 2024, 12:58:07 CEST schrieb keith:
>> Verisilicon/DC8200 display controller IP has 2 display pipes and each
>> pipe support a primary plane and a cursor plane .
>> In addition, there are four overlay planes as two display pipes common resources.
>>
>> The first display pipe is bound to the inno HDMI encoder.
>> The second display pipe is bound to a simple encoder, which is used to
>> find dsi bridge by dts node.
>>
>> Patch 1 adds YAML schema for JH7110 display pipeline.
>>
>> Patches 2 to 3 add inno common api and match the ROCKCHIP inno hdmi driver
>> by calling the common api.
>> The collating public interface is based on ROCKCHIP inno hdmi,
>> and it can be resused by JH7110 inno hdmi.
>> Those common api are tested on rk-3128 SDK, which kernel version is 4.x.
> as you were working on the rk3128-inno-hdmi variant recently
> and I don't really have a rk3036 or rk3128 in working condition
> right now, could you give this series a try.
Sure, I'm going to check this soon.
Regards,
Alex
> For reference, the full series is at lore:
> https://lore.kernel.org/dri-devel/[email protected]/
>
> and generalizes the inno-hdmi driver into the bridge model we
> have in a number of other places already.
>
>
> Thanks
> Heiko
>
>
>
>> step1, make sure the process is consistent with the latest kernel version.
>> step2, just remove the interface and add a common interface.
>>
>> Patches 4 to 8 add kms driver for dc8200 display controller.
>>
>> Patch 9 adds inno hdmi support for JH7110 display pipeline.
>>
>> Patch 10 adds a simple encoder.
>>
>> This patchset should be applied on next branch.
>>
>> V1:
>> Changes since v1:
>> - Further standardize the yaml file.
>> - Dts naming convention improved.
>> - Fix the problem of compiling and loading ko files.
>> - Use drm new api to automatically manage resources.
>> - Drop vs_crtc_funcs&vs_plane_funcs, subdivide the plane's help interface.
>> - Reduce the modifiers unused.
>> - Optimize the hdmi driver code
>>
>> V2:
>> Changes since v2:
>> - fix the error about checking the yaml file.
>> - match drm driver GEM DMA API.
>> - Delete the custom crtc property .
>> - hdmi use drmm_ new api to automatically manage resources.
>> - update the modifiers comments.
>> - enabling KASAN, fix the error during removing module
>>
>> V3:
>> Changes since v3:
>> - Delete the custom plane property.
>> - Delete the custom fourcc modifiers.
>> - Adjust the calculation mode of hdmi pixclock.
>> - Add match data for dc8200 driver.
>> - Adjust some magic values.
>> - Add a simple encoder for dsi output.
>>
>> V4:
>> Changes since v4:
>> - Delete the display subsystem module as all crtcs and planes are a driver.
>> - Delete the custom struct, directly use the drm struct data.
>> - Tidy up the inno hdmi public interface.
>> - Add a simple encoder for dsi output.
>>
>> keith (10):
>> dt-bindings: display: Add YAML schema for JH7110 display pipeline
>> drm/bridge: add common api for inno hdmi
>> drm/rockchip:hdmi: migrate to use inno-hdmi bridge driver
>> drm/vs: Add hardware funcs for vs.
>> drm/vs: add vs mode config init
>> drm/vs: add vs plane api
>> drm/vs: add ctrc fun
>> drm/vs: add vs drm master driver
>> drm/vs: Innosilicon HDMI support
>> drm/vs: add simple dsi encoder
>>
>> .../display/bridge/innosilicon,inno-hdmi.yaml | 49 +
>> .../display/rockchip/rockchip,inno-hdmi.yaml | 27 +-
>> .../starfive/starfive,dsi-encoder.yaml | 92 ++
>> .../starfive/starfive,jh7110-dc8200.yaml | 169 +++
>> .../starfive/starfive,jh7110-inno-hdmi.yaml | 75 ++
>> .../soc/starfive/starfive,jh7110-syscon.yaml | 1 +
>> MAINTAINERS | 11 +
>> drivers/gpu/drm/Kconfig | 2 +
>> drivers/gpu/drm/Makefile | 1 +
>> drivers/gpu/drm/bridge/Kconfig | 2 +
>> drivers/gpu/drm/bridge/Makefile | 1 +
>> drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
>> drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
>> .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 +++++++++
>> .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 ++
>> drivers/gpu/drm/rockchip/Kconfig | 1 +
>> drivers/gpu/drm/rockchip/Makefile | 2 +-
>> drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 517 ++++++++
>> .../{inno_hdmi.h => inno_hdmi-rockchip.h} | 45 -
>> drivers/gpu/drm/rockchip/inno_hdmi.c | 1073 -----------------
>> drivers/gpu/drm/verisilicon/Kconfig | 23 +
>> drivers/gpu/drm/verisilicon/Makefile | 11 +
>> .../gpu/drm/verisilicon/inno_hdmi-starfive.c | 481 ++++++++
>> .../gpu/drm/verisilicon/inno_hdmi-starfive.h | 152 +++
>> drivers/gpu/drm/verisilicon/vs_crtc.c | 241 ++++
>> drivers/gpu/drm/verisilicon/vs_crtc.h | 17 +
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c | 1060 ++++++++++++++++
>> drivers/gpu/drm/verisilicon/vs_dc_hw.h | 493 ++++++++
>> drivers/gpu/drm/verisilicon/vs_drv.c | 721 +++++++++++
>> drivers/gpu/drm/verisilicon/vs_drv.h | 98 ++
>> drivers/gpu/drm/verisilicon/vs_modeset.c | 36 +
>> drivers/gpu/drm/verisilicon/vs_modeset.h | 10 +
>> drivers/gpu/drm/verisilicon/vs_plane.c | 487 ++++++++
>> drivers/gpu/drm/verisilicon/vs_plane.h | 26 +
>> drivers/gpu/drm/verisilicon/vs_simple_enc.c | 190 +++
>> drivers/gpu/drm/verisilicon/vs_simple_enc.h | 25 +
>> drivers/gpu/drm/verisilicon/vs_type.h | 84 ++
>> include/drm/bridge/inno_hdmi.h | 69 ++
>> 38 files changed, 5840 insertions(+), 1144 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.yaml
>> create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,dsi-encoder.yaml
>> create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,jh7110-dc8200.yaml
>> create mode 100644 Documentation/devicetree/bindings/display/starfive/starfive,jh7110-inno-hdmi.yaml
>> create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
>> create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
>> create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
>> create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
>> create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
>> rename drivers/gpu/drm/rockchip/{inno_hdmi.h => inno_hdmi-rockchip.h} (85%)
>> delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c
>> create mode 100644 drivers/gpu/drm/verisilicon/Kconfig
>> create mode 100644 drivers/gpu/drm/verisilicon/Makefile
>> create mode 100644 drivers/gpu/drm/verisilicon/inno_hdmi-starfive.c
>> create mode 100644 drivers/gpu/drm/verisilicon/inno_hdmi-starfive.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_crtc.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_drv.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_modeset.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_plane.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_simple_enc.c
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_simple_enc.h
>> create mode 100644 drivers/gpu/drm/verisilicon/vs_type.h
>> create mode 100644 include/drm/bridge/inno_hdmi.h
>>
>>
>
>
>
Hi Keith,
thanks a lot for working on this. See some general remarks below
Am 21.05.24 um 12:58 schrieb keith:
> Add INNO common api so that it can be used by vendor
> drivers which implement vendor specific extensions to Innosilicon HDMI.
>
> Signed-off-by: keith <[email protected]>
> ---
> MAINTAINERS | 2 +
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
> drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
> .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 ++++++++++++++++++
> .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 +++
> include/drm/bridge/inno_hdmi.h | 69 ++
> 8 files changed, 766 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
> create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
> create mode 100644 include/drm/bridge/inno_hdmi.h
>
...
> + drm_encoder_helper_add(encoder, pdata->helper_private);
> +
> + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
> +
> + drm_connector_helper_add(&hdmi->connector,
> + &inno_hdmi_connector_helper_funcs);
> +
> + drmm_connector_init(drm, &hdmi->connector,
> + &inno_hdmi_connector_funcs,
> + DRM_MODE_CONNECTOR_HDMIA,
> + hdmi->ddc);
> +
I really don't want to anticipate bridge maintainer's feedback, but new
bridge drivers must not contain connector creation. That must happen
somewhere else.
Also I'm neither seeing any drm_brige struct nor drm_bridge_funcs, which
are both essential for a bridge driver. I don't think moving a part of a
driver to .../drm/bridge/ makes it a bridge driver.
Regeards,
Alex
> + drm_connector_attach_encoder(&hdmi->connector, encoder);
> +
> + return 0;
> +}
> +
...
On Tue, May 21, 2024 at 05:36:43PM +0200, Alex Bee wrote:
> Hi Keith,
>
> thanks a lot for working on this. See some general remarks below
>
> Am 21.05.24 um 12:58 schrieb keith:
> > Add INNO common api so that it can be used by vendor
> > drivers which implement vendor specific extensions to Innosilicon HDMI.
> >
> > Signed-off-by: keith <[email protected]>
> > ---
> > MAINTAINERS | 2 +
> > drivers/gpu/drm/bridge/Kconfig | 2 +
> > drivers/gpu/drm/bridge/Makefile | 1 +
> > drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
> > drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
> > .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 ++++++++++++++++++
> > .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 +++
> > include/drm/bridge/inno_hdmi.h | 69 ++
> > 8 files changed, 766 insertions(+)
> > create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
> > create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
> > create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
> > create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
> > create mode 100644 include/drm/bridge/inno_hdmi.h
> >
> ....
>
> > + drm_encoder_helper_add(encoder, pdata->helper_private);
> > +
> > + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
> > +
> > + drm_connector_helper_add(&hdmi->connector,
> > + &inno_hdmi_connector_helper_funcs);
> > +
> > + drmm_connector_init(drm, &hdmi->connector,
> > + &inno_hdmi_connector_funcs,
> > + DRM_MODE_CONNECTOR_HDMIA,
> > + hdmi->ddc);
> > +
>
> I really don't want to anticipate bridge maintainer's feedback, but new
> bridge drivers must not contain connector creation. That must happen
> somewhere else.
You're absolutely right :-) Connector creation should be handled by the
drm_bridge_connector helper. The HDMI bridge driver should focus on the
HDMI bridge itself.
> Also I'm neither seeing any drm_brige struct nor drm_bridge_funcs, which
> are both essential for a bridge driver. I don't think moving a part of a
> driver to .../drm/bridge/ makes it a bridge driver.
>
> > + drm_connector_attach_encoder(&hdmi->connector, encoder);
> > +
> > + return 0;
> > +}
> > +
> ....
>
--
Regards,
Laurent Pinchart
On Tue, May 21, 2024 at 06:58:11PM +0800, keith wrote:
> add hardware base api for vs drm
Commit message is nearly missing. Please describe your hardware.
>
> Signed-off-by: keith <[email protected]>
Full name please
> ---
> MAINTAINERS | 1 +
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/verisilicon/Kconfig | 13 +
> drivers/gpu/drm/verisilicon/Makefile | 5 +
> drivers/gpu/drm/verisilicon/vs_dc_hw.c | 1060 ++++++++++++++++++++++++
> drivers/gpu/drm/verisilicon/vs_dc_hw.h | 493 +++++++++++
> drivers/gpu/drm/verisilicon/vs_type.h | 84 ++
> 8 files changed, 1659 insertions(+)
> create mode 100644 drivers/gpu/drm/verisilicon/Kconfig
> create mode 100644 drivers/gpu/drm/verisilicon/Makefile
> create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.c
> create mode 100644 drivers/gpu/drm/verisilicon/vs_dc_hw.h
> create mode 100644 drivers/gpu/drm/verisilicon/vs_type.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cf2d66f88a83..9cb376f76f74 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7156,6 +7156,7 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
> F: Documentation/devicetree/bindings/display/bridge/innosilicon,inno-hdmi.yaml
> F: Documentation/devicetree/bindings/display/starfive/
> F: drivers/gpu/drm/bridge/innosilicon/
> +F: drivers/gpu/drm/verisilicon
> F: include/drm/bridge/inno_hdmi.h
>
> DRM DRIVER FOR SYNAPTICS R63353 PANELS
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 026444eeb5c6..5413d87ef1d6 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -423,6 +423,8 @@ source "drivers/gpu/drm/sprd/Kconfig"
>
> source "drivers/gpu/drm/imagination/Kconfig"
>
> +source "drivers/gpu/drm/verisilicon/Kconfig"
> +
> config DRM_HYPERV
> tristate "DRM Support for Hyper-V synthetic video device"
> depends on DRM && PCI && MMU && HYPERV
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index f9ca4f8fa6c5..cb27092b1672 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -219,3 +219,4 @@ obj-y += solomon/
> obj-$(CONFIG_DRM_SPRD) += sprd/
> obj-$(CONFIG_DRM_LOONGSON) += loongson/
> obj-$(CONFIG_DRM_POWERVR) += imagination/
> +obj-$(CONFIG_DRM_VERISILICON_DC8200) += verisilicon/
> diff --git a/drivers/gpu/drm/verisilicon/Kconfig b/drivers/gpu/drm/verisilicon/Kconfig
> new file mode 100644
> index 000000000000..2d733f93439e
> --- /dev/null
> +++ b/drivers/gpu/drm/verisilicon/Kconfig
> @@ -0,0 +1,13 @@
> +# SPDX-License-Identifier: GPL-2.0
> +config DRM_VERISILICON_DC8200
> + tristate "DRM Support for VeriSilicon DC8200"
> + depends on DRM
> + select DRM_KMS_HELPER
> + select DRM_GEM_DMA_HELPER
> + select CMA
> + select DMA_CMA
> + help
> + Choose this option if you have a VeriSilicon DC8200 chipset.
> + This driver provides VeriSilicon kernel mode
> + setting and buffer management. It does not
> + provide 2D or 3D acceleration.
> diff --git a/drivers/gpu/drm/verisilicon/Makefile b/drivers/gpu/drm/verisilicon/Makefile
> new file mode 100644
> index 000000000000..7da54b259940
> --- /dev/null
> +++ b/drivers/gpu/drm/verisilicon/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +vs_drm-objs := vs_dc_hw.o
> +
> +obj-$(CONFIG_DRM_VERISILICON_DC8200) += vs_drm.o
> diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.c b/drivers/gpu/drm/verisilicon/vs_dc_hw.c
> new file mode 100644
> index 000000000000..69f020f8352f
> --- /dev/null
> +++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.c
> @@ -0,0 +1,1060 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
No changes in 2024?
> + */
> +
> +#include <linux/bits.h>
> +#include <linux/io.h>
> +#include <linux/media-bus-format.h>
> +//#include <drm/drm_atomic_helper.h>
Either uncomment or drop.
> +#include <drm/drm_blend.h>
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_framebuffer.h>
> +#include <drm/drm_fb_dma_helper.h>
> +
> +#include "vs_dc_hw.h"
> +
> +static const u32 horkernel[] = {
> + 0x00000000, 0x20000000, 0x00002000, 0x00000000,
> + 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000,
> + 0x00000000, 0x00000000, 0x181f0000, 0x000027e1,
> + 0x00000000, 0x00000000, 0x00000000, 0x2b981468,
> + 0x00000000, 0x00000000, 0x00000000, 0x10f00000,
> + 0x00002f10, 0x00000000, 0x00000000, 0x00000000,
> + 0x32390dc7, 0x00000000, 0x00000000, 0x00000000,
> + 0x0af50000, 0x0000350b, 0x00000000, 0x00000000,
> + 0x00000000, 0x3781087f, 0x00000000, 0x00000000,
> + 0x00000000, 0x06660000, 0x0000399a, 0x00000000,
> + 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000,
> + 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4,
> + 0x00000000, 0x00000000, 0x00000000, 0x3de1021f,
> + 0x00000000, 0x00000000, 0x00000000, 0x01470000,
> + 0x00003eb9, 0x00000000, 0x00000000, 0x00000000,
> + 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000,
> + 0x00480000, 0x00003fb8, 0x00000000, 0x00000000,
> + 0x00000000, 0x3fef0011, 0x00000000, 0x00000000,
> + 0x00000000, 0x00000000, 0x00004000, 0x00000000,
> + 0x00000000, 0x00000000, 0x20002000, 0x00000000,
> + 0x00000000, 0x00000000, 0x1c030000, 0x000023fd,
> + 0x00000000, 0x00000000, 0x00000000, 0x27e1181f,
> + 0x00000000, 0x00000000, 0x00000000, 0x14680000,
> + 0x00002b98, 0x00000000, 0x00000000, 0x00000000,
> + 0x2f1010f0, 0x00000000, 0x00000000, 0x00000000,
> + 0x0dc70000, 0x00003239, 0x00000000, 0x00000000,
> + 0x00000000, 0x350b0af5, 0x00000000, 0x00000000,
> + 0x00000000, 0x087f0000, 0x00003781, 0x00000000,
> + 0x00000000, 0x00000000, 0x399a0666, 0x00000000,
> + 0x00000000, 0x00000000, 0x04a70000, 0x00003b59,
> + 0x00000000, 0x00000000, 0x00000000, 0x3cc4033c,
> + 0x00000000, 0x00000000, 0x00000000, 0x021f0000,
> +};
> +
> +#define H_COEF_SIZE ARRAY_SIZE(horkernel)
> +
> +static const u32 verkernel[] = {
> + 0x00000000, 0x20000000, 0x00002000, 0x00000000,
> + 0x00000000, 0x00000000, 0x23fd1c03, 0x00000000,
> + 0x00000000, 0x00000000, 0x181f0000, 0x000027e1,
> + 0x00000000, 0x00000000, 0x00000000, 0x2b981468,
> + 0x00000000, 0x00000000, 0x00000000, 0x10f00000,
> + 0x00002f10, 0x00000000, 0x00000000, 0x00000000,
> + 0x32390dc7, 0x00000000, 0x00000000, 0x00000000,
> + 0x0af50000, 0x0000350b, 0x00000000, 0x00000000,
> + 0x00000000, 0x3781087f, 0x00000000, 0x00000000,
> + 0x00000000, 0x06660000, 0x0000399a, 0x00000000,
> + 0x00000000, 0x00000000, 0x3b5904a7, 0x00000000,
> + 0x00000000, 0x00000000, 0x033c0000, 0x00003cc4,
> + 0x00000000, 0x00000000, 0x00000000, 0x3de1021f,
> + 0x00000000, 0x00000000, 0x00000000, 0x01470000,
> + 0x00003eb9, 0x00000000, 0x00000000, 0x00000000,
> + 0x3f5300ad, 0x00000000, 0x00000000, 0x00000000,
> + 0x00480000, 0x00003fb8, 0x00000000, 0x00000000,
> + 0x00000000, 0x3fef0011, 0x00000000, 0x00000000,
> + 0x00000000, 0x00000000, 0x00004000, 0x00000000,
> + 0xcdcd0000, 0xfdfdfdfd, 0xabababab, 0xabababab,
> + 0x00000000, 0x00000000, 0x5ff5f456, 0x000f5f58,
> + 0x02cc6c78, 0x02cc0c28, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> + 0xfeeefeee, 0xfeeefeee, 0xfeeefeee, 0xfeeefeee,
> +};
> +
> +#define V_COEF_SIZE ARRAY_SIZE(verkernel)
> +
> +/*
> + * RGB 709->2020 conversion parameters
> + */
> +static const u16 RGB2RGB[RGB_TO_RGB_TABLE_SIZE] = {
> + 10279, 5395, 709,
> + 1132, 15065, 187,
> + 269, 1442, 14674
> +};
> +
> +/*
> + * YUV601 to RGB conversion parameters
> + * YUV2RGB[0] - [8] : C0 - C8;
> + * YUV2RGB[9] - [11]: D0 - D2;
> + * YUV2RGB[12] - [13]: Y clamp min & max calue;
> + * YUV2RGB[14] - [15]: UV clamp min & max calue;
> + */
> +static const s32 YUV601_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
> + 1196, 0, 1640, 1196,
> + -404, -836, 1196, 2076,
> + 0, -916224, 558336, -1202944,
> + 64, 940, 64, 960
> +};
> +
> +/*
> + * YUV709 to RGB conversion parameters
> + * YUV2RGB[0] - [8] : C0 - C8;
> + * YUV2RGB[9] - [11]: D0 - D2;
> + * YUV2RGB[12] - [13]: Y clamp min & max calue;
> + * YUV2RGB[14] - [15]: UV clamp min & max calue;
> + */
> +static s32 YUV709_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
> + 1196, 0, 1844, 1196,
> + -220, -548, 1196, 2172,
> + 0, -1020672, 316672, -1188608,
> + 64, 940, 64, 960
> +};
> +
> +/*
> + * YUV2020 to RGB conversion parameters
> + * YUV2RGB[0] - [8] : C0 - C8;
> + * YUV2RGB[9] - [11]: D0 - D2;
> + * YUV2RGB[12] - [13]: Y clamp min & max calue;
> + * YUV2RGB[14] - [15]: UV clamp min & max calue;
> + */
> +static s32 YUV2020_2RGB[YUV_TO_RGB_TABLE_SIZE] = {
> + 1196, 0, 1724, 1196,
> + -192, -668, 1196, 2200,
> + 0, -959232, 363776, -1202944,
> + 64, 940, 64, 960
> +};
> +
> +/*
> + * RGB to YUV2020 conversion parameters
> + * RGB2YUV[0] - [8] : C0 - C8;
> + * RGB2YUV[9] - [11]: D0 - D2;
> + */
> +static s16 RGB2YUV[RGB_TO_YUV_TABLE_SIZE] = {
> + 230, 594, 52,
> + -125, -323, 448,
> + 448, -412, -36,
> + 64, 512, 512
Please fix spaces vs tabs here.
> +};
> +
> +/* one is for primary plane and the other is for all overlay planes */
> +static const struct dc_hw_plane_reg dc_plane_reg[] = {
> + {
> + .y_address = DC_FRAMEBUFFER_ADDRESS,
> + .u_address = DC_FRAMEBUFFER_U_ADDRESS,
> + .v_address = DC_FRAMEBUFFER_V_ADDRESS,
> + .y_stride = DC_FRAMEBUFFER_STRIDE,
> + .u_stride = DC_FRAMEBUFFER_U_STRIDE,
> + .v_stride = DC_FRAMEBUFFER_V_STRIDE,
> + .size = DC_FRAMEBUFFER_SIZE,
> + .top_left = DC_FRAMEBUFFER_TOP_LEFT,
> + .bottom_right = DC_FRAMEBUFFER_BOTTOM_RIGHT,
> + .scale_factor_x = DC_FRAMEBUFFER_SCALE_FACTOR_X,
> + .scale_factor_y = DC_FRAMEBUFFER_SCALE_FACTOR_Y,
> + .h_filter_coef_index = DC_FRAMEBUFFER_H_FILTER_COEF_INDEX,
> + .h_filter_coef_data = DC_FRAMEBUFFER_H_FILTER_COEF_DATA,
> + .v_filter_coef_index = DC_FRAMEBUFFER_V_FILTER_COEF_INDEX,
> + .v_filter_coef_data = DC_FRAMEBUFFER_V_FILTER_COEF_DATA,
> + .init_offset = DC_FRAMEBUFFER_INIT_OFFSET,
> + .color_key = DC_FRAMEBUFFER_COLOR_KEY,
> + .color_key_high = DC_FRAMEBUFFER_COLOR_KEY_HIGH,
> + .clear_value = DC_FRAMEBUFFER_CLEAR_VALUE,
> + .color_table_index = DC_FRAMEBUFFER_COLOR_TABLE_INDEX,
> + .color_table_data = DC_FRAMEBUFFER_COLOR_TABLE_DATA,
> + .scale_config = DC_FRAMEBUFFER_SCALE_CONFIG,
> + .water_mark = DC_FRAMEBUFFER_WATER_MARK,
> + .degamma_index = DC_FRAMEBUFFER_DEGAMMA_INDEX,
> + .degamma_data = DC_FRAMEBUFFER_DEGAMMA_DATA,
> + .degamma_ex_data = DC_FRAMEBUFFER_DEGAMMA_EX_DATA,
> + .src_global_color = DC_FRAMEBUFFER_SRC_GLOBAL_COLOR,
> + .dst_global_color = DC_FRAMEBUFFER_DST_GLOBAL_COLOR,
> + .blend_config = DC_FRAMEBUFFER_BLEND_CONFIG,
> + .roi_origin = DC_FRAMEBUFFER_ROI_ORIGIN,
> + .roi_size = DC_FRAMEBUFFER_ROI_SIZE,
> + .yuv_to_rgb_coef0 = DC_FRAMEBUFFER_YUVTORGB_COEF0,
> + .yuv_to_rgb_coef1 = DC_FRAMEBUFFER_YUVTORGB_COEF1,
> + .yuv_to_rgb_coef2 = DC_FRAMEBUFFER_YUVTORGB_COEF2,
> + .yuv_to_rgb_coef3 = DC_FRAMEBUFFER_YUVTORGB_COEF3,
> + .yuv_to_rgb_coef4 = DC_FRAMEBUFFER_YUVTORGB_COEF4,
> + .yuv_to_rgb_coefd0 = DC_FRAMEBUFFER_YUVTORGB_COEFD0,
> + .yuv_to_rgb_coefd1 = DC_FRAMEBUFFER_YUVTORGB_COEFD1,
> + .yuv_to_rgb_coefd2 = DC_FRAMEBUFFER_YUVTORGB_COEFD2,
> + .y_clamp_bound = DC_FRAMEBUFFER_Y_CLAMP_BOUND,
> + .uv_clamp_bound = DC_FRAMEBUFFER_UV_CLAMP_BOUND,
> + .rgb_to_rgb_coef0 = DC_FRAMEBUFFER_RGBTORGB_COEF0,
> + .rgb_to_rgb_coef1 = DC_FRAMEBUFFER_RGBTORGB_COEF1,
> + .rgb_to_rgb_coef2 = DC_FRAMEBUFFER_RGBTORGB_COEF2,
> + .rgb_to_rgb_coef3 = DC_FRAMEBUFFER_RGBTORGB_COEF3,
> + .rgb_to_rgb_coef4 = DC_FRAMEBUFFER_RGBTORGB_COEF4,
> + },
> + {
> + .y_address = DC_OVERLAY_ADDRESS,
> + .u_address = DC_OVERLAY_U_ADDRESS,
> + .v_address = DC_OVERLAY_V_ADDRESS,
> + .y_stride = DC_OVERLAY_STRIDE,
> + .u_stride = DC_OVERLAY_U_STRIDE,
> + .v_stride = DC_OVERLAY_V_STRIDE,
> + .size = DC_OVERLAY_SIZE,
> + .top_left = DC_OVERLAY_TOP_LEFT,
> + .bottom_right = DC_OVERLAY_BOTTOM_RIGHT,
> + .scale_factor_x = DC_OVERLAY_SCALE_FACTOR_X,
> + .scale_factor_y = DC_OVERLAY_SCALE_FACTOR_Y,
> + .h_filter_coef_index = DC_OVERLAY_H_FILTER_COEF_INDEX,
> + .h_filter_coef_data = DC_OVERLAY_H_FILTER_COEF_DATA,
> + .v_filter_coef_index = DC_OVERLAY_V_FILTER_COEF_INDEX,
> + .v_filter_coef_data = DC_OVERLAY_V_FILTER_COEF_DATA,
> + .init_offset = DC_OVERLAY_INIT_OFFSET,
> + .color_key = DC_OVERLAY_COLOR_KEY,
> + .color_key_high = DC_OVERLAY_COLOR_KEY_HIGH,
> + .clear_value = DC_OVERLAY_CLEAR_VALUE,
> + .color_table_index = DC_OVERLAY_COLOR_TABLE_INDEX,
> + .color_table_data = DC_OVERLAY_COLOR_TABLE_DATA,
> + .scale_config = DC_OVERLAY_SCALE_CONFIG,
> + .water_mark = DC_OVERLAY_WATER_MARK,
> + .degamma_index = DC_OVERLAY_DEGAMMA_INDEX,
> + .degamma_data = DC_OVERLAY_DEGAMMA_DATA,
> + .degamma_ex_data = DC_OVERLAY_DEGAMMA_EX_DATA,
> + .src_global_color = DC_OVERLAY_SRC_GLOBAL_COLOR,
> + .dst_global_color = DC_OVERLAY_DST_GLOBAL_COLOR,
> + .blend_config = DC_OVERLAY_BLEND_CONFIG,
> + .roi_origin = DC_OVERLAY_ROI_ORIGIN,
> + .roi_size = DC_OVERLAY_ROI_SIZE,
> + .yuv_to_rgb_coef0 = DC_OVERLAY_YUVTORGB_COEF0,
> + .yuv_to_rgb_coef1 = DC_OVERLAY_YUVTORGB_COEF1,
> + .yuv_to_rgb_coef2 = DC_OVERLAY_YUVTORGB_COEF2,
> + .yuv_to_rgb_coef3 = DC_OVERLAY_YUVTORGB_COEF3,
> + .yuv_to_rgb_coef4 = DC_OVERLAY_YUVTORGB_COEF4,
> + .yuv_to_rgb_coefd0 = DC_OVERLAY_YUVTORGB_COEFD0,
> + .yuv_to_rgb_coefd1 = DC_OVERLAY_YUVTORGB_COEFD1,
> + .yuv_to_rgb_coefd2 = DC_OVERLAY_YUVTORGB_COEFD2,
> + .y_clamp_bound = DC_OVERLAY_Y_CLAMP_BOUND,
> + .uv_clamp_bound = DC_OVERLAY_UV_CLAMP_BOUND,
> + .rgb_to_rgb_coef0 = DC_OVERLAY_RGBTORGB_COEF0,
> + .rgb_to_rgb_coef1 = DC_OVERLAY_RGBTORGB_COEF1,
> + .rgb_to_rgb_coef2 = DC_OVERLAY_RGBTORGB_COEF2,
> + .rgb_to_rgb_coef3 = DC_OVERLAY_RGBTORGB_COEF3,
> + .rgb_to_rgb_coef4 = DC_OVERLAY_RGBTORGB_COEF4,
> + },
> +};
> +
> +static inline u32 hi_read(struct dc_hw *hw, u32 reg)
> +{
> + return readl(hw->hi_base + reg);
> +}
> +
> +static inline void hi_write(struct dc_hw *hw, u32 reg, u32 value)
> +{
> + writel(value, hw->hi_base + reg);
> +}
> +
> +static inline void dc_write(struct dc_hw *hw, u32 reg, u32 value)
> +{
> + writel(value, hw->reg_base + reg - DC_REG_BASE);
> +}
> +
> +static inline u32 dc_read(struct dc_hw *hw, u32 reg)
> +{
> + u32 value = readl(hw->reg_base + reg - DC_REG_BASE);
> +
> + return value;
just return readl(...)
> +}
> +
> +static inline void dc_set_clear(struct dc_hw *hw, u32 reg, u32 set, u32 clear)
> +{
> + u32 value = dc_read(hw, reg);
> +
> + value &= ~clear;
> + value |= set;
> + dc_write(hw, reg, value);
regmap_update_bits?
> +}
> +
> +static void load_default_filter(struct dc_hw *hw,
> + const struct dc_hw_plane_reg *reg, u32 offset)
> +{
> + u8 i;
> +
> + dc_write(hw, reg->scale_config + offset, 0x33);
> + dc_write(hw, reg->init_offset + offset, 0x80008000);
> + dc_write(hw, reg->h_filter_coef_index + offset, 0x00);
> + for (i = 0; i < H_COEF_SIZE; i++)
> + dc_write(hw, reg->h_filter_coef_data + offset, horkernel[i]);
> +
> + dc_write(hw, reg->v_filter_coef_index + offset, 0x00);
> + for (i = 0; i < V_COEF_SIZE; i++)
> + dc_write(hw, reg->v_filter_coef_data + offset, verkernel[i]);
> +}
> +
> +static void load_rgb_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg,
> + u32 offset, const u16 *table)
> +{
> + dc_write(hw, reg->rgb_to_rgb_coef0 + offset, table[0] | (table[1] << 16));
> + dc_write(hw, reg->rgb_to_rgb_coef1 + offset, table[2] | (table[3] << 16));
> + dc_write(hw, reg->rgb_to_rgb_coef2 + offset, table[4] | (table[5] << 16));
> + dc_write(hw, reg->rgb_to_rgb_coef3 + offset, table[6] | (table[7] << 16));
> + dc_write(hw, reg->rgb_to_rgb_coef4 + offset, table[8]);
> +}
> +
> +static void load_yuv_to_rgb(struct dc_hw *hw, const struct dc_hw_plane_reg *reg,
> + u32 offset, const s32 *table)
> +{
> + dc_write(hw, reg->yuv_to_rgb_coef0 + offset,
> + (0xFFFF & table[0]) | (table[1] << 16));
> + dc_write(hw, reg->yuv_to_rgb_coef1 + offset,
> + (0xFFFF & table[2]) | (table[3] << 16));
> + dc_write(hw, reg->yuv_to_rgb_coef2 + offset,
> + (0xFFFF & table[4]) | (table[5] << 16));
> + dc_write(hw, reg->yuv_to_rgb_coef3 + offset,
> + (0xFFFF & table[6]) | (table[7] << 16));
> + dc_write(hw, reg->yuv_to_rgb_coef4 + offset, table[8]);
> + dc_write(hw, reg->yuv_to_rgb_coefd0 + offset, table[9]);
> + dc_write(hw, reg->yuv_to_rgb_coefd1 + offset, table[10]);
> + dc_write(hw, reg->yuv_to_rgb_coefd2 + offset, table[11]);
> + dc_write(hw, reg->y_clamp_bound + offset, table[12] | (table[13] << 16));
> + dc_write(hw, reg->uv_clamp_bound + offset, table[14] | (table[15] << 16));
> +}
> +
> +static void load_rgb_to_yuv(struct dc_hw *hw, u32 offset, s16 *table)
Is there any reason why load_rgb_to_yuv differs from two other
functions?
> +{
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF0 + offset,
> + table[0] | (table[1] << 16));
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF1 + offset,
> + table[2] | (table[3] << 16));
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF2 + offset,
> + table[4] | (table[5] << 16));
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF3 + offset,
> + table[6] | (table[7] << 16));
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEF4 + offset, table[8]);
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD0 + offset, table[9]);
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD1 + offset, table[10]);
> + dc_write(hw, DC_DISPLAY_RGBTOYUV_COEFD2 + offset, table[11]);
> +}
> +
> +static int update_vs_format(u32 drm_format)
> +{
> + u8 f = FORMAT_A8R8G8B8;
> +
> + switch (drm_format) {
> + case DRM_FORMAT_XRGB4444:
> + case DRM_FORMAT_RGBX4444:
> + case DRM_FORMAT_XBGR4444:
> + case DRM_FORMAT_BGRX4444:
> + f = FORMAT_X4R4G4B4;
> + break;
> + case DRM_FORMAT_ARGB4444:
> + case DRM_FORMAT_RGBA4444:
> + case DRM_FORMAT_ABGR4444:
> + case DRM_FORMAT_BGRA4444:
> + f = FORMAT_A4R4G4B4;
> + break;
> + case DRM_FORMAT_XRGB1555:
> + case DRM_FORMAT_RGBX5551:
> + case DRM_FORMAT_XBGR1555:
> + case DRM_FORMAT_BGRX5551:
> + f = FORMAT_X1R5G5B5;
> + break;
> + case DRM_FORMAT_ARGB1555:
> + case DRM_FORMAT_RGBA5551:
> + case DRM_FORMAT_ABGR1555:
> + case DRM_FORMAT_BGRA5551:
> + f = FORMAT_A1R5G5B5;
> + break;
> + case DRM_FORMAT_RGB565:
> + case DRM_FORMAT_BGR565:
> + f = FORMAT_R5G6B5;
> + break;
> + case DRM_FORMAT_XRGB8888:
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_BGRX8888:
> + f = FORMAT_X8R8G8B8;
> + break;
> + case DRM_FORMAT_ARGB8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_BGRA8888:
> + f = FORMAT_A8R8G8B8;
> + break;
> + case DRM_FORMAT_YUYV:
> + case DRM_FORMAT_YVYU:
> + f = FORMAT_YUY2;
> + break;
> + case DRM_FORMAT_UYVY:
> + case DRM_FORMAT_VYUY:
> + f = FORMAT_UYVY;
> + break;
> + case DRM_FORMAT_YUV420:
> + case DRM_FORMAT_YVU420:
> + f = FORMAT_YV12;
> + break;
> + case DRM_FORMAT_NV21:
> + f = FORMAT_NV12;
> + break;
> + case DRM_FORMAT_NV16:
> + case DRM_FORMAT_NV61:
> + f = FORMAT_NV16;
> + break;
> + case DRM_FORMAT_P010:
> + f = FORMAT_P010;
> + break;
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_BGRA1010102:
> + f = FORMAT_A2R10G10B10;
> + break;
> + case DRM_FORMAT_NV12:
> + f = FORMAT_NV12;
> + break;
> + case DRM_FORMAT_YUV444:
> + f = FORMAT_YUV444;
s/f = /return /g all over the place.
> + break;
> + default:
return -EINVAL;
> + break;
> + }
> +
> + return f;
> +}
> +
> +int dc_hw_init(struct vs_dc *dc)
> +{
> + u8 i, id, panel_num, layer_num;
> + struct dc_hw *hw = &dc->hw;
> + u32 offset;
> +
> + layer_num = hw->info->layer_num;
> + for (i = 0; i < layer_num; i++) {
> + id = dc->planes[i].id;
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + hw->reg[i] = dc_plane_reg[0];
> + else
> + hw->reg[i] = dc_plane_reg[1];
> +
> + load_default_filter(hw, &hw->reg[i], dc->planes[i].offset);
> + load_rgb_to_rgb(hw, &hw->reg[i], dc->planes[i].offset, RGB2RGB);
> + }
> +
> + panel_num = hw->info->panel_num;
> + for (i = 0; i < panel_num; i++) {
> + offset = i << 2;
> +
> + load_rgb_to_yuv(hw, offset, RGB2YUV);
> + dc_write(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0x111);
> +
> + offset = i ? DC_CURSOR_OFFSET : 0;
> + dc_write(hw, DC_CURSOR_BACKGROUND + offset, 0x00FFFFFF);
> + dc_write(hw, DC_CURSOR_FOREGROUND + offset, 0x00AAAAAA);
> + }
> +
> + return 0;
> +}
> +
> +void dc_hw_disable_plane(struct vs_dc *dc, u8 id)
> +{
> + struct dc_hw *hw = &dc->hw;
> +
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + dc->planes[id].offset,
> + PRIMARY_EN(false), PRIMARY_EN_MASK);
> + else
> + dc_set_clear(hw, DC_OVERLAY_CONFIG + dc->planes[id].offset,
> + OVERLAY_FB_EN(false), OVERLAY_FB_EN_MASK);
> +}
> +
> +static int update_cursor_size(uint32_t crtc_w)
get_cursor_size()
> +{
> + u8 size_type;
> +
> + switch (crtc_w) {
> + case 32:
> + size_type = CURSOR_SIZE_32X32;
> + break;
> + case 64:
> + size_type = CURSOR_SIZE_64X64;
> + break;
> + default:
> + size_type = CURSOR_SIZE_32X32;
> + break;
> + }
> +
> + return size_type;
Same comment. Return directly without extra variable assignments.
> +}
> +
> +void dc_hw_update_cursor(struct dc_hw *hw, u8 id, dma_addr_t dma_addr,
> + u32 crtc_w, u32 crtc_x, u32 crtc_y,
> + s32 hotspot_x, s32 hotspot_y)
> +{
> + u32 offset, size;
> +
> + offset = id ? DC_CURSOR_OFFSET : 0;
> + size = update_cursor_size(crtc_w);
> +
> + dc_write(hw, DC_CURSOR_ADDRESS + offset,
> + dma_addr);
> + dc_write(hw, DC_CURSOR_LOCATION + offset,
> + X_LCOTION(crtc_x) |
> + Y_LCOTION(crtc_y));
> + dc_set_clear(hw, DC_CURSOR_CONFIG + offset,
> + CURSOR_HOT_X(hotspot_x) |
> + CURSOR_HOT_y(hotspot_y) |
> + CURSOR_SIZE(size) |
> + CURSOR_VALID(1) |
> + CURSOR_TRIG_FETCH(1) |
> + CURSOR_FORMAT(CURSOR_FORMAT_A8R8G8B8),
> + CURSOR_HOT_X_MASK |
> + CURSOR_HOT_y_MASK |
> + CURSOR_SIZE_MASK |
> + CURSOR_VALID_MASK |
> + CURSOR_TRIG_FETCH_MASK |
> + CURSOR_FORMAT_MASK);
> +}
> +
> +void dc_hw_disable_cursor(struct dc_hw *hw, u8 id)
> +{
> + u32 offset = 0;
> +
> + offset = id ? DC_CURSOR_OFFSET : 0;
> + dc_set_clear(hw, DC_CURSOR_CONFIG + offset, CURSOR_VALID(1), CURSOR_FORMAT_MASK);
> +}
> +
> +void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index,
> + u16 r, u16 g, u16 b)
> +{
> + if (index >= hw->info->gamma_size)
> + return;
> +
> + hw->gamma[id].gamma[index][0] = r;
> + hw->gamma[id].gamma[index][1] = g;
> + hw->gamma[id].gamma[index][2] = b;
> +}
> +
> +void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable)
> +{
> + u32 value;
> +
> + if (enable) {
> + dc_write(hw, DC_DISPLAY_GAMMA_EX_INDEX + (id << 2), 0x00);
> + for (int i = 0; i < GAMMA_EX_SIZE; i++) {
> + value = hw->gamma[id].gamma[i][2] |
> + (hw->gamma[id].gamma[i][1] << 12);
> + dc_write(hw, DC_DISPLAY_GAMMA_EX_DATA + (id << 2), value);
> + dc_write(hw, DC_DISPLAY_GAMMA_EX_ONE_DATA + (id << 2),
> + hw->gamma[id].gamma[i][0]);
> + }
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (id << 2), PANEL_GAMMA_EN, 0);
> + } else {
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + (id << 2), 0, PANEL_GAMMA_EN);
> + }
> +}
> +
> +void dc_hw_enable(struct dc_hw *hw, int id, struct drm_display_mode *mode,
> + u8 encoder_type, u32 output_fmt)
> +{
> + u32 dp_cfg, dpi_cfg, offset = id << 2;
> + bool is_yuv = false;
> +
> + if (encoder_type != DRM_MODE_ENCODER_DSI) {
> + switch (output_fmt) {
> + case MEDIA_BUS_FMT_RGB565_1X16:
> + dp_cfg = 0;
> + break;
> + case MEDIA_BUS_FMT_RGB666_1X18:
> + dp_cfg = 1;
> + break;
> + case MEDIA_BUS_FMT_RGB888_1X24:
> + dp_cfg = 2;
> + break;
> + case MEDIA_BUS_FMT_RGB101010_1X30:
> + dp_cfg = 3;
> + break;
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + dp_cfg = 2 << 4;
> + is_yuv = true;
> + break;
> + case MEDIA_BUS_FMT_YUV8_1X24:
> + dp_cfg = 4 << 4;
> + is_yuv = true;
> + break;
> + case MEDIA_BUS_FMT_UYVY10_1X20:
> + dp_cfg = 8 << 4;
> + is_yuv = true;
> + break;
> + case MEDIA_BUS_FMT_YUV10_1X30:
> + dp_cfg = 10 << 4;
> + is_yuv = true;
> + break;
> + case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
> + dp_cfg = 12 << 4;
> + is_yuv = true;
> + break;
> + case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
> + dp_cfg = 13 << 4;
> + is_yuv = true;
> + break;
> + default:
> + dp_cfg = 2;
> + break;
> + }
> + if (is_yuv)
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, PANEL_RGB2YUV_EN, 0);
> + else
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, PANEL_RGB2YUV_EN);
> + dc_write(hw, DC_DISPLAY_DP_CONFIG + offset, dp_cfg | DP_SELECT);
> + }
> +
> + if (hw->out[id] == OUT_DPI)
> + dc_set_clear(hw, DC_DISPLAY_DP_CONFIG + offset, 0, DP_SELECT);
> +
> + switch (output_fmt) {
> + case MEDIA_BUS_FMT_RGB565_1X16:
> + dpi_cfg = 0;
> + break;
> + case MEDIA_BUS_FMT_RGB666_1X18:
> + dpi_cfg = 3;
> + break;
> + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
> + dpi_cfg = 4;
> + break;
> + case MEDIA_BUS_FMT_RGB888_1X24:
> + dpi_cfg = 5;
> + break;
> + case MEDIA_BUS_FMT_RGB101010_1X30:
> + dpi_cfg = 6;
> + break;
> + default:
> + dpi_cfg = 5;
> + break;
> + }
> + dc_write(hw, DC_DISPLAY_DPI_CONFIG + offset, dpi_cfg);
> +
> + if (id == 0)
> + dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, PANEL0_EN | TWO_PANEL_EN);
> + else
> + dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, PANEL1_EN | TWO_PANEL_EN);
> +
> + dc_write(hw, DC_DISPLAY_H + offset,
> + H_ACTIVE_LEN(mode->hdisplay) |
> + H_TOTAL_LEN(mode->htotal));
> +
> + dc_write(hw, DC_DISPLAY_H_SYNC + offset,
> + H_SYNC_START_LEN(mode->hsync_start) |
> + H_SYNC_END_LEN(mode->hsync_end) |
> + H_POLARITY_LEN(mode->flags & DRM_MODE_FLAG_PHSYNC ? 0 : 1) |
> + H_PLUS_LEN(1));
> +
> + dc_write(hw, DC_DISPLAY_V + offset,
> + V_ACTIVE_LEN(mode->vdisplay) |
> + V_TOTAL_LEN(mode->vtotal));
> +
> + dc_write(hw, DC_DISPLAY_V_SYNC + offset,
> + V_SYNC_START_LEN(mode->vsync_start) |
> + V_SYNC_END_LEN(mode->vsync_end) |
> + V_POLARITY_LEN(mode->flags & DRM_MODE_FLAG_PVSYNC ? 0 : 1) |
> + V_PLUS_LEN(1));
> +
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, PANEL_OUTPUT_EN, 0);
> + dc_set_clear(hw, DC_DISPLAY_PANEL_START, BIT(id), SYNC_EN);
> +}
> +
> +void dc_hw_disable(struct dc_hw *hw, int id)
> +{
> + u32 offset = id << 2;
> +
> + if (hw->out[id] == OUT_DPI)
> + dc_set_clear(hw, DC_DISPLAY_DP_CONFIG + offset, 0, DP_SELECT);
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG + offset, 0, PANEL_OUTPUT_EN);
> + dc_set_clear(hw, DC_DISPLAY_PANEL_START, 0, BIT(id) | TWO_PANEL_EN);
> +}
> +
> +void dc_hw_enable_interrupt(struct dc_hw *hw)
> +{
> + hi_write(hw, AQ_INTR_ENBL, 0xFFFFFFFF);
> +}
> +
> +void dc_hw_disable_interrupt(struct dc_hw *hw)
> +{
> + hi_write(hw, AQ_INTR_ENBL, 0);
> +}
> +
> +u32 dc_hw_get_interrupt(struct dc_hw *hw)
> +{
> + return hi_read(hw, AQ_INTR_ACKNOWLEDGE);
> +}
> +
> +void dc_hw_enable_shadow_register(struct vs_dc *dc, bool enable)
> +{
> + u32 i, offset;
> + struct dc_hw *hw = &dc->hw;
> + u8 id, layer_num = hw->info->layer_num;
> + u8 panel_num = hw->info->panel_num;
> +
> + for (i = 0; i < layer_num; i++) {
> + id = dc->planes[i].id;
> + offset = dc->planes[i].offset;
> + if (enable) {
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
> + PRIMARY_SHADOW_EN, 0);
> + else
> + dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
> + OVERLAY_SHADOW_EN, 0);
> + } else {
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
> + 0, PRIMARY_SHADOW_EN);
> + else
> + dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
> + 0, OVERLAY_SHADOW_EN);
> + }
> + }
> +
> + for (i = 0; i < panel_num; i++) {
> + offset = i << 2;
> + if (enable)
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, 0, PANEL_SHADOW_EN);
> + else
> + dc_set_clear(hw, DC_DISPLAY_PANEL_CONFIG_EX + offset, PANEL_SHADOW_EN, 0);
> + }
> +}
> +
> +void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id)
> +{
> + if (out <= OUT_DP)
This doesn't scale if you add another output type. Please either add
OUT_MAX or consider something which doesn't make OUT_DP special.
> + hw->out[id] = out;
> +}
> +
> +static inline u8 to_vs_yuv_color_space(u32 color_space)
> +{
> + u8 cs;
> +
> + switch (color_space) {
> + case DRM_COLOR_YCBCR_BT601:
> + cs = COLOR_SPACE_601;
> + break;
> + case DRM_COLOR_YCBCR_BT709:
> + cs = COLOR_SPACE_709;
> + break;
> + case DRM_COLOR_YCBCR_BT2020:
> + cs = COLOR_SPACE_2020;
> + break;
> + default:
> + cs = COLOR_SPACE_601;
> + break;
> + }
> +
> + return cs;
> +}
> +
> +static inline u8 update_uv_swizzle(u32 format)
> +{
> + u8 uv_swizzle = 0;
> +
> + switch (format) {
> + case DRM_FORMAT_YVYU:
> + case DRM_FORMAT_VYUY:
> + case DRM_FORMAT_NV21:
> + case DRM_FORMAT_NV61:
> + uv_swizzle = 1;
> + break;
> + default:
> + break;
> + }
> +
> + return uv_swizzle;
> +}
> +
> +static inline u8 update_swizzle(u32 format)
> +{
> + u8 swizzle = SWIZZLE_ARGB;
> +
> + switch (format) {
> + case DRM_FORMAT_RGBX4444:
> + case DRM_FORMAT_RGBA4444:
> + case DRM_FORMAT_RGBX5551:
> + case DRM_FORMAT_RGBA5551:
> + case DRM_FORMAT_RGBX8888:
> + case DRM_FORMAT_RGBA8888:
> + case DRM_FORMAT_RGBA1010102:
> + swizzle = SWIZZLE_RGBA;
> + break;
> + case DRM_FORMAT_XBGR4444:
> + case DRM_FORMAT_ABGR4444:
> + case DRM_FORMAT_XBGR1555:
> + case DRM_FORMAT_ABGR1555:
> + case DRM_FORMAT_BGR565:
> + case DRM_FORMAT_XBGR8888:
> + case DRM_FORMAT_ABGR8888:
> + case DRM_FORMAT_ABGR2101010:
> + swizzle = SWIZZLE_ABGR;
> + break;
> + case DRM_FORMAT_BGRX4444:
> + case DRM_FORMAT_BGRA4444:
> + case DRM_FORMAT_BGRX5551:
> + case DRM_FORMAT_BGRA5551:
> + case DRM_FORMAT_BGRX8888:
> + case DRM_FORMAT_BGRA8888:
> + case DRM_FORMAT_BGRA1010102:
> + swizzle = SWIZZLE_BGRA;
> + break;
> + default:
> + break;
> + }
> +
> + return swizzle;
> +}
> +
> +static inline u8 to_vs_rotation(unsigned int rotation)
> +{
> + u8 rot;
> +
> + switch (rotation & DRM_MODE_REFLECT_MASK) {
> + case DRM_MODE_REFLECT_X:
> + rot = FLIP_X;
> + return rot;
> + case DRM_MODE_REFLECT_Y:
> + rot = FLIP_Y;
> + return rot;
> + case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
> + rot = FLIP_XY;
> + return rot;
> + default:
> + break;
> + }
> +
> + switch (rotation & DRM_MODE_ROTATE_MASK) {
> + case DRM_MODE_ROTATE_0:
> + rot = ROT_0;
> + break;
> + case DRM_MODE_ROTATE_90:
> + rot = ROT_90;
> + break;
> + case DRM_MODE_ROTATE_180:
> + rot = ROT_180;
> + break;
> + case DRM_MODE_ROTATE_270:
> + rot = ROT_270;
> + break;
> + default:
> + rot = ROT_0;
> + break;
> + }
> +
> + return rot;
> +}
> +
> +void plane_hw_update_format_colorspace(struct vs_dc *dc, u32 format,
> + enum drm_color_encoding encoding, u8 id, bool is_yuv)
> +{
> + u32 offset = dc->planes[id].offset;
> + struct dc_hw *hw = &dc->hw;
> +
> + if (is_yuv) {
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
> + PRIMARY_YUVCLAMP_EN, PRIMARY_RGB2RGB_EN);
> + else
> + dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
> + OVERLAY_CLAMP_EN, OVERLAY_RGB2RGB_EN);
> +
> + switch (to_vs_yuv_color_space(encoding)) {
> + case COLOR_SPACE_601:
> + load_yuv_to_rgb(hw, &hw->reg[id], offset, YUV601_2RGB);
> + break;
> + case COLOR_SPACE_709:
> + load_yuv_to_rgb(hw, &hw->reg[id], offset, YUV709_2RGB);
> + break;
> + case COLOR_SPACE_2020:
> + load_yuv_to_rgb(hw, &hw->reg[id], offset, YUV2020_2RGB);
> + break;
> + default:
> + break;
> + }
> + } else {
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
> + PRIMARY_RGB2RGB_EN, PRIMARY_YUVCLAMP_EN);
> + else
> + dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
> + OVERLAY_RGB2RGB_EN, OVERLAY_CLAMP_EN);
> + }
> +}
> +
> +void plane_hw_update_address(struct vs_dc *dc, u8 id, u32 format, dma_addr_t *dma_addr,
> + struct drm_framebuffer *drm_fb, struct drm_rect *src)
> +{
> + u32 offset = dc->planes[id].offset;
> + struct dc_hw *hw = &dc->hw;
> +
> + dc_write(hw, hw->reg[id].y_address + offset, dma_addr[0]);
> + dc_write(hw, hw->reg[id].u_address + offset,
> + format == DRM_FORMAT_YVU420 ?
> + dma_addr[2] : dma_addr[1]);
> + dc_write(hw, hw->reg[id].v_address + offset,
> + format == DRM_FORMAT_YVU420 ?
> + dma_addr[1] : dma_addr[2]);
> + dc_write(hw, hw->reg[id].y_stride + offset, drm_fb->pitches[0]);
> + dc_write(hw, hw->reg[id].u_stride + offset,
> + format == DRM_FORMAT_YVU420 ?
> + drm_fb->pitches[2] : drm_fb->pitches[1]);
> + dc_write(hw, hw->reg[id].v_stride + offset,
> + format == DRM_FORMAT_YVU420 ?
> + drm_fb->pitches[1] : drm_fb->pitches[2]);
> + dc_write(hw, hw->reg[id].size + offset,
> + FB_SIZE(drm_rect_width(src) >> 16, drm_rect_height(src) >> 16));
> +}
> +
> +void plane_hw_update_format(struct vs_dc *dc, u32 format, enum drm_color_encoding encoding,
> + unsigned int rotation, bool visible, unsigned int zpos,
> + u8 id, u8 display_id)
> +{
> + u32 offset = dc->planes[id].offset;
> + struct dc_hw *hw = &dc->hw;
> +
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1) {
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset,
> + PRIMARY_FORMAT(update_vs_format(format)) |
> + PRIMARY_UV_SWIZ(update_uv_swizzle(format)) |
> + PRIMARY_SWIZ(update_swizzle(format)) |
> + PRIMARY_TILE(DRM_FORMAT_MOD_LINEAR) |
> + PRIMARY_YUV_COLOR(to_vs_yuv_color_space(encoding)) |
> + PRIMARY_ROTATION(to_vs_rotation(rotation)),
> + PRIMARY_FORMAT_MASK |
> + PRIMARY_UV_SWIZ_MASK |
> + PRIMARY_SWIZ_MASK |
> + PRIMARY_TILE_MASK |
> + PRIMARY_YUV_COLOR_MASK |
> + PRIMARY_ROTATION_MASK |
> + PRIMARY_CLEAR_EN_MASK);
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG_EX + offset,
> + PRIMARY_DECODER_EN(false) |
> + PRIMARY_EN(visible) |
> + PRIMARY_ZPOS(zpos) |
> + PRIMARY_CHANNEL(display_id),
> + PRIMARY_DECODER_EN_EN_MASK |
> + PRIMARY_EN_MASK |
> + PRIMARY_ZPOS_MASK |
> + PRIMARY_CHANNEL_MASK);
> + } else {
> + dc_set_clear(hw, DC_OVERLAY_CONFIG + offset,
> + OVERLAY_FB_EN(visible) |
> + OVERLAY_FORMAT(update_vs_format(format)) |
> + OVERLAY_UV_SWIZ(update_uv_swizzle(format)) |
> + OVERLAY_SWIZ(update_swizzle(format)) |
> + OVERLAY_TILE(DRM_FORMAT_MOD_LINEAR) |
> + OVERLAY_YUV_COLOR(to_vs_yuv_color_space(encoding)) |
> + OVERLAY_ROTATION(to_vs_rotation(rotation)),
> + OVERLAY_DEC_EN_MASK |
> + OVERLAY_CLEAR_EN_MASK |
> + OVERLAY_FB_EN_MASK |
> + OVERLAY_FORMAT_MASK |
> + OVERLAY_UV_SWIZ_MASK |
> + OVERLAY_SWIZ_MASK |
> + OVERLAY_TILE_MASK |
> + OVERLAY_YUV_COLOR_MASK |
> + OVERLAY_ROTATION_MASK);
> +
> + dc_set_clear(hw, DC_OVERLAY_CONFIG_EX + offset,
> + OVERLAY_LAYER_SEL(zpos) |
> + OVERLAY_PANEL_SEL(display_id),
> + OVERLAY_LAYER_SEL_MASK |
> + OVERLAY_PANEL_SEL_MASK);
> + }
> +}
> +
> +static u32 calc_factor(u32 src, u32 dest)
A comment is appreciated.
> +{
> + u32 factor = 1 << 16;
> +
> + if (src > 1 && dest > 1)
> + factor = ((src - 1) << 16) / (dest - 1);
> +
> + return factor;
> +}
> +
> +void plane_hw_update_scale(struct vs_dc *dc, struct drm_rect *src, struct drm_rect *dst,
> + u8 id, u8 display_id, unsigned int rotation)
> +{
> + u32 offset = dc->planes[id].offset;
> + struct dc_hw *hw = &dc->hw;
> +
> + int dst_w = drm_rect_width(dst);
> + int dst_h = drm_rect_height(dst);
> + int src_w, src_h, temp;
> + u32 scale_factor_x;
> + u32 scale_factor_y;
> + bool enable_scale = false;
> +
> + src_w = drm_rect_width(src) >> 16;
> + src_h = drm_rect_height(src) >> 16;
> +
> + if (drm_rotation_90_or_270(rotation)) {
> + temp = src_w;
> + src_w = src_h;
> + src_h = temp;
> + }
> +
> + if (src_w != dst_w) {
> + scale_factor_x = calc_factor(src_w, dst_w);
> + enable_scale = true;
> + } else {
> + scale_factor_x = 1 << 16;
> + }
> + if (src_h != dst_h) {
> + scale_factor_y = calc_factor(src_h, dst_h);
> + enable_scale = true;
> + } else {
> + scale_factor_y = 1 << 16;
> + }
> + if (enable_scale) {
> + dc_write(hw, hw->reg[id].scale_factor_x + offset, scale_factor_x);
> + dc_write(hw, hw->reg[id].scale_factor_y + offset, scale_factor_y);
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset, PRIMARY_SCALE_EN, 0);
> + else
> + dc_set_clear(hw, DC_OVERLAY_SCALE_CONFIG + offset, OVERLAY_SCALE_EN, 0);
> + } else {
> + if (id == PRIMARY_PLANE_0 || id == PRIMARY_PLANE_1)
> + dc_set_clear(hw, DC_FRAMEBUFFER_CONFIG + offset, 0, PRIMARY_SCALE_EN);
> + else
> + dc_set_clear(hw, DC_OVERLAY_SCALE_CONFIG + offset, 0, OVERLAY_SCALE_EN);
> + }
> +
> + dc_write(hw, hw->reg[id].top_left + offset, X_POS(dst->x1) | Y_POS(dst->y1));
> + dc_write(hw, hw->reg[id].bottom_right + offset, X_POS(dst->x2) | Y_POS(dst->y2));
> +}
> +
> +void plane_hw_update_blend(struct vs_dc *dc, u16 alpha,
> + u16 pixel_blend_mode, u8 id, u8 display_id)
> +{
> + u32 offset = dc->planes[id].offset;
> + struct dc_hw *hw = &dc->hw;
> +
> + dc_write(hw, hw->reg[id].src_global_color + offset, PRIMARY_ALPHA_LEN(alpha >> 8));
> + dc_write(hw, hw->reg[id].dst_global_color + offset, PRIMARY_ALPHA_LEN(alpha >> 8));
> + switch (pixel_blend_mode) {
> + case DRM_MODE_BLEND_PREMULTI:
> + dc_write(hw, hw->reg[id].blend_config + offset, BLEND_PREMULTI);
> + break;
> + case DRM_MODE_BLEND_COVERAGE:
> + dc_write(hw, hw->reg[id].blend_config + offset, BLEND_COVERAGE);
> + break;
> + case DRM_MODE_BLEND_PIXEL_NONE:
> + dc_write(hw, hw->reg[id].blend_config + offset, BLEND_PIXEL_NONE);
> + break;
> + default:
> + break;
> + }
> +}
> diff --git a/drivers/gpu/drm/verisilicon/vs_dc_hw.h b/drivers/gpu/drm/verisilicon/vs_dc_hw.h
> new file mode 100644
> index 000000000000..63d8d153f57f
> --- /dev/null
> +++ b/drivers/gpu/drm/verisilicon/vs_dc_hw.h
> @@ -0,0 +1,493 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
> + */
> +
> +#ifndef __VS_DC_HW_H__
> +#define __VS_DC_HW_H__
> +
> +#include <linux/bitfield.h>
> +#include <linux/bits.h>
> +#include <drm/drm_atomic.h>
> +
> +#include "vs_type.h"
> +
> +#define UPDATE(x, h, l) FIELD_PREP(GENMASK(h, l), x)
> +
> +#define AQ_INTR_ACKNOWLEDGE 0x0010
> +#define AQ_INTR_ENBL 0x0014
> +#define DC_HW_REVISION 0x0024
> +#define DC_HW_CHIP_CID 0x0030
> +
> +#define DC_REG_BASE 0x0800
> +#define DC_REG_RANGE 0x2000
> +#define DC_SEC_REG_OFFSET 0x100000
> +
> +#define DC_FRAMEBUFFER_CONFIG 0x1518
> +# define PRIMARY_FORMAT(x) ((x) << 26)
> +# define PRIMARY_FORMAT_MASK GENMASK(31, 26)
> +# define PRIMARY_UV_SWIZ(x) ((x) << 25)
> +# define PRIMARY_UV_SWIZ_MASK GENMASK(25, 25)
> +# define PRIMARY_SWIZ(x) ((x) << 23)
> +# define PRIMARY_SWIZ_MASK GENMASK(24, 23)
> +# define PRIMARY_SCALE_EN BIT(12)
> +# define PRIMARY_TILE(x) ((x) << 17)
> +# define PRIMARY_TILE_MASK GENMASK(21, 17)
> +# define PRIMARY_YUV_COLOR(x) ((x) << 14)
> +# define PRIMARY_YUV_COLOR_MASK GENMASK(16, 14)
> +# define PRIMARY_ROTATION(x) ((x) << 11)
> +# define PRIMARY_ROTATION_MASK GENMASK(13, 11)
> +# define PRIMARY_CLEAR_EN(x) ((x) << 8)
> +# define PRIMARY_CLEAR_EN_MASK GENMASK(8, 8)
> +
> +#define DC_FRAMEBUFFER_CONFIG_EX 0x1CC0
> +# define PRIMARY_CHANNEL(x) ((x) << 19)
> +# define PRIMARY_CHANNEL_MASK GENMASK(19, 19)
> +# define PRIMARY_ZPOS(x) ((x) << 16)
> +# define PRIMARY_ZPOS_MASK GENMASK(18, 16)
> +# define PRIMARY_EN(x) ((x) << 13)
> +# define PRIMARY_EN_MASK GENMASK(13, 13)
> +# define PRIMARY_SHADOW_EN BIT(12)
> +# define PRIMARY_YUVCLAMP_EN BIT(8)
> +# define PRIMARY_RGB2RGB_EN BIT(6)
> +# define PRIMARY_SYNC1_EN BIT(4)
> +# define PRIMARY_SYNC0_EN BIT(3)
> +# define PRIMARY_DECODER_EN(x) ((x) << 1)
> +# define PRIMARY_DECODER_EN_EN_MASK GENMASK(1, 1)
> +
> +#define DC_FRAMEBUFFER_SCALE_CONFIG 0x1520
> +#define DC_FRAMEBUFFER_TOP_LEFT 0x24D8
> +#define X_POS(x) (x)
> +#define Y_POS(x) ((x) << 15)
> +
> +#define DC_FRAMEBUFFER_BOTTOM_RIGHT 0x24E0
> +#define DC_FRAMEBUFFER_ADDRESS 0x1400
> +#define DC_FRAMEBUFFER_U_ADDRESS 0x1530
> +#define DC_FRAMEBUFFER_V_ADDRESS 0x1538
> +#define DC_FRAMEBUFFER_STRIDE 0x1408
> +#define DC_FRAMEBUFFER_U_STRIDE 0x1800
> +#define DC_FRAMEBUFFER_V_STRIDE 0x1808
> +#define DC_FRAMEBUFFER_SIZE 0x1810
> +#define FB_SIZE(w, h) ((w) | ((h) << 15))
> +
> +#define DC_FRAMEBUFFER_SCALE_FACTOR_X 0x1828
> +#define DC_FRAMEBUFFER_SCALE_FACTOR_Y 0x1830
> +#define DC_FRAMEBUFFER_H_FILTER_COEF_INDEX 0x1838
> +#define DC_FRAMEBUFFER_H_FILTER_COEF_DATA 0x1A00
> +#define DC_FRAMEBUFFER_V_FILTER_COEF_INDEX 0x1A08
> +#define DC_FRAMEBUFFER_V_FILTER_COEF_DATA 0x1A10
> +#define DC_FRAMEBUFFER_INIT_OFFSET 0x1A20
> +#define DC_FRAMEBUFFER_COLOR_KEY 0x1508
> +#define DC_FRAMEBUFFER_COLOR_KEY_HIGH 0x1510
> +#define DC_FRAMEBUFFER_CLEAR_VALUE 0x1A18
> +#define DC_FRAMEBUFFER_COLOR_TABLE_INDEX 0x1818
> +#define DC_FRAMEBUFFER_COLOR_TABLE_DATA 0x1820
> +#define DC_FRAMEBUFFER_BG_COLOR 0x1528
> +#define DC_FRAMEBUFFER_ROI_ORIGIN 0x1CB0
> +#define DC_FRAMEBUFFER_ROI_SIZE 0x1CB8
> +#define DC_FRAMEBUFFER_WATER_MARK 0x1CE8
> +#define DC_FRAMEBUFFER_DEGAMMA_INDEX 0x1D88
> +#define DC_FRAMEBUFFER_DEGAMMA_DATA 0x1D90
> +#define DC_FRAMEBUFFER_DEGAMMA_EX_DATA 0x1D98
> +#define DC_FRAMEBUFFER_YUVTORGB_COEF0 0x1DA0
> +#define DC_FRAMEBUFFER_YUVTORGB_COEF1 0x1DA8
> +#define DC_FRAMEBUFFER_YUVTORGB_COEF2 0x1DB0
> +#define DC_FRAMEBUFFER_YUVTORGB_COEF3 0x1DB8
> +#define DC_FRAMEBUFFER_YUVTORGB_COEF4 0x1E00
> +#define DC_FRAMEBUFFER_YUVTORGB_COEFD0 0x1E08
> +#define DC_FRAMEBUFFER_YUVTORGB_COEFD1 0x1E10
> +#define DC_FRAMEBUFFER_YUVTORGB_COEFD2 0x1E18
> +#define DC_FRAMEBUFFER_Y_CLAMP_BOUND 0x1E88
> +#define DC_FRAMEBUFFER_UV_CLAMP_BOUND 0x1E90
> +#define DC_FRAMEBUFFER_RGBTORGB_COEF0 0x1E20
> +#define DC_FRAMEBUFFER_RGBTORGB_COEF1 0x1E28
> +#define DC_FRAMEBUFFER_RGBTORGB_COEF2 0x1E30
> +#define DC_FRAMEBUFFER_RGBTORGB_COEF3 0x1E38
> +#define DC_FRAMEBUFFER_RGBTORGB_COEF4 0x1E40
> +#define DC_FRAMEBUFFER_BLEND_CONFIG 0x2510
> +# define BLEND_PREMULTI 0x3450
> +# define BLEND_COVERAGE 0x3950
> +# define BLEND_PIXEL_NONE 0x3548
> +
> +#define DC_FRAMEBUFFER_SRC_GLOBAL_COLOR 0x2500
> +# define PRIMARY_ALPHA_LEN(x) ((x) << 24)
> +
> +#define DC_FRAMEBUFFER_DST_GLOBAL_COLOR 0x2508
> +
> +#define DC_OVERLAY_CONFIG 0x1540
> +# define OVERLAY_SHADOW_EN BIT(31)
> +# define OVERLAY_CLAMP_EN BIT(30)
> +# define OVERLAY_RGB2RGB_EN BIT(29)
> +# define OVERLAY_DEC_EN(x) ((x) << 27)
> +# define OVERLAY_DEC_EN_MASK GENMASK(27, 27)
> +# define OVERLAY_CLEAR_EN(x) ((x) << 25)
> +# define OVERLAY_CLEAR_EN_MASK GENMASK(25, 25)
> +# define OVERLAY_FB_EN(x) ((x) << 24)
> +# define OVERLAY_FB_EN_MASK GENMASK(24, 24)
> +# define OVERLAY_FORMAT(x) ((x) << 16)
> +# define OVERLAY_FORMAT_MASK GENMASK(21, 16)
> +# define OVERLAY_UV_SWIZ(x) ((x) << 15)
> +# define OVERLAY_UV_SWIZ_MASK GENMASK(15, 15)
> +# define OVERLAY_SWIZ(x) ((x) << 13)
> +# define OVERLAY_SWIZ_MASK GENMASK(14, 13)
> +# define OVERLAY_TILE(x) ((x) << 8)
> +# define OVERLAY_TILE_MASK GENMASK(12, 8)
> +# define OVERLAY_YUV_COLOR(x) ((x) << 5)
> +# define OVERLAY_YUV_COLOR_MASK GENMASK(7, 5)
> +# define OVERLAY_ROTATION(x) ((x) << 2)
> +# define OVERLAY_ROTATION_MASK GENMASK(4, 2)
> +
> +#define DC_OVERLAY_CONFIG_EX 0x2540
> +# define OVERLAY_LAYER_SEL(x) ((x) << 0)
> +# define OVERLAY_LAYER_SEL_MASK GENMASK(2, 0)
> +# define OVERLAY_PANEL_SEL(x) ((x) << 3)
> +# define OVERLAY_PANEL_SEL_MASK GENMASK(3, 3)
> +
> +#define DC_OVERLAY_SCALE_CONFIG 0x1C00
> +# define OVERLAY_SCALE_EN BIT(8)
> +
> +#define DC_OVERLAY_BLEND_CONFIG 0x1580
> +#define DC_OVERLAY_TOP_LEFT 0x1640
> +#define DC_OVERLAY_BOTTOM_RIGHT 0x1680
> +#define DC_OVERLAY_ADDRESS 0x15C0
> +#define DC_OVERLAY_U_ADDRESS 0x1840
> +#define DC_OVERLAY_V_ADDRESS 0x1880
> +#define DC_OVERLAY_STRIDE 0x1600
> +#define DC_OVERLAY_U_STRIDE 0x18C0
> +#define DC_OVERLAY_V_STRIDE 0x1900
> +#define DC_OVERLAY_SIZE 0x17C0
> +#define DC_OVERLAY_SCALE_FACTOR_X 0x1A40
> +#define DC_OVERLAY_SCALE_FACTOR_Y 0x1A80
> +#define DC_OVERLAY_H_FILTER_COEF_INDEX 0x1AC0
> +#define DC_OVERLAY_H_FILTER_COEF_DATA 0x1B00
> +#define DC_OVERLAY_V_FILTER_COEF_INDEX 0x1B40
> +#define DC_OVERLAY_V_FILTER_COEF_DATA 0x1B80
> +#define DC_OVERLAY_INIT_OFFSET 0x1BC0
> +#define DC_OVERLAY_COLOR_KEY 0x1740
> +#define DC_OVERLAY_COLOR_KEY_HIGH 0x1780
> +#define DC_OVERLAY_CLEAR_VALUE 0x1940
> +#define DC_OVERLAY_COLOR_TABLE_INDEX 0x1980
> +#define DC_OVERLAY_COLOR_TABLE_DATA 0x19C0
> +#define DC_OVERLAY_SRC_GLOBAL_COLOR 0x16C0
> +# define OVERLAY_ALPHA_LEN(x) ((x) << 24)
> +
> +#define DC_OVERLAY_DST_GLOBAL_COLOR 0x1700
> +#define DC_OVERLAY_ROI_ORIGIN 0x1D00
> +#define DC_OVERLAY_ROI_SIZE 0x1D40
> +#define DC_OVERLAY_WATER_MARK 0x1DC0
> +#define DC_OVERLAY_DEGAMMA_INDEX 0x2200
> +#define DC_OVERLAY_DEGAMMA_DATA 0x2240
> +#define DC_OVERLAY_DEGAMMA_EX_DATA 0x2280
> +#define DC_OVERLAY_YUVTORGB_COEF0 0x1EC0
> +#define DC_OVERLAY_YUVTORGB_COEF1 0x1F00
> +#define DC_OVERLAY_YUVTORGB_COEF2 0x1F40
> +#define DC_OVERLAY_YUVTORGB_COEF3 0x1F80
> +#define DC_OVERLAY_YUVTORGB_COEF4 0x1FC0
> +#define DC_OVERLAY_YUVTORGB_COEFD0 0x2000
> +#define DC_OVERLAY_YUVTORGB_COEFD1 0x2040
> +#define DC_OVERLAY_YUVTORGB_COEFD2 0x2080
> +#define DC_OVERLAY_Y_CLAMP_BOUND 0x22C0
> +#define DC_OVERLAY_UV_CLAMP_BOUND 0x2300
> +#define DC_OVERLAY_RGBTORGB_COEF0 0x20C0
> +#define DC_OVERLAY_RGBTORGB_COEF1 0x2100
> +#define DC_OVERLAY_RGBTORGB_COEF2 0x2140
> +#define DC_OVERLAY_RGBTORGB_COEF3 0x2180
> +#define DC_OVERLAY_RGBTORGB_COEF4 0x21C0
> +
> +#define DC_CURSOR_CONFIG 0x1468
> +# define CURSOR_HOT_X(x) ((x) << 16)
> +# define CURSOR_HOT_X_MASK GENMASK(23, 16)
> +# define CURSOR_HOT_y(x) ((x) << 8)
> +# define CURSOR_HOT_y_MASK GENMASK(15, 8)
> +# define CURSOR_SIZE(x) ((x) << 5)
> +# define CURSOR_SIZE_MASK GENMASK(7, 5)
> +# define CURSOR_VALID(x) ((x) << 3)
> +# define CURSOR_VALID_MASK GENMASK(3, 3)
> +# define CURSOR_TRIG_FETCH(x) ((x) << 2)
> +# define CURSOR_TRIG_FETCH_MASK GENMASK(2, 2)
> +# define CURSOR_FORMAT(x) ((x) << 0)
> +# define CURSOR_FORMAT_MASK GENMASK(1, 0)
> +# define CURSOR_FORMAT_DISABLE 0
> +# define CURSOR_FORMAT_MARK 1
> +# define CURSOR_FORMAT_A8R8G8B8 2
> +
> +#define DC_CURSOR_ADDRESS 0x146C
> +#define DC_CURSOR_LOCATION 0x1470
> +# define X_LCOTION(x) (x)
> +# define Y_LCOTION(x) ((x) << 16)
> +
> +#define DC_CURSOR_BACKGROUND 0x1474
> +#define DC_CURSOR_FOREGROUND 0x1478
> +#define DC_CURSOR_CLK_GATING 0x1484
> +#define DC_CURSOR_CONFIG_EX 0x24E8
> +#define DC_CURSOR_OFFSET 0x1080
> +
> +#define DC_DISPLAY_DITHER_CONFIG 0x1410
> +#define DC_DISPLAY_PANEL_CONFIG 0x1418
> +# define PANEL_RGB2YUV_EN BIT(16)
> +# define PANEL_GAMMA_EN BIT(13)
> +# define PANEL_OUTPUT_EN BIT(12)
> +
> +#define DC_DISPLAY_PANEL_CONFIG_EX 0x2518
> +# define PANEL_SHADOW_EN BIT(0)
> +
> +#define DC_DISPLAY_DITHER_TABLE_LOW 0x1420
> +#define DC_DISPLAY_DITHER_TABLE_HIGH 0x1428
> +#define DC_DISPLAY_H 0x1430
> +# define H_ACTIVE_LEN(x) (x)
> +# define H_TOTAL_LEN(x) ((x) << 16)
> +
> +#define DC_DISPLAY_H_SYNC 0x1438
> +# define H_SYNC_START_LEN(x) (x)
> +# define H_SYNC_END_LEN(x) ((x) << 15)
> +# define H_PLUS_LEN(x) ((x) << 30)
> +# define H_POLARITY_LEN(x) ((x) << 31)
> +
> +#define DC_DISPLAY_V 0x1440
> +# define V_ACTIVE_LEN(x) (x)
> +# define V_TOTAL_LEN(x) ((x) << 16)
> +
> +#define DC_DISPLAY_V_SYNC 0x1448
> +# define V_SYNC_START_LEN(x) (x)
> +# define V_SYNC_END_LEN(x) ((x) << 15)
> +# define V_PLUS_LEN(x) ((x) << 30)
> +# define V_POLARITY_LEN(x) ((x) << 31)
> +
> +#define DC_DISPLAY_CURRENT_LOCATION 0x1450
> +#define DC_DISPLAY_GAMMA_INDEX 0x1458
> +#define DC_DISPLAY_GAMMA_DATA 0x1460
> +#define DC_DISPLAY_INT 0x147C
> +#define DC_DISPLAY_INT_ENABLE 0x1480
> +#define DC_DISPLAY_DBI_CONFIG 0x1488
> +#define DC_DISPLAY_GENERAL_CONFIG 0x14B0
> +#define DC_DISPLAY_DPI_CONFIG 0x14B8
> +#define DC_DISPLAY_PANEL_START 0x1CCC
> +# define PANEL0_EN BIT(0)
> +# define PANEL1_EN BIT(1)
> +# define TWO_PANEL_EN BIT(2)
> +# define SYNC_EN BIT(3)
> +
> +#define DC_DISPLAY_DEBUG_COUNTER_SELECT 0x14D0
> +#define DC_DISPLAY_DEBUG_COUNTER_VALUE 0x14D8
> +#define DC_DISPLAY_DP_CONFIG 0x1CD0
> +# define DP_SELECT BIT(3)
> +
> +#define DC_DISPLAY_GAMMA_EX_INDEX 0x1CF0
> +#define DC_DISPLAY_GAMMA_EX_DATA 0x1CF8
> +#define DC_DISPLAY_GAMMA_EX_ONE_DATA 0x1D80
> +#define DC_DISPLAY_RGBTOYUV_COEF0 0x1E48
> +#define DC_DISPLAY_RGBTOYUV_COEF1 0x1E50
> +#define DC_DISPLAY_RGBTOYUV_COEF2 0x1E58
> +#define DC_DISPLAY_RGBTOYUV_COEF3 0x1E60
> +#define DC_DISPLAY_RGBTOYUV_COEF4 0x1E68
> +#define DC_DISPLAY_RGBTOYUV_COEFD0 0x1E70
> +#define DC_DISPLAY_RGBTOYUV_COEFD1 0x1E78
> +#define DC_DISPLAY_RGBTOYUV_COEFD2 0x1E80
> +
> +#define DC_CLK_GATTING 0x1A28
> +#define DC_QOS_CONFIG 0x1A38
> +
> +#define DC_TRANSPARENCY_OPAQUE 0x00
> +#define DC_TRANSPARENCY_KEY 0x02
> +#define DC_DISPLAY_DITHERTABLE_LOW 0x7B48F3C0
> +#define DC_DISPLAY_DITHERTABLE_HIGH 0x596AD1E2
> +
> +#define DC_TILE_MODE4X4 0x15
> +
> +#define GAMMA_SIZE 256
> +#define GAMMA_EX_SIZE 300
> +#define DEGAMMA_SIZE 260
> +
> +#define RGB_TO_RGB_TABLE_SIZE 9
> +#define YUV_TO_RGB_TABLE_SIZE 16
> +#define RGB_TO_YUV_TABLE_SIZE 12
> +
> +#define DC_LAYER_NUM 6
> +#define DC_DISPLAY_NUM 2
> +#define DC_CURSOR_NUM 2
> +
> +enum dc_hw_plane_id {
> + PRIMARY_PLANE_0,
> + OVERLAY_PLANE_0,
> + OVERLAY_PLANE_1,
> + PRIMARY_PLANE_1,
> + OVERLAY_PLANE_2,
> + OVERLAY_PLANE_3,
> + CURSOR_PLANE_0,
> + CURSOR_PLANE_1,
> + PLANE_NUM
> +};
> +
> +enum dc_hw_color_format {
> + FORMAT_X4R4G4B4,
> + FORMAT_A4R4G4B4,
> + FORMAT_X1R5G5B5,
> + FORMAT_A1R5G5B5,
> + FORMAT_R5G6B5,
> + FORMAT_X8R8G8B8,
> + FORMAT_A8R8G8B8,
> + FORMAT_YUY2,
> + FORMAT_UYVY,
> + FORMAT_INDEX8,
> + FORMAT_MONOCHROME,
> + FORMAT_YV12 = 0xf,
> + FORMAT_A8,
> + FORMAT_NV12,
> + FORMAT_NV16,
> + FORMAT_RG16,
> + FORMAT_R8,
> + FORMAT_NV12_10BIT,
> + FORMAT_A2R10G10B10,
> + FORMAT_NV16_10BIT,
> + FORMAT_INDEX1,
> + FORMAT_INDEX2,
> + FORMAT_INDEX4,
> + FORMAT_P010,
> + FORMAT_YUV444,
> + FORMAT_YUV444_10BIT,
> +};
> +
> +enum dc_hw_yuv_color_space {
> + COLOR_SPACE_601 = 0,
> + COLOR_SPACE_709 = 1,
> + COLOR_SPACE_2020 = 3,
> +};
> +
> +enum dc_hw_rotation {
> + ROT_0 = 0,
> + ROT_90 = 4,
> + ROT_180 = 5,
> + ROT_270 = 6,
> + FLIP_X = 1,
> + FLIP_Y = 2,
> + FLIP_XY = 3,
> +};
> +
> +enum dc_hw_swizzle {
> + SWIZZLE_ARGB = 0,
> + SWIZZLE_RGBA,
> + SWIZZLE_ABGR,
> + SWIZZLE_BGRA,
> +};
> +
> +enum dc_hw_out {
> + OUT_DPI,
> + OUT_DP,
> +};
> +
> +enum dc_hw_cursor_size {
> + CURSOR_SIZE_32X32 = 0,
> + CURSOR_SIZE_64X64,
> +};
> +
> +struct dc_hw_plane_reg {
> + u32 y_address;
> + u32 u_address;
> + u32 v_address;
> + u32 y_stride;
> + u32 u_stride;
> + u32 v_stride;
> + u32 size;
> + u32 top_left;
> + u32 bottom_right;
> + u32 scale_factor_x;
> + u32 scale_factor_y;
> + u32 h_filter_coef_index;
> + u32 h_filter_coef_data;
> + u32 v_filter_coef_index;
> + u32 v_filter_coef_data;
> + u32 init_offset;
> + u32 color_key;
> + u32 color_key_high;
> + u32 clear_value;
> + u32 color_table_index;
> + u32 color_table_data;
> + u32 scale_config;
> + u32 water_mark;
> + u32 degamma_index;
> + u32 degamma_data;
> + u32 degamma_ex_data;
> + u32 src_global_color;
> + u32 dst_global_color;
> + u32 blend_config;
> + u32 roi_origin;
> + u32 roi_size;
> + u32 yuv_to_rgb_coef0;
> + u32 yuv_to_rgb_coef1;
> + u32 yuv_to_rgb_coef2;
> + u32 yuv_to_rgb_coef3;
> + u32 yuv_to_rgb_coef4;
> + u32 yuv_to_rgb_coefd0;
> + u32 yuv_to_rgb_coefd1;
> + u32 yuv_to_rgb_coefd2;
> + u32 y_clamp_bound;
> + u32 uv_clamp_bound;
> + u32 rgb_to_rgb_coef0;
> + u32 rgb_to_rgb_coef1;
> + u32 rgb_to_rgb_coef2;
> + u32 rgb_to_rgb_coef3;
> + u32 rgb_to_rgb_coef4;
> +};
> +
> +struct dc_hw_gamma {
> + u16 gamma[GAMMA_EX_SIZE][3];
> +};
> +
> +struct dc_hw_read {
Not used, please drop.
> + u32 reg;
> + u32 value;
> +};
> +
> +struct dc_hw {
> + enum dc_hw_out out[DC_DISPLAY_NUM];
> + void *hi_base;
> + void *reg_base;
> + struct dc_hw_plane_reg reg[DC_LAYER_NUM];
> +
> + struct dc_hw_gamma gamma[DC_DISPLAY_NUM];
> + struct vs_dc_info *info;
> +};
> +
> +struct vs_dc_plane {
> + enum dc_hw_plane_id id;
> + u32 offset;
> +};
> +
> +struct vs_dc {
> + struct vs_crtc *crtc[DC_DISPLAY_NUM];
Not defined here. Please drop and add when it is actually defined.
> + struct dc_hw hw;
> +
> + struct vs_dc_plane planes[PLANE_NUM];
> +};
> +
> +int dc_hw_init(struct vs_dc *dc);
> +void dc_hw_disable_plane(struct vs_dc *dc, u8 id);
> +void dc_hw_update_cursor(struct dc_hw *hw, u8 id, dma_addr_t dma_addr,
> + u32 crtc_w, u32 crtc_x, u32 crtc_y,
> + s32 hotspot_x, int32_t hotspot_y);
> +void dc_hw_disable_cursor(struct dc_hw *hw, u8 id);
> +void dc_hw_update_gamma(struct dc_hw *hw, u8 id, u16 index,
> + u16 r, u16 g, u16 b);
> +void dc_hw_enable_gamma(struct dc_hw *hw, u8 id, bool enable);
> +void dc_hw_enable(struct dc_hw *hw, int id, struct drm_display_mode *mode,
> + u8 encoder_type, u32 output_fmt);
> +void dc_hw_disable(struct dc_hw *hw, int id);
> +void dc_hw_enable_interrupt(struct dc_hw *hw);
> +void dc_hw_disable_interrupt(struct dc_hw *hw);
> +u32 dc_hw_get_interrupt(struct dc_hw *hw);
> +void dc_hw_enable_shadow_register(struct vs_dc *dc, bool enable);
> +void dc_hw_set_out(struct dc_hw *hw, enum dc_hw_out out, u8 id);
> +void dc_hw_commit(struct dc_hw *hw);
> +void plane_hw_update_format_colorspace(struct vs_dc *dc, u32 format,
> + enum drm_color_encoding encoding, u8 id, bool is_yuv);
> +void plane_hw_update_address(struct vs_dc *dc, u8 id, u32 format, dma_addr_t *dma_addr,
> + struct drm_framebuffer *drm_fb, struct drm_rect *src);
> +void plane_hw_update_format(struct vs_dc *dc, u32 format, enum drm_color_encoding encoding,
> + unsigned int rotation, bool visible, unsigned int zpos,
> + u8 id, u8 display_id);
> +void plane_hw_update_scale(struct vs_dc *dc, struct drm_rect *src, struct drm_rect *dst,
> + u8 id, u8 display_id, unsigned int rotation);
> +void plane_hw_update_blend(struct vs_dc *dc, u16 alpha, u16 pixel_blend_mode,
> + u8 id, u8 display_id);
Could you please settle on a single prefix for all your function names?
Ideally it should be close to the driver name. It's hard to understand
that the function comes from the verisilicon driver if its name starts
from dc_ or especially with plane_.
I'd strongly suggest to stop defining anything outside of the selected
vs_ namespace.
> +
> +#endif /* __VS_DC_HW_H__ */
> diff --git a/drivers/gpu/drm/verisilicon/vs_type.h b/drivers/gpu/drm/verisilicon/vs_type.h
> new file mode 100644
> index 000000000000..30ccc2eda48b
> --- /dev/null
> +++ b/drivers/gpu/drm/verisilicon/vs_type.h
> @@ -0,0 +1,84 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd.
> + */
> +
> +#ifndef __VS_TYPE_H__
> +#define __VS_TYPE_H__
> +
> +#include <drm/drm_plane.h>
These types are largely unused within this patch. Please drop all the
unused parts and add them later, when required.
> +
> +struct vs_plane_primary_info {
> + u8 id;
> + unsigned int num_formats;
> + const u32 *formats;
> + u8 num_modifiers;
> + const u64 *modifiers;
> + unsigned int min_width;
> + unsigned int min_height;
> + unsigned int max_width;
> + unsigned int max_height;
> + unsigned int rotation;
> + unsigned int color_encoding;
> +
> + int min_scale; /* 16.16 fixed point */
> + int max_scale; /* 16.16 fixed point */
> +
> + u8 zpos;
> +
> +};
> +
> +struct vs_plane_overlay_info {
> + u8 id;
> + unsigned int num_formats;
> + const u32 *formats;
> + u8 num_modifiers;
> + const u64 *modifiers;
> + unsigned int min_width;
> + unsigned int min_height;
> + unsigned int max_width;
> + unsigned int max_height;
> + unsigned int rotation;
> + unsigned int color_encoding;
> +
> + int min_scale; /* 16.16 fixed point */
> + int max_scale; /* 16.16 fixed point */
> +
> + u8 zpos;
> +
> +};
> +
> +struct vs_plane_cursor_info {
> + u8 id;
> + unsigned int num_formats;
> + const u32 *formats;
> + unsigned int min_width;
> + unsigned int min_height;
> + unsigned int max_width;
> + unsigned int max_height;
> + u8 zpos;
> +
> +};
> +
> +struct vs_dc_info {
> + const char *name;
> +
> + u8 panel_num;
> +
> + /* planes */
> + u8 layer_num;
> + u8 primary_num;
> + u8 overlay_num;
> + u8 cursor_num;
> + const struct vs_plane_primary_info *primary;
> + const struct vs_plane_overlay_info *overlay;
> + const struct vs_plane_cursor_info *cursor;
> +
> + /* 0 means no gamma LUT */
> + u16 gamma_size;
> + u8 gamma_bits;
> +
> + u16 pitch_alignment;
> +};
> +
> +#endif /* __VS_TYPE_H__ */
> --
> 2.27.0
>
--
With best wishes
Dmitry
Hi keith,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master next-20240521]
[cannot apply to robh/for-next rockchip/for-next v6.9]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/keith/dt-bindings-display-Add-YAML-schema-for-JH7110-display-pipeline/20240521-110316
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20240521105817.3301-5-keith.zhao%40starfivetech.com
patch subject: [PATCH v4 04/10] drm/vs: Add hardware funcs for vs.
config: arc-kismet-CONFIG_DMA_CMA-CONFIG_DRM_VERISILICON_DC8200-0-0 (https://download.01.org/0day-ci/archive/20240522/[email protected]/config)
reproduce: (https://download.01.org/0day-ci/archive/20240522/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
kismet warnings: (new ones prefixed by >>)
>> kismet: WARNING: unmet direct dependencies detected for DMA_CMA when selected by DRM_VERISILICON_DC8200
WARNING: unmet direct dependencies detected for DMA_CMA
Depends on [n]: HAVE_DMA_CONTIGUOUS [=n] && CMA [=y]
Selected by [y]:
- DRM_VERISILICON_DC8200 [=y] && HAS_IOMEM [=y] && DRM [=y]
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi keith,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master next-20240521]
[cannot apply to robh/for-next rockchip/for-next v6.9]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/keith/dt-bindings-display-Add-YAML-schema-for-JH7110-display-pipeline/20240521-110316
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20240521105817.3301-5-keith.zhao%40starfivetech.com
patch subject: [PATCH v4 04/10] drm/vs: Add hardware funcs for vs.
config: arc-randconfig-r123-20240522 (https://download.01.org/0day-ci/archive/20240522/[email protected]/config)
compiler: arc-elf-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240522/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
drivers/gpu/drm/verisilicon/vs_dc_hw.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/stackdepot.h, ...):
include/linux/page-flags.h:241:46: sparse: sparse: self-comparison always evaluates to false
include/linux/page-flags.h:241:46: sparse: sparse: self-comparison always evaluates to false
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
drivers/gpu/drm/verisilicon/vs_dc_hw.c:261:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:261:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:261:9: sparse: got void *
drivers/gpu/drm/verisilicon/vs_dc_hw.c:261:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:261:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:261:9: sparse: got void *
drivers/gpu/drm/verisilicon/vs_dc_hw.c:256:16: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:256:16: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:256:16: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void const volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: expected void const volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:271:21: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
>> drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void volatile [noderef] __iomem *addr @@ got void * @@
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: expected void volatile [noderef] __iomem *addr
drivers/gpu/drm/verisilicon/vs_dc_hw.c:266:9: sparse: got void *
vim +266 drivers/gpu/drm/verisilicon/vs_dc_hw.c
263
264 static inline void dc_write(struct dc_hw *hw, u32 reg, u32 value)
265 {
> 266 writel(value, hw->reg_base + reg - DC_REG_BASE);
267 }
268
269 static inline u32 dc_read(struct dc_hw *hw, u32 reg)
270 {
> 271 u32 value = readl(hw->reg_base + reg - DC_REG_BASE);
272
273 return value;
274 }
275
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi keith,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master next-20240521]
[cannot apply to robh/for-next rockchip/for-next v6.9]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/keith/dt-bindings-display-Add-YAML-schema-for-JH7110-display-pipeline/20240521-110316
base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next
patch link: https://lore.kernel.org/r/20240521105817.3301-5-keith.zhao%40starfivetech.com
patch subject: [PATCH v4 04/10] drm/vs: Add hardware funcs for vs.
config: arm-kismet-CONFIG_CMA-CONFIG_DRM_VERISILICON_DC8200-0-0 (https://download.01.org/0day-ci/archive/20240522/[email protected]/config)
reproduce: (https://download.01.org/0day-ci/archive/20240522/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
kismet warnings: (new ones prefixed by >>)
>> kismet: WARNING: unmet direct dependencies detected for CMA when selected by DRM_VERISILICON_DC8200
WARNING: unmet direct dependencies detected for CMA
Depends on [n]: MMU [=n]
Selected by [y]:
- DRM_VERISILICON_DC8200 [=y] && HAS_IOMEM [=y] && DRM [=y]
WARNING: unmet direct dependencies detected for DMA_CMA
Depends on [n]: HAVE_DMA_CONTIGUOUS [=n] && CMA [=y]
Selected by [y]:
- DRM_VERISILICON_DC8200 [=y] && HAS_IOMEM [=y] && DRM [=y]
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi Alex, Laurent:
I want to make as few changes as possible on the current basis, and add bridge_fun,
> -----Original Message-----
> From: Laurent Pinchart <[email protected]>
> Sent: 2024年5月21日 23:42
> To: Alex Bee <[email protected]>
> Cc: Keith Zhao <[email protected]>; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected]; Xingyu Wu
> <[email protected]>; [email protected]; Jack Zhu
> <[email protected]>; Shengyang Chen
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH v4 02/10] drm/bridge: add common api for inno hdmi
>
> On Tue, May 21, 2024 at 05:36:43PM +0200, Alex Bee wrote:
> > Hi Keith,
> >
> > thanks a lot for working on this. See some general remarks below
> >
> > Am 21.05.24 um 12:58 schrieb keith:
> > > Add INNO common api so that it can be used by vendor drivers which
> > > implement vendor specific extensions to Innosilicon HDMI.
> > >
> > > Signed-off-by: keith <[email protected]>
> > > ---
> > > MAINTAINERS | 2 +
> > > drivers/gpu/drm/bridge/Kconfig | 2 +
> > > drivers/gpu/drm/bridge/Makefile | 1 +
> > > drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
> > > drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
> > > .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587
> ++++++++++++++++++
> > > .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 +++
> > > include/drm/bridge/inno_hdmi.h | 69 ++
> > > 8 files changed, 766 insertions(+)
> > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
> > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
> > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
> > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
> > > create mode 100644 include/drm/bridge/inno_hdmi.h
> > >
> > ....
> >
> > > + drm_encoder_helper_add(encoder, pdata->helper_private);
> > > +
> > > + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
> > > +
> > > + drm_connector_helper_add(&hdmi->connector,
> > > + &inno_hdmi_connector_helper_funcs);
> > > +
> > > + drmm_connector_init(drm, &hdmi->connector,
> > > + &inno_hdmi_connector_funcs,
> > > + DRM_MODE_CONNECTOR_HDMIA,
> > > + hdmi->ddc);
> > > +
> >
> > I really don't want to anticipate bridge maintainer's feedback, but
> > new bridge drivers must not contain connector creation. That must
> > happen somewhere else.
>
> You're absolutely right :-) Connector creation should be handled by the
> drm_bridge_connector helper. The HDMI bridge driver should focus on the
> HDMI bridge itself.
static int inno_bridge_attach(struct drm_bridge *bridge,
enum drm_bridge_attach_flags flags)
{
struct inno_hdmi *hdmi = bridge_to_inno(bridge);
if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
DRM_ERROR("Fix bridge driver to make connector optional!");
return -EINVAL;
}
hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
drm_connector_helper_add(&hdmi->connector,
&inno_hdmi_connector_helper_funcs);
drmm_connector_init(drm, &hdmi->connector,
&inno_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA,
hdmi->ddc);
drm_connector_attach_encoder(&hdmi->connector, encoder);
}
static const struct drm_bridge_funcs inno_bridge_attach = {
.attach = inno_bridge_attach,
};
Connector creation is handled by the drm_bridge_funcs ->attach.
Is it ok?
Regards
Keith
>
> > Also I'm neither seeing any drm_brige struct nor drm_bridge_funcs,
> > which are both essential for a bridge driver. I don't think moving a
> > part of a driver to .../drm/bridge/ makes it a bridge driver.
> >
> > > + drm_connector_attach_encoder(&hdmi->connector, encoder);
> > > +
> > > + return 0;
> > > +}
> > > +
> > ....
> >
>
> --
> Regards,
>
> Laurent Pinchart
Hi,
On Tue, May 21, 2024 at 06:58:10PM GMT, keith wrote:
> Add the ROCKCHIP inno hdmi driver that uses the Inno DesignWare
> HDMI TX bridge and remove the old separate one.
>
> Signed-off-by: keith <[email protected]>
> ---
> drivers/gpu/drm/rockchip/Kconfig | 1 +
> drivers/gpu/drm/rockchip/Makefile | 2 +-
> drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c | 517 ++++++++
> .../{inno_hdmi.h => inno_hdmi-rockchip.h} | 45 -
> drivers/gpu/drm/rockchip/inno_hdmi.c | 1073 -----------------
> 5 files changed, 519 insertions(+), 1119 deletions(-)
> create mode 100644 drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
> rename drivers/gpu/drm/rockchip/{inno_hdmi.h => inno_hdmi-rockchip.h} (85%)
> delete mode 100644 drivers/gpu/drm/rockchip/inno_hdmi.c
>
> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
> index 1bf3e2829cd0..cc6cfd5a30d6 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -74,6 +74,7 @@ config ROCKCHIP_DW_MIPI_DSI
>
> config ROCKCHIP_INNO_HDMI
> bool "Rockchip specific extensions for Innosilicon HDMI"
> + select DRM_INNO_HDMI
> help
> This selects support for Rockchip SoC specific extensions
> for the Innosilicon HDMI driver. If you want to enable
> diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
> index 3ff7b21c0414..4b2d0cba8db3 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -12,7 +12,7 @@ rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
> rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
> rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
> rockchipdrm-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi-rockchip.o
> -rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
> +rockchipdrm-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi-rockchip.o
> rockchipdrm-$(CONFIG_ROCKCHIP_LVDS) += rockchip_lvds.o
> rockchipdrm-$(CONFIG_ROCKCHIP_RGB) += rockchip_rgb.o
> rockchipdrm-$(CONFIG_ROCKCHIP_RK3066_HDMI) += rk3066_hdmi.o
> diff --git a/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
> new file mode 100644
> index 000000000000..69d0e913e13b
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/inno_hdmi-rockchip.c
> @@ -0,0 +1,517 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Zheng Yang <[email protected]>
> + * Yakir Yang <[email protected]>
> + */
> +
> +#include <linux/irq.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/hdmi.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/platform_device.h>
> +
> +#include <drm/bridge/inno_hdmi.h>
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_probe_helper.h>
> +#include <drm/drm_simple_kms_helper.h>
> +
> +#include "rockchip_drm_drv.h"
> +
> +#include "inno_hdmi-rockchip.h"
> +
> +#define INNO_HDMI_MIN_TMDS_CLOCK 25000000U
> +
> +struct rk_inno_hdmi {
> + struct rockchip_encoder encoder;
> + struct inno_hdmi inno_hdmi;
> + struct clk *pclk;
> + struct clk *refclk;
> +};
> +
> +static struct inno_hdmi *rk_encoder_to_inno_hdmi(struct drm_encoder *encoder)
> +{
> + struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
> + struct rk_inno_hdmi *rk_hdmi = container_of(rkencoder, struct rk_inno_hdmi, encoder);
> +
> + return &rk_hdmi->inno_hdmi;
> +}
> +
> +enum {
> + CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
> + CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
> + CSC_RGB_0_255_TO_RGB_16_235_8BIT,
> +};
> +
> +static const char coeff_csc[][24] = {
> + /*
> + * RGB2YUV:601 SD mode:
> + * Cb = -0.291G - 0.148R + 0.439B + 128
> + * Y = 0.504G + 0.257R + 0.098B + 16
> + * Cr = -0.368G + 0.439R - 0.071B + 128
> + */
> + {
> + 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80,
> + 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e,
> + 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80
> + },
> + /*
> + * RGB2YUV:709 HD mode:
> + * Cb = - 0.338G - 0.101R + 0.439B + 128
> + * Y = 0.614G + 0.183R + 0.062B + 16
> + * Cr = - 0.399G + 0.439R - 0.040B + 128
> + */
> + {
> + 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80,
> + 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10,
> + 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80
> + },
> + /*
> + * RGB[0:255]2RGB[16:235]:
> + * R' = R x (235-16)/255 + 16;
> + * G' = G x (235-16)/255 + 16;
> + * B' = B x (235-16)/255 + 16;
> + */
> + {
> + 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10,
> + 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
> + 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10
> + },
> +};
> +
> +static struct inno_hdmi_phy_config rk3036_hdmi_phy_configs[] = {
> + { 74250000, 0x3f, 0xbb },
> + { 165000000, 0x6f, 0xbb },
> + { ~0UL, 0x00, 0x00 }
> +};
> +
> +static struct inno_hdmi_phy_config rk3128_hdmi_phy_configs[] = {
> + { 74250000, 0x3f, 0xaa },
> + { 165000000, 0x5f, 0xaa },
> + { ~0UL, 0x00, 0x00 }
> +};
> +
> +static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
> + unsigned long pixelclk)
> +{
> + const struct inno_hdmi_phy_config *phy_configs = hdmi->plat_data->phy_configs;
> + int i;
> +
> + for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) {
> + if (pixelclk <= phy_configs[i].pixelclock)
> + return i;
> + }
> +
> + DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n",
> + pixelclk);
> +
> + return -EINVAL;
> +}
> +
> +static void inno_hdmi_standby(struct inno_hdmi *hdmi)
> +{
> + inno_hdmi_sys_power(hdmi, false);
> +
> + hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00);
> + hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00);
> + hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00);
> + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
> +};
> +
> +static void inno_hdmi_power_up(struct inno_hdmi *hdmi,
> + unsigned long mpixelclock)
> +{
> + struct inno_hdmi_phy_config *phy_config;
> + int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock);
> +
> + if (ret < 0) {
> + phy_config = hdmi->plat_data->default_phy_config;
> + DRM_DEV_ERROR(hdmi->dev,
> + "Using default phy configuration for TMDS rate %lu",
> + mpixelclock);
> + } else {
> + phy_config = &hdmi->plat_data->phy_configs[ret];
> + }
> +
> + inno_hdmi_sys_power(hdmi, false);
> +
> + hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis);
> + hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control);
> + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15);
> + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14);
> + hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10);
> + hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f);
> + hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00);
> + hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01);
> +
> + inno_hdmi_sys_power(hdmi, true);
> +};
> +
> +static void inno_hdmi_reset(struct inno_hdmi *hdmi)
> +{
> + u32 val;
> + u32 msk;
> +
> + hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL);
> + udelay(100);
> +
> + hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG);
> + udelay(100);
> +
> + msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL;
> + val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH;
> + hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val);
> +
> + inno_hdmi_standby(hdmi);
> +}
> +
> +static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi)
> +{
> + struct drm_connector *connector = &hdmi->connector;
> + struct drm_connector_state *conn_state = connector->state;
> + struct inno_hdmi_connector_state *inno_conn_state =
> + to_inno_hdmi_conn_state(conn_state);
> + int c0_c2_change = 0;
> + int csc_enable = 0;
> + int csc_mode = 0;
> + int auto_csc = 0;
> + int value;
> + int i;
> +
> + /* Input video mode is SDR RGB24bit, data enable signal from external */
> + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL |
> + v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444));
> +
> + /* Input color hardcode to RGB, and output color hardcode to RGB888 */
> + value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) |
> + v_VIDEO_OUTPUT_COLOR(0) |
> + v_VIDEO_INPUT_CSP(0);
> + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value);
> +
> + if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_RGB) {
> + if (inno_conn_state->rgb_limited_range) {
> + csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
> + auto_csc = AUTO_CSC_DISABLE;
> + c0_c2_change = C0_C2_CHANGE_DISABLE;
> + csc_enable = v_CSC_ENABLE;
> +
> + } else {
> + value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1);
> + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
> +
> + hdmi_modb(hdmi, HDMI_VIDEO_CONTRL,
> + m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP,
> + v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) |
> + v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE));
> + return 0;
> + }
> + } else {
> + if (inno_conn_state->colorimetry == HDMI_COLORIMETRY_ITU_601) {
> + if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
> + csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
> + auto_csc = AUTO_CSC_DISABLE;
> + c0_c2_change = C0_C2_CHANGE_DISABLE;
> + csc_enable = v_CSC_ENABLE;
> + }
> + } else {
> + if (inno_conn_state->enc_out_format == HDMI_COLORSPACE_YUV444) {
> + csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
> + auto_csc = AUTO_CSC_DISABLE;
> + c0_c2_change = C0_C2_CHANGE_DISABLE;
> + csc_enable = v_CSC_ENABLE;
> + }
> + }
> + }
> +
> + for (i = 0; i < 24; i++)
> + hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i,
> + coeff_csc[csc_mode][i]);
> +
> + value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1);
> + hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value);
> + hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC |
> + m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) |
> + v_VIDEO_C0_C2_SWAP(c0_c2_change));
> +
> + return 0;
> +}
> +
> +static int inno_hdmi_setup(struct inno_hdmi *hdmi,
> + struct drm_display_mode *mode)
> +{
> + struct drm_display_info *display = &hdmi->connector.display_info;
> + unsigned long mpixelclock = mode->clock * 1000;
> +
> + /* Mute video and audio output */
> + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
> + v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1));
> +
> + /* Set HDMI Mode */
> + hdmi_writeb(hdmi, HDMI_HDCP_CTRL,
> + v_HDMI_DVI(display->is_hdmi));
> +
> + inno_hdmi_config_video_timing(hdmi, mode);
> +
> + inno_hdmi_config_video_csc(hdmi);
> +
> + if (display->is_hdmi)
> + inno_hdmi_config_video_avi(hdmi, mode);
> +
> + /*
> + * When IP controller have configured to an accurate video
> + * timing, then the TMDS clock source would be switched to
> + * DCLK_LCDC, so we need to init the TMDS rate to mode pixel
> + * clock rate, and reconfigure the DDC clock.
> + */
> + inno_hdmi_i2c_init(hdmi, mpixelclock);
> +
> + /* Unmute video and audio output */
> + hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK,
> + v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0));
> +
> + inno_hdmi_power_up(hdmi, mpixelclock);
> +
> + return 0;
> +}
>
It's kind of a general comment, but I don't think that's the right
abstraction. You should create a inno_hdmi bridge that allows to
supplement some of the atomic hooks, but not reimplement them entirely
each time.
You can have a look at how dw-hdmi does it for example. Also, why do you
still need the encoder and connectors?
Maxime
Hi Keith,
On Wed, May 22, 2024 at 05:58:00AM +0000, Keith Zhao wrote:
> Hi Alex, Laurent:
>
> I want to make as few changes as possible on the current basis, and add bridge_fun,
>
> On 2024年5月21日 23:42, Laurent Pinchart wrote:
> > On Tue, May 21, 2024 at 05:36:43PM +0200, Alex Bee wrote:
> > > Hi Keith,
> > >
> > > thanks a lot for working on this. See some general remarks below
> > >
> > > Am 21.05.24 um 12:58 schrieb keith:
> > > > Add INNO common api so that it can be used by vendor drivers which
> > > > implement vendor specific extensions to Innosilicon HDMI.
> > > >
> > > > Signed-off-by: keith <[email protected]>
> > > > ---
> > > > MAINTAINERS | 2 +
> > > > drivers/gpu/drm/bridge/Kconfig | 2 +
> > > > drivers/gpu/drm/bridge/Makefile | 1 +
> > > > drivers/gpu/drm/bridge/innosilicon/Kconfig | 6 +
> > > > drivers/gpu/drm/bridge/innosilicon/Makefile | 2 +
> > > > .../gpu/drm/bridge/innosilicon/inno-hdmi.c | 587 ++++++++++++++++++
> > > > .../gpu/drm/bridge/innosilicon/inno-hdmi.h | 97 +++
> > > > include/drm/bridge/inno_hdmi.h | 69 ++
> > > > 8 files changed, 766 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/Kconfig
> > > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/Makefile
> > > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.c
> > > > create mode 100644 drivers/gpu/drm/bridge/innosilicon/inno-hdmi.h
> > > > create mode 100644 include/drm/bridge/inno_hdmi.h
> > > >
> > > ....
> > >
> > > > + drm_encoder_helper_add(encoder, pdata->helper_private);
> > > > +
> > > > + hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
> > > > +
> > > > + drm_connector_helper_add(&hdmi->connector,
> > > > + &inno_hdmi_connector_helper_funcs);
> > > > +
> > > > + drmm_connector_init(drm, &hdmi->connector,
> > > > + &inno_hdmi_connector_funcs,
> > > > + DRM_MODE_CONNECTOR_HDMIA,
> > > > + hdmi->ddc);
> > > > +
> > >
> > > I really don't want to anticipate bridge maintainer's feedback, but
> > > new bridge drivers must not contain connector creation. That must
> > > happen somewhere else.
> >
> > You're absolutely right :-) Connector creation should be handled by the
> > drm_bridge_connector helper. The HDMI bridge driver should focus on the
> > HDMI bridge itself.
>
> static int inno_bridge_attach(struct drm_bridge *bridge,
> enum drm_bridge_attach_flags flags)
> {
> struct inno_hdmi *hdmi = bridge_to_inno(bridge);
>
> if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
> DRM_ERROR("Fix bridge driver to make connector optional!");
> return -EINVAL;
> }
This kind of code was added to existing bridge drivers when we
transitioned to the new model where bridges don't create the connectors,
because we couldn't fix all the existing bridges in one go. New bridges
must do the opposite. See imx8qxp-pixel-link.c for instance, it has this
code instead in its attach function:
if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
DRM_DEV_ERROR(pl->dev,
"do not support creating a drm_connector\n");
return -EINVAL;
}
(I would personally drop the DRM_DEV_ERROR message)
> hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
>
> drm_connector_helper_add(&hdmi->connector,
> &inno_hdmi_connector_helper_funcs);
>
> drmm_connector_init(drm, &hdmi->connector,
> &inno_hdmi_connector_funcs,
> DRM_MODE_CONNECTOR_HDMIA,
> hdmi->ddc);
>
> drm_connector_attach_encoder(&hdmi->connector, encoder);
> }
>
> static const struct drm_bridge_funcs inno_bridge_attach = {
> .attach = inno_bridge_attach,
> };
>
> Connector creation is handled by the drm_bridge_funcs ->attach.
> Is it ok?
No, the connector should be created by the display controller driver by
calling drm_brige_connector_init(). It should not be created by the
bridge driver. The bridge driver should provide the bridge functions
(drm_bridge_funcs), but not create any connector.
> > > Also I'm neither seeing any drm_brige struct nor drm_bridge_funcs,
> > > which are both essential for a bridge driver. I don't think moving a
> > > part of a driver to .../drm/bridge/ makes it a bridge driver.
> > >
> > > > + drm_connector_attach_encoder(&hdmi->connector, encoder);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > ....
> > >
--
Regards,
Laurent Pinchart