GSC is a graphics system controller, it provides
a chassis controller for graphics discrete cards.
There are two MEI interfaces in GSC: HECI1 and HECI2.
This series includes instantiation of the auxiliary devices for HECI2
and mei-gsc auxiliary device driver that binds to the auxiliary device.
The prinicpal user of this interface is the
Intel Graphics System Controller Firmware Update Library (IGSC FU)
(https://github.com/intel/igsc)
In v2 the platform device was replaced by the auxiliary device.
v3 is the rebase over drm-tip to make public CI running.
In v4 the not needed debug prints and empty line were removed,
'select' were replaced by 'depends on' in MEI Kconfig,
the new include file now listed in the MAINTATINERS file.
V5, rebase and add Greg KH Reviewed-by
V6, rebase and drop redundant assignments found by the kernel test
robot.
V7, add Greg KH Reviewed-by to the individual patches
V8, address Tvrtko comments for i915
V9, rebase and address more Tvrtko comments, use drm error printing
V10, rebase
V11, address Rodrigo comments about code style,
set missed mask in the interrupt config,
add explicit devm_irq_free to error and remove flows
Tomas, please look at the devm_irq_free part.
Alexander Usyskin (2):
mei: gsc: setup char driver alive in spite of firmware handshake
failure
mei: gsc: retrieve the firmware version
Tomas Winkler (3):
drm/i915/gsc: add gsc as a mei auxiliary device
mei: add support for graphics system controller (gsc) devices
mei: gsc: add runtime pm handlers
MAINTAINERS | 1 +
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/gt/intel_gsc.c | 204 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gsc.h | 37 ++++
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
drivers/misc/mei/Kconfig | 14 ++
drivers/misc/mei/Makefile | 3 +
drivers/misc/mei/bus-fixup.c | 25 +++
drivers/misc/mei/gsc-me.c | 259 +++++++++++++++++++++++
drivers/misc/mei/hw-me.c | 29 ++-
drivers/misc/mei/hw-me.h | 2 +
include/linux/mei_aux.h | 19 ++
21 files changed, 633 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
create mode 100644 drivers/misc/mei/gsc-me.c
create mode 100644 include/linux/mei_aux.h
--
2.32.0
From: Tomas Winkler <[email protected]>
GSC is a graphics system controller, based on CSE, it provides
a chassis controller for graphics discrete cards, as well as it
supports media protection on selected devices.
mei_gsc binds to a auxiliary devices exposed by Intel discrete
driver i915.
Signed-off-by: Alexander Usyskin <[email protected]>
Signed-off-by: Tomas Winkler <[email protected]>
---
V4: drop debug prints
replace selects with depends on in Kconfig
V5: Rebase
V6: Rebase
V7: add Greg KH Reviewed-by
V8: Rebase
V9: Rebase
V11: explicitely call devm_free_irq on error path and remove
---
drivers/misc/mei/Kconfig | 14 +++
drivers/misc/mei/Makefile | 3 +
drivers/misc/mei/gsc-me.c | 194 ++++++++++++++++++++++++++++++++++++++
drivers/misc/mei/hw-me.c | 27 +++++-
drivers/misc/mei/hw-me.h | 2 +
5 files changed, 238 insertions(+), 2 deletions(-)
create mode 100644 drivers/misc/mei/gsc-me.c
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index 0e0bcd0da852..d21486d69df2 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -46,6 +46,20 @@ config INTEL_MEI_TXE
Supported SoCs:
Intel Bay Trail
+config INTEL_MEI_GSC
+ tristate "Intel MEI GSC embedded device"
+ depends on INTEL_MEI
+ depends on INTEL_MEI_ME
+ depends on X86 && PCI
+ depends on DRM_I915
+ help
+ Intel auxiliary driver for GSC devices embedded in Intel graphics devices.
+
+ An MEI device here called GSC can be embedded in an
+ Intel graphics devices, to support a range of chassis
+ tasks such as graphics card firmware update and security
+ tasks.
+
source "drivers/misc/mei/hdcp/Kconfig"
source "drivers/misc/mei/pxp/Kconfig"
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index d8e5165917f2..fb740d754900 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) += mei-me.o
mei-me-objs := pci-me.o
mei-me-objs += hw-me.o
+obj-$(CONFIG_INTEL_MEI_GSC) += mei-gsc.o
+mei-gsc-objs := gsc-me.o
+
obj-$(CONFIG_INTEL_MEI_TXE) += mei-txe.o
mei-txe-objs := pci-txe.o
mei-txe-objs += hw-txe.o
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
new file mode 100644
index 000000000000..64b02adf3149
--- /dev/null
+++ b/drivers/misc/mei/gsc-me.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#include <linux/module.h>
+#include <linux/mei_aux.h>
+#include <linux/device.h>
+#include <linux/irqreturn.h>
+#include <linux/jiffies.h>
+#include <linux/ktime.h>
+#include <linux/delay.h>
+#include <linux/pm_runtime.h>
+
+#include "mei_dev.h"
+#include "hw-me.h"
+#include "hw-me-regs.h"
+
+#include "mei-trace.h"
+
+#define MEI_GSC_RPM_TIMEOUT 500
+
+static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
+{
+ struct mei_me_hw *hw = to_me_hw(dev);
+
+ *val = ioread32(hw->mem_addr + where + 0xC00);
+
+ return 0;
+}
+
+static int mei_gsc_probe(struct auxiliary_device *aux_dev,
+ const struct auxiliary_device_id *aux_dev_id)
+{
+ struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+ struct mei_device *dev;
+ struct mei_me_hw *hw;
+ struct device *device;
+ const struct mei_cfg *cfg;
+ int ret;
+
+ cfg = mei_me_get_cfg(aux_dev_id->driver_data);
+ if (!cfg)
+ return -ENODEV;
+
+ device = &aux_dev->dev;
+
+ dev = mei_me_dev_init(device, cfg);
+ if (IS_ERR(dev)) {
+ ret = PTR_ERR(dev);
+ goto err;
+ }
+
+ hw = to_me_hw(dev);
+ hw->mem_addr = devm_ioremap_resource(device, &adev->bar);
+ if (IS_ERR(hw->mem_addr)) {
+ dev_err(device, "mmio not mapped\n");
+ ret = PTR_ERR(hw->mem_addr);
+ goto err;
+ }
+
+ hw->irq = adev->irq;
+ hw->read_fws = mei_gsc_read_hfs;
+
+ dev_set_drvdata(device, dev);
+
+ ret = devm_request_threaded_irq(device, hw->irq,
+ mei_me_irq_quick_handler,
+ mei_me_irq_thread_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
+ if (ret) {
+ dev_err(device, "irq register failed %d\n", ret);
+ goto err;
+ }
+
+ pm_runtime_get_noresume(device);
+ pm_runtime_set_active(device);
+ pm_runtime_enable(device);
+
+ if (mei_start(dev)) {
+ dev_err(device, "init hw failure.\n");
+ ret = -ENODEV;
+ goto irq_err;
+ }
+
+ pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
+ pm_runtime_use_autosuspend(device);
+
+ ret = mei_register(dev, device);
+ if (ret)
+ goto register_err;
+
+ pm_runtime_put_noidle(device);
+ return 0;
+
+register_err:
+ mei_stop(dev);
+irq_err:
+ devm_free_irq(device, hw->irq, dev);
+
+err:
+ dev_err(device, "probe failed: %d\n", ret);
+ dev_set_drvdata(device, NULL);
+ return ret;
+}
+
+static void mei_gsc_remove(struct auxiliary_device *aux_dev)
+{
+ struct mei_device *dev;
+ struct mei_me_hw *hw;
+
+ dev = dev_get_drvdata(&aux_dev->dev);
+ if (!dev)
+ return;
+
+ hw = to_me_hw(dev);
+
+ mei_stop(dev);
+
+ mei_deregister(dev);
+
+ pm_runtime_disable(&aux_dev->dev);
+
+ mei_disable_interrupts(dev);
+ devm_free_irq(&aux_dev->dev, hw->irq, dev);
+}
+
+static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
+{
+ struct mei_device *dev = dev_get_drvdata(device);
+
+ if (!dev)
+ return -ENODEV;
+
+ mei_stop(dev);
+
+ mei_disable_interrupts(dev);
+
+ return 0;
+}
+
+static int __maybe_unused mei_gsc_pm_resume(struct device *device)
+{
+ struct mei_device *dev = dev_get_drvdata(device);
+ int err;
+
+ if (!dev)
+ return -ENODEV;
+
+ err = mei_restart(dev);
+ if (err)
+ return err;
+
+ /* Start timer if stopped in suspend */
+ schedule_delayed_work(&dev->timer_work, HZ);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_resume);
+
+static const struct auxiliary_device_id mei_gsc_id_table[] = {
+ {
+ .name = "i915.mei-gsc",
+ .driver_data = MEI_ME_GSC_CFG,
+
+ },
+ {
+ .name = "i915.mei-gscfi",
+ .driver_data = MEI_ME_GSCFI_CFG,
+ },
+ {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(auxiliary, mei_gsc_id_table);
+
+static struct auxiliary_driver mei_gsc_driver = {
+ .probe = mei_gsc_probe,
+ .remove = mei_gsc_remove,
+ .driver = {
+ /* auxiliary_driver_register() sets .name to be the modname */
+ .pm = &mei_gsc_pm_ops,
+ },
+ .id_table = mei_gsc_id_table
+};
+module_auxiliary_driver(mei_gsc_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_ALIAS("auxiliary:i915.mei-gsc");
+MODULE_ALIAS("auxiliary:i915.mei-gscfi");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index d3a6c0728645..9748d14849a1 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -1226,6 +1226,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
me_intr_disable(dev, hcsr);
return IRQ_WAKE_THREAD;
}
+EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler);
/**
* mei_me_irq_thread_handler - function called after ISR to handle the interrupt
@@ -1320,6 +1321,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
mutex_unlock(&dev->device_lock);
return IRQ_HANDLED;
}
+EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
static const struct mei_hw_ops mei_me_hw_ops = {
@@ -1433,6 +1435,12 @@ static bool mei_me_fw_type_sps(const struct pci_dev *pdev)
#define MEI_CFG_KIND_ITOUCH \
.kind = "itouch"
+#define MEI_CFG_TYPE_GSC \
+ .kind = "gsc"
+
+#define MEI_CFG_TYPE_GSCFI \
+ .kind = "gscfi"
+
#define MEI_CFG_FW_SPS \
.quirk_probe = mei_me_fw_type_sps
@@ -1565,6 +1573,18 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = {
MEI_CFG_FW_SPS,
};
+/* Graphics System Controller */
+static const struct mei_cfg mei_me_gsc_cfg = {
+ MEI_CFG_TYPE_GSC,
+ MEI_CFG_PCH8_HFS,
+};
+
+/* Graphics System Controller Firmware Interface */
+static const struct mei_cfg mei_me_gscfi_cfg = {
+ MEI_CFG_TYPE_GSCFI,
+ MEI_CFG_PCH8_HFS,
+};
+
/*
* mei_cfg_list - A list of platform platform specific configurations.
* Note: has to be synchronized with enum mei_cfg_idx.
@@ -1585,6 +1605,8 @@ static const struct mei_cfg *const mei_cfg_list[] = {
[MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
[MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
[MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
+ [MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,
+ [MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,
};
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
@@ -1595,7 +1617,8 @@ const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
return NULL;
return mei_cfg_list[idx];
-};
+}
+EXPORT_SYMBOL_GPL(mei_me_get_cfg);
/**
* mei_me_dev_init - allocates and initializes the mei device structure
@@ -1630,4 +1653,4 @@ struct mei_device *mei_me_dev_init(struct device *parent,
return dev;
}
-
+EXPORT_SYMBOL_GPL(mei_me_dev_init);
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index 00a7132ac7a2..a071c645e905 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -112,6 +112,8 @@ enum mei_cfg_idx {
MEI_ME_PCH12_SPS_ITOUCH_CFG,
MEI_ME_PCH15_CFG,
MEI_ME_PCH15_SPS_CFG,
+ MEI_ME_GSC_CFG,
+ MEI_ME_GSCFI_CFG,
MEI_ME_NUM_CFG,
};
--
2.32.0
On 3/15/2022 6:11 AM, Alexander Usyskin wrote:
> From: Tomas Winkler <[email protected]>
>
> GSC is a graphics system controller, based on CSE, it provides
> a chassis controller for graphics discrete cards, as well as it
> supports media protection on selected devices.
>
> mei_gsc binds to a auxiliary devices exposed by Intel discrete
> driver i915.
>
> Signed-off-by: Alexander Usyskin <[email protected]>
> Signed-off-by: Tomas Winkler <[email protected]>
Reviewed-by: Daniele Ceraolo Spurio <[email protected]>
Daniele
> ---
> V4: drop debug prints
> replace selects with depends on in Kconfig
> V5: Rebase
> V6: Rebase
> V7: add Greg KH Reviewed-by
> V8: Rebase
> V9: Rebase
> V11: explicitely call devm_free_irq on error path and remove
> ---
> drivers/misc/mei/Kconfig | 14 +++
> drivers/misc/mei/Makefile | 3 +
> drivers/misc/mei/gsc-me.c | 194 ++++++++++++++++++++++++++++++++++++++
> drivers/misc/mei/hw-me.c | 27 +++++-
> drivers/misc/mei/hw-me.h | 2 +
> 5 files changed, 238 insertions(+), 2 deletions(-)
> create mode 100644 drivers/misc/mei/gsc-me.c
>
> diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
> index 0e0bcd0da852..d21486d69df2 100644
> --- a/drivers/misc/mei/Kconfig
> +++ b/drivers/misc/mei/Kconfig
> @@ -46,6 +46,20 @@ config INTEL_MEI_TXE
> Supported SoCs:
> Intel Bay Trail
>
> +config INTEL_MEI_GSC
> + tristate "Intel MEI GSC embedded device"
> + depends on INTEL_MEI
> + depends on INTEL_MEI_ME
> + depends on X86 && PCI
> + depends on DRM_I915
> + help
> + Intel auxiliary driver for GSC devices embedded in Intel graphics devices.
> +
> + An MEI device here called GSC can be embedded in an
> + Intel graphics devices, to support a range of chassis
> + tasks such as graphics card firmware update and security
> + tasks.
> +
> source "drivers/misc/mei/hdcp/Kconfig"
> source "drivers/misc/mei/pxp/Kconfig"
>
> diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
> index d8e5165917f2..fb740d754900 100644
> --- a/drivers/misc/mei/Makefile
> +++ b/drivers/misc/mei/Makefile
> @@ -18,6 +18,9 @@ obj-$(CONFIG_INTEL_MEI_ME) += mei-me.o
> mei-me-objs := pci-me.o
> mei-me-objs += hw-me.o
>
> +obj-$(CONFIG_INTEL_MEI_GSC) += mei-gsc.o
> +mei-gsc-objs := gsc-me.o
> +
> obj-$(CONFIG_INTEL_MEI_TXE) += mei-txe.o
> mei-txe-objs := pci-txe.o
> mei-txe-objs += hw-txe.o
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> new file mode 100644
> index 000000000000..64b02adf3149
> --- /dev/null
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -0,0 +1,194 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
> + *
> + * Intel Management Engine Interface (Intel MEI) Linux driver
> + */
> +
> +#include <linux/module.h>
> +#include <linux/mei_aux.h>
> +#include <linux/device.h>
> +#include <linux/irqreturn.h>
> +#include <linux/jiffies.h>
> +#include <linux/ktime.h>
> +#include <linux/delay.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "mei_dev.h"
> +#include "hw-me.h"
> +#include "hw-me-regs.h"
> +
> +#include "mei-trace.h"
> +
> +#define MEI_GSC_RPM_TIMEOUT 500
> +
> +static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
> +{
> + struct mei_me_hw *hw = to_me_hw(dev);
> +
> + *val = ioread32(hw->mem_addr + where + 0xC00);
> +
> + return 0;
> +}
> +
> +static int mei_gsc_probe(struct auxiliary_device *aux_dev,
> + const struct auxiliary_device_id *aux_dev_id)
> +{
> + struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
> + struct mei_device *dev;
> + struct mei_me_hw *hw;
> + struct device *device;
> + const struct mei_cfg *cfg;
> + int ret;
> +
> + cfg = mei_me_get_cfg(aux_dev_id->driver_data);
> + if (!cfg)
> + return -ENODEV;
> +
> + device = &aux_dev->dev;
> +
> + dev = mei_me_dev_init(device, cfg);
> + if (IS_ERR(dev)) {
> + ret = PTR_ERR(dev);
> + goto err;
> + }
> +
> + hw = to_me_hw(dev);
> + hw->mem_addr = devm_ioremap_resource(device, &adev->bar);
> + if (IS_ERR(hw->mem_addr)) {
> + dev_err(device, "mmio not mapped\n");
> + ret = PTR_ERR(hw->mem_addr);
> + goto err;
> + }
> +
> + hw->irq = adev->irq;
> + hw->read_fws = mei_gsc_read_hfs;
> +
> + dev_set_drvdata(device, dev);
> +
> + ret = devm_request_threaded_irq(device, hw->irq,
> + mei_me_irq_quick_handler,
> + mei_me_irq_thread_handler,
> + IRQF_ONESHOT, KBUILD_MODNAME, dev);
> + if (ret) {
> + dev_err(device, "irq register failed %d\n", ret);
> + goto err;
> + }
> +
> + pm_runtime_get_noresume(device);
> + pm_runtime_set_active(device);
> + pm_runtime_enable(device);
> +
> + if (mei_start(dev)) {
> + dev_err(device, "init hw failure.\n");
> + ret = -ENODEV;
> + goto irq_err;
> + }
> +
> + pm_runtime_set_autosuspend_delay(device, MEI_GSC_RPM_TIMEOUT);
> + pm_runtime_use_autosuspend(device);
> +
> + ret = mei_register(dev, device);
> + if (ret)
> + goto register_err;
> +
> + pm_runtime_put_noidle(device);
> + return 0;
> +
> +register_err:
> + mei_stop(dev);
> +irq_err:
> + devm_free_irq(device, hw->irq, dev);
> +
> +err:
> + dev_err(device, "probe failed: %d\n", ret);
> + dev_set_drvdata(device, NULL);
> + return ret;
> +}
> +
> +static void mei_gsc_remove(struct auxiliary_device *aux_dev)
> +{
> + struct mei_device *dev;
> + struct mei_me_hw *hw;
> +
> + dev = dev_get_drvdata(&aux_dev->dev);
> + if (!dev)
> + return;
> +
> + hw = to_me_hw(dev);
> +
> + mei_stop(dev);
> +
> + mei_deregister(dev);
> +
> + pm_runtime_disable(&aux_dev->dev);
> +
> + mei_disable_interrupts(dev);
> + devm_free_irq(&aux_dev->dev, hw->irq, dev);
> +}
> +
> +static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
> +{
> + struct mei_device *dev = dev_get_drvdata(device);
> +
> + if (!dev)
> + return -ENODEV;
> +
> + mei_stop(dev);
> +
> + mei_disable_interrupts(dev);
> +
> + return 0;
> +}
> +
> +static int __maybe_unused mei_gsc_pm_resume(struct device *device)
> +{
> + struct mei_device *dev = dev_get_drvdata(device);
> + int err;
> +
> + if (!dev)
> + return -ENODEV;
> +
> + err = mei_restart(dev);
> + if (err)
> + return err;
> +
> + /* Start timer if stopped in suspend */
> + schedule_delayed_work(&dev->timer_work, HZ);
> +
> + return 0;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(mei_gsc_pm_ops, mei_gsc_pm_suspend, mei_gsc_pm_resume);
> +
> +static const struct auxiliary_device_id mei_gsc_id_table[] = {
> + {
> + .name = "i915.mei-gsc",
> + .driver_data = MEI_ME_GSC_CFG,
> +
> + },
> + {
> + .name = "i915.mei-gscfi",
> + .driver_data = MEI_ME_GSCFI_CFG,
> + },
> + {
> + /* sentinel */
> + }
> +};
> +MODULE_DEVICE_TABLE(auxiliary, mei_gsc_id_table);
> +
> +static struct auxiliary_driver mei_gsc_driver = {
> + .probe = mei_gsc_probe,
> + .remove = mei_gsc_remove,
> + .driver = {
> + /* auxiliary_driver_register() sets .name to be the modname */
> + .pm = &mei_gsc_pm_ops,
> + },
> + .id_table = mei_gsc_id_table
> +};
> +module_auxiliary_driver(mei_gsc_driver);
> +
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_ALIAS("auxiliary:i915.mei-gsc");
> +MODULE_ALIAS("auxiliary:i915.mei-gscfi");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
> index d3a6c0728645..9748d14849a1 100644
> --- a/drivers/misc/mei/hw-me.c
> +++ b/drivers/misc/mei/hw-me.c
> @@ -1226,6 +1226,7 @@ irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
> me_intr_disable(dev, hcsr);
> return IRQ_WAKE_THREAD;
> }
> +EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler);
>
> /**
> * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
> @@ -1320,6 +1321,7 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
> mutex_unlock(&dev->device_lock);
> return IRQ_HANDLED;
> }
> +EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
>
> static const struct mei_hw_ops mei_me_hw_ops = {
>
> @@ -1433,6 +1435,12 @@ static bool mei_me_fw_type_sps(const struct pci_dev *pdev)
> #define MEI_CFG_KIND_ITOUCH \
> .kind = "itouch"
>
> +#define MEI_CFG_TYPE_GSC \
> + .kind = "gsc"
> +
> +#define MEI_CFG_TYPE_GSCFI \
> + .kind = "gscfi"
> +
> #define MEI_CFG_FW_SPS \
> .quirk_probe = mei_me_fw_type_sps
>
> @@ -1565,6 +1573,18 @@ static const struct mei_cfg mei_me_pch15_sps_cfg = {
> MEI_CFG_FW_SPS,
> };
>
> +/* Graphics System Controller */
> +static const struct mei_cfg mei_me_gsc_cfg = {
> + MEI_CFG_TYPE_GSC,
> + MEI_CFG_PCH8_HFS,
> +};
> +
> +/* Graphics System Controller Firmware Interface */
> +static const struct mei_cfg mei_me_gscfi_cfg = {
> + MEI_CFG_TYPE_GSCFI,
> + MEI_CFG_PCH8_HFS,
> +};
> +
> /*
> * mei_cfg_list - A list of platform platform specific configurations.
> * Note: has to be synchronized with enum mei_cfg_idx.
> @@ -1585,6 +1605,8 @@ static const struct mei_cfg *const mei_cfg_list[] = {
> [MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
> [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
> [MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
> + [MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,
> + [MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,
> };
>
> const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
> @@ -1595,7 +1617,8 @@ const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
> return NULL;
>
> return mei_cfg_list[idx];
> -};
> +}
> +EXPORT_SYMBOL_GPL(mei_me_get_cfg);
>
> /**
> * mei_me_dev_init - allocates and initializes the mei device structure
> @@ -1630,4 +1653,4 @@ struct mei_device *mei_me_dev_init(struct device *parent,
>
> return dev;
> }
> -
> +EXPORT_SYMBOL_GPL(mei_me_dev_init);
> diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
> index 00a7132ac7a2..a071c645e905 100644
> --- a/drivers/misc/mei/hw-me.h
> +++ b/drivers/misc/mei/hw-me.h
> @@ -112,6 +112,8 @@ enum mei_cfg_idx {
> MEI_ME_PCH12_SPS_ITOUCH_CFG,
> MEI_ME_PCH15_CFG,
> MEI_ME_PCH15_SPS_CFG,
> + MEI_ME_GSC_CFG,
> + MEI_ME_GSCFI_CFG,
> MEI_ME_NUM_CFG,
> };
>
From: Tomas Winkler <[email protected]>
GSC is a graphics system controller, it provides
a chassis controller for graphics discrete cards.
There are two MEI interfaces in GSC: HECI1 and HECI2.
Both interfaces are on the BAR0 at offsets 0x00258000 and 0x00259000.
GSC is a GT Engine (class 4: instance 6). HECI1 interrupt is signaled
via bit 15 and HECI2 via bit 14 in the interrupt register.
This patch exports GSC as auxiliary device for mei driver to bind to
for HECI2 interface and prepares for HECI1 interface as
it will follow up soon.
CC: Rodrigo Vivi <[email protected]>
Signed-off-by: Tomas Winkler <[email protected]>
Signed-off-by: Vitaly Lubart <[email protected]>
Signed-off-by: Alexander Usyskin <[email protected]>
Acked-by: Tvrtko Ursulin <[email protected]>
---
V4: add header to the MAINTAINERS file
drop empty line
V5: rebase
V6: rebase, drop redundant assignments
V7: add Greg KH Reviewed-by
V8: rename dev_priv variable to i915,
drop data from irq_set_chip_data,
switch intel_gsc_irq_handler with gsc_irq_handler to have same
prefixes in the external API,
add error prints and use right drm print functions
V9: do not fail on zero irq number,
add defence aginst discepancy between has_pxp flag and actual
definition structure,
move more error prints to drm prints
V11: fix code style, rename and move defines, add missed interrupt mask
---
MAINTAINERS | 1 +
drivers/gpu/drm/i915/Kconfig | 1 +
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/gt/intel_gsc.c | 204 +++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gsc.h | 37 ++++
drivers/gpu/drm/i915/gt/intel_gt.c | 3 +
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 2 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
include/linux/mei_aux.h | 19 +++
15 files changed, 303 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
create mode 100644 include/linux/mei_aux.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4b5ea01549eb..69a1cdec2b8e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9833,6 +9833,7 @@ S: Supported
F: Documentation/driver-api/mei/*
F: drivers/misc/mei/
F: drivers/watchdog/mei_wdt.c
+F: include/linux/mei_aux.h
F: include/linux/mei_cl_bus.h
F: include/uapi/linux/mei.h
F: samples/mei/*
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 98c5450b8eac..2660a85175d9 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -30,6 +30,7 @@ config DRM_I915
select VMAP_PFN
select DRM_TTM
select DRM_BUDDY
+ select AUXILIARY_BUS
help
Choose this option if you have a system that has "Intel Graphics
Media Accelerator" or "HD Graphics" integrated graphics,
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1a771ee5b1d0..9be7b13d8822 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -196,6 +196,9 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_huc_debugfs.o \
gt/uc/intel_huc_fw.o
+# graphics system controller (GSC) support
+i915-y += gt/intel_gsc.o
+
# modesetting core code
i915-y += \
display/hsw_ips.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
new file mode 100644
index 000000000000..21e860861f0b
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ */
+
+#include <linux/irq.h>
+#include <linux/mei_aux.h>
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "gt/intel_gsc.h"
+#include "gt/intel_gt.h"
+
+#define GSC_BAR_LENGTH 0x00000FFC
+
+static void gsc_irq_mask(struct irq_data *d)
+{
+ /* generic irq handling */
+}
+
+static void gsc_irq_unmask(struct irq_data *d)
+{
+ /* generic irq handling */
+}
+
+static struct irq_chip gsc_irq_chip = {
+ .name = "gsc_irq_chip",
+ .irq_mask = gsc_irq_mask,
+ .irq_unmask = gsc_irq_unmask,
+};
+
+static int gsc_irq_init(int irq)
+{
+ irq_set_chip_and_handler_name(irq, &gsc_irq_chip,
+ handle_simple_irq, "gsc_irq_handler");
+
+ return irq_set_chip_data(irq, NULL);
+}
+
+struct gsc_def {
+ const char *name;
+ unsigned long bar;
+ size_t bar_size;
+};
+
+/* gsc resources and definitions (HECI1 and HECI2) */
+static const struct gsc_def gsc_def_dg1[] = {
+ {
+ /* HECI1 not yet implemented. */
+ },
+ {
+ .name = "mei-gscfi",
+ .bar = DG1_GSC_HECI2_BASE,
+ .bar_size = GSC_BAR_LENGTH,
+ }
+};
+
+static void gsc_release_dev(struct device *dev)
+{
+ struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);
+ struct mei_aux_device *adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+
+ kfree(adev);
+}
+
+static void gsc_destroy_one(struct intel_gsc_intf *intf)
+{
+ if (intf->adev) {
+ auxiliary_device_delete(&intf->adev->aux_dev);
+ auxiliary_device_uninit(&intf->adev->aux_dev);
+ intf->adev = NULL;
+ }
+ if (intf->irq >= 0)
+ irq_free_desc(intf->irq);
+ intf->irq = -1;
+}
+
+static void gsc_init_one(struct drm_i915_private *i915,
+ struct intel_gsc_intf *intf,
+ unsigned int intf_id)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct mei_aux_device *adev;
+ struct auxiliary_device *aux_dev;
+ const struct gsc_def *def;
+ int ret;
+
+ intf->irq = -1;
+ intf->id = intf_id;
+
+ if (intf_id == 0 && !HAS_HECI_PXP(i915))
+ return;
+
+ def = &gsc_def_dg1[intf_id];
+
+ if (!def->name) {
+ drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", intf_id + 1);
+ return;
+ }
+
+ intf->irq = irq_alloc_desc(0);
+ if (intf->irq < 0) {
+ drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
+ return;
+ }
+
+ ret = gsc_irq_init(intf->irq);
+ if (ret < 0) {
+ drm_err(&i915->drm, "gsc irq init failed %d\n", ret);
+ goto fail;
+ }
+
+ adev = kzalloc(sizeof(*adev), GFP_KERNEL);
+ if (!adev)
+ goto fail;
+
+ adev->irq = intf->irq;
+ adev->bar.parent = &pdev->resource[0];
+ adev->bar.start = def->bar + pdev->resource[0].start;
+ adev->bar.end = adev->bar.start + def->bar_size - 1;
+ adev->bar.flags = IORESOURCE_MEM;
+ adev->bar.desc = IORES_DESC_NONE;
+
+ aux_dev = &adev->aux_dev;
+ aux_dev->name = def->name;
+ aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |
+ PCI_DEVID(pdev->bus->number, pdev->devfn);
+ aux_dev->dev.parent = &pdev->dev;
+ aux_dev->dev.release = gsc_release_dev;
+
+ ret = auxiliary_device_init(aux_dev);
+ if (ret < 0) {
+ drm_err(&i915->drm, "gsc aux init failed %d\n", ret);
+ kfree(adev);
+ goto fail;
+ }
+
+ ret = auxiliary_device_add(aux_dev);
+ if (ret < 0) {
+ drm_err(&i915->drm, "gsc aux add failed %d\n", ret);
+ /* adev will be freed with the put_device() and .release sequence */
+ auxiliary_device_uninit(aux_dev);
+ goto fail;
+ }
+ intf->adev = adev;
+
+ return;
+fail:
+ gsc_destroy_one(intf);
+}
+
+static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
+{
+ int ret;
+
+ if (intf_id >= INTEL_GSC_NUM_INTERFACES) {
+ drm_warn_once(>->i915->drm, "GSC irq: intf_id %d is out of range", intf_id);
+ return;
+ }
+
+ if (!HAS_HECI_GSC(gt->i915)) {
+ drm_warn_once(>->i915->drm, "GSC irq: not supported");
+ return;
+ }
+
+ if (gt->gsc.intf[intf_id].irq < 0) {
+ drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set");
+ return;
+ }
+
+ ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
+ if (ret)
+ drm_err_ratelimited(>->i915->drm, "error handling GSC irq: %d\n", ret);
+}
+
+void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir)
+{
+ if (iir & GSC_IRQ_INTF(0))
+ gsc_irq_handler(gt, 0);
+ if (iir & GSC_IRQ_INTF(1))
+ gsc_irq_handler(gt, 1);
+}
+
+void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
+{
+ unsigned int i;
+
+ if (!HAS_HECI_GSC(i915))
+ return;
+
+ for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
+ gsc_init_one(i915, &gsc->intf[i], i);
+}
+
+void intel_gsc_fini(struct intel_gsc *gsc)
+{
+ struct intel_gt *gt = gsc_to_gt(gsc);
+ unsigned int i;
+
+ if (!HAS_HECI_GSC(gt->i915))
+ return;
+
+ for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
+ gsc_destroy_one(&gsc->intf[i]);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
new file mode 100644
index 000000000000..68582f912b21
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2019-2022, Intel Corporation. All rights reserved.
+ */
+#ifndef __INTEL_GSC_DEV_H__
+#define __INTEL_GSC_DEV_H__
+
+#include <linux/types.h>
+
+struct drm_i915_private;
+struct intel_gt;
+struct mei_aux_device;
+
+#define INTEL_GSC_NUM_INTERFACES 2
+/*
+ * The HECI1 bit corresponds to bit15 and HECI2 to bit14.
+ * The reason for this is to allow growth for more interfaces in the future.
+ */
+#define GSC_IRQ_INTF(_x) BIT(15 - (_x))
+
+/**
+ * struct intel_gsc - graphics security controller
+ * @intf : gsc interface
+ */
+struct intel_gsc {
+ struct intel_gsc_intf {
+ struct mei_aux_device *adev;
+ int irq;
+ unsigned int id;
+ } intf[INTEL_GSC_NUM_INTERFACES];
+};
+
+void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *dev_priv);
+void intel_gsc_fini(struct intel_gsc *gsc);
+void intel_gsc_irq_handler(struct intel_gt *gt, u32 iir);
+
+#endif /* __INTEL_GSC_DEV_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8a2483ccbfb9..fd83ab4b8849 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -444,6 +444,8 @@ void intel_gt_chipset_flush(struct intel_gt *gt)
void intel_gt_driver_register(struct intel_gt *gt)
{
+ intel_gsc_init(>->gsc, gt->i915);
+
intel_rps_driver_register(>->rps);
intel_gt_debugfs_register(gt);
@@ -766,6 +768,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
intel_wakeref_t wakeref;
intel_rps_driver_unregister(>->rps);
+ intel_gsc_fini(>->gsc);
intel_pxp_fini(>->pxp);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 0f571c8ee22b..de779a505c21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -34,6 +34,11 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
return container_of(huc, struct intel_gt, uc.huc);
}
+static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
+{
+ return container_of(gsc, struct intel_gt, gsc);
+}
+
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index e443ac4c8059..88b4becfcb17 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -68,6 +68,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_KCR_INSTANCE)
return intel_pxp_irq_handler(>->pxp, iir);
+ if (instance == OTHER_GSC_INSTANCE)
+ return intel_gsc_irq_handler(gt, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -184,6 +187,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, 0);
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, 0);
+ if (HAS_HECI_GSC(gt->i915))
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE, 0);
/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~0);
@@ -201,6 +206,8 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~0);
if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~0);
+ if (HAS_HECI_GSC(gt->i915))
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
@@ -215,6 +222,7 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
u32 irqs = GT_RENDER_USER_INTERRUPT;
+ const u32 gsc_mask = GSC_IRQ_INTF(0) | GSC_IRQ_INTF(1);
u32 dmask;
u32 smask;
@@ -233,6 +241,9 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, dmask);
if (CCS_MASK(gt))
intel_uncore_write(uncore, GEN12_CCS_RSVD_INTR_ENABLE, smask);
+ if (HAS_HECI_GSC(gt->i915))
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_ENABLE,
+ gsc_mask);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
@@ -250,6 +261,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
intel_uncore_write(uncore, GEN12_CCS0_CCS1_INTR_MASK, ~dmask);
if (HAS_ENGINE(gt, CCS2) || HAS_ENGINE(gt, CCS3))
intel_uncore_write(uncore, GEN12_CCS2_CCS3_INTR_MASK, ~dmask);
+ if (HAS_HECI_GSC(gt->i915))
+ intel_uncore_write(uncore, GEN11_GUNIT_CSME_INTR_MASK, ~gsc_mask);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 19cd34f24263..a277fb480cc8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1483,6 +1483,7 @@
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
#define OTHER_KCR_INSTANCE 4
+#define OTHER_GSC_INSTANCE 6
#define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f20687796490..5556d55f76ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -16,6 +16,7 @@
#include <linux/workqueue.h>
#include "uc/intel_uc.h"
+#include "intel_gsc.h"
#include "i915_vma.h"
#include "intel_engine_types.h"
@@ -72,6 +73,7 @@ struct intel_gt {
struct i915_ggtt *ggtt;
struct intel_uc uc;
+ struct intel_gsc gsc;
struct mutex tlb_invalidate_lock;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 26df561a4e94..17f1f114a618 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1307,6 +1307,14 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
+#define HAS_HECI_PXP(dev_priv) \
+ (INTEL_INFO(dev_priv)->has_heci_pxp)
+
+#define HAS_HECI_GSCFI(dev_priv) \
+ (INTEL_INFO(dev_priv)->has_heci_gscfi)
+
+#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
+
#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 67b89769f577..a948f566bd3d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -901,7 +901,8 @@ static const struct intel_device_info rkl_info = {
.has_llc = 0, \
.has_pxp = 0, \
.has_snoop = 1, \
- .is_dgfx = 1
+ .is_dgfx = 1, \
+ .has_heci_gscfi = 1
static const struct intel_device_info dg1_info = {
GEN12_FEATURES,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddbc7a685a50..63c56d668963 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -976,6 +976,8 @@
#define GEN12_COMPUTE2_RING_BASE 0x1e000
#define GEN12_COMPUTE3_RING_BASE 0x26000
#define BLT_RING_BASE 0x22000
+#define DG1_GSC_HECI1_BASE 0x00258000
+#define DG1_GSC_HECI2_BASE 0x00259000
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index f9b955810593..576d15a04c9e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -141,6 +141,8 @@ enum intel_ppgtt_type {
func(has_flat_ccs); \
func(has_global_mocs); \
func(has_gt_uc); \
+ func(has_heci_pxp); \
+ func(has_heci_gscfi); \
func(has_guc_deprivilege); \
func(has_l3_dpf); \
func(has_llc); \
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
new file mode 100644
index 000000000000..587f25128848
--- /dev/null
+++ b/include/linux/mei_aux.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022, Intel Corporation. All rights reserved.
+ */
+#ifndef _LINUX_MEI_AUX_H
+#define _LINUX_MEI_AUX_H
+
+#include <linux/auxiliary_bus.h>
+
+struct mei_aux_device {
+ struct auxiliary_device aux_dev;
+ int irq;
+ struct resource bar;
+};
+
+#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
+ container_of(auxiliary_dev, struct mei_aux_device, aux_dev)
+
+#endif /* _LINUX_MEI_AUX_H */
--
2.32.0
Can you re-send this series with an added patch to force
CONFIG_INTEL_MEI_GSC to be selected for CI? we don't need to review or
merge that additional patch, but I want to make sure we get CI results
with the config turned on before we merge this series. I'm also going to
ping the CI team to see if we can turn it on by default for CI builds.
Daniele
On 3/15/2022 6:11 AM, Alexander Usyskin wrote:
> GSC is a graphics system controller, it provides
> a chassis controller for graphics discrete cards.
>
> There are two MEI interfaces in GSC: HECI1 and HECI2.
>
> This series includes instantiation of the auxiliary devices for HECI2
> and mei-gsc auxiliary device driver that binds to the auxiliary device.
>
> The prinicpal user of this interface is the
> Intel Graphics System Controller Firmware Update Library (IGSC FU)
> (https://github.com/intel/igsc)
>
> In v2 the platform device was replaced by the auxiliary device.
> v3 is the rebase over drm-tip to make public CI running.
> In v4 the not needed debug prints and empty line were removed,
> 'select' were replaced by 'depends on' in MEI Kconfig,
> the new include file now listed in the MAINTATINERS file.
> V5, rebase and add Greg KH Reviewed-by
> V6, rebase and drop redundant assignments found by the kernel test
> robot.
> V7, add Greg KH Reviewed-by to the individual patches
> V8, address Tvrtko comments for i915
> V9, rebase and address more Tvrtko comments, use drm error printing
> V10, rebase
> V11, address Rodrigo comments about code style,
> set missed mask in the interrupt config,
> add explicit devm_irq_free to error and remove flows
>
> Tomas, please look at the devm_irq_free part.
>
> Alexander Usyskin (2):
> mei: gsc: setup char driver alive in spite of firmware handshake
> failure
> mei: gsc: retrieve the firmware version
>
> Tomas Winkler (3):
> drm/i915/gsc: add gsc as a mei auxiliary device
> mei: add support for graphics system controller (gsc) devices
> mei: gsc: add runtime pm handlers
>
> MAINTAINERS | 1 +
> drivers/gpu/drm/i915/Kconfig | 1 +
> drivers/gpu/drm/i915/Makefile | 3 +
> drivers/gpu/drm/i915/gt/intel_gsc.c | 204 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_gsc.h | 37 ++++
> drivers/gpu/drm/i915/gt/intel_gt.c | 3 +
> drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
> drivers/gpu/drm/i915/i915_drv.h | 8 +
> drivers/gpu/drm/i915/i915_pci.c | 3 +-
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 2 +
> drivers/misc/mei/Kconfig | 14 ++
> drivers/misc/mei/Makefile | 3 +
> drivers/misc/mei/bus-fixup.c | 25 +++
> drivers/misc/mei/gsc-me.c | 259 +++++++++++++++++++++++
> drivers/misc/mei/hw-me.c | 29 ++-
> drivers/misc/mei/hw-me.h | 2 +
> include/linux/mei_aux.h | 19 ++
> 21 files changed, 633 insertions(+), 3 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
> create mode 100644 drivers/misc/mei/gsc-me.c
> create mode 100644 include/linux/mei_aux.h
>
Hi
As I understand the config patch should go to https://gitlab.freedesktop.org/gfx-ci/i915-infra kconfig/debug, branch "master".
Thus, this series does not need this change. Am I right?
--
Thanks,
Sasha
> -----Original Message-----
> From: Ceraolo Spurio, Daniele <[email protected]>
> Sent: Tuesday, March 22, 2022 22:10
> To: Usyskin, Alexander <[email protected]>; Greg Kroah-
> Hartman <[email protected]>; Jani Nikula
> <[email protected]>; Joonas Lahtinen
> <[email protected]>; Vivi, Rodrigo <[email protected]>;
> David Airlie <[email protected]>; Daniel Vetter <[email protected]>; Tvrtko
> Ursulin <[email protected]>
> Cc: [email protected]; Winkler, Tomas
> <[email protected]>; Lubart, Vitaly <[email protected]>; intel-
> [email protected]
> Subject: Re: [Intel-gfx] [PATCH v11 0/5] Add driver for GSC controller
>
> Can you re-send this series with an added patch to force
> CONFIG_INTEL_MEI_GSC to be selected for CI? we don't need to review or
> merge that additional patch, but I want to make sure we get CI results
> with the config turned on before we merge this series. I'm also going to
> ping the CI team to see if we can turn it on by default for CI builds.
>
> Daniele
>
> On 3/15/2022 6:11 AM, Alexander Usyskin wrote:
> > GSC is a graphics system controller, it provides
> > a chassis controller for graphics discrete cards.
> >
> > There are two MEI interfaces in GSC: HECI1 and HECI2.
> >
> > This series includes instantiation of the auxiliary devices for HECI2
> > and mei-gsc auxiliary device driver that binds to the auxiliary device.
> >
> > The prinicpal user of this interface is the
> > Intel Graphics System Controller Firmware Update Library (IGSC FU)
> > (https://github.com/intel/igsc)
> >
> > In v2 the platform device was replaced by the auxiliary device.
> > v3 is the rebase over drm-tip to make public CI running.
> > In v4 the not needed debug prints and empty line were removed,
> > 'select' were replaced by 'depends on' in MEI Kconfig,
> > the new include file now listed in the MAINTATINERS file.
> > V5, rebase and add Greg KH Reviewed-by
> > V6, rebase and drop redundant assignments found by the kernel test
> > robot.
> > V7, add Greg KH Reviewed-by to the individual patches
> > V8, address Tvrtko comments for i915
> > V9, rebase and address more Tvrtko comments, use drm error printing
> > V10, rebase
> > V11, address Rodrigo comments about code style,
> > set missed mask in the interrupt config,
> > add explicit devm_irq_free to error and remove flows
> >
> > Tomas, please look at the devm_irq_free part.
> >
> > Alexander Usyskin (2):
> > mei: gsc: setup char driver alive in spite of firmware handshake
> > failure
> > mei: gsc: retrieve the firmware version
> >
> > Tomas Winkler (3):
> > drm/i915/gsc: add gsc as a mei auxiliary device
> > mei: add support for graphics system controller (gsc) devices
> > mei: gsc: add runtime pm handlers
> >
> > MAINTAINERS | 1 +
> > drivers/gpu/drm/i915/Kconfig | 1 +
> > drivers/gpu/drm/i915/Makefile | 3 +
> > drivers/gpu/drm/i915/gt/intel_gsc.c | 204 ++++++++++++++++++
> > drivers/gpu/drm/i915/gt/intel_gsc.h | 37 ++++
> > drivers/gpu/drm/i915/gt/intel_gt.c | 3 +
> > drivers/gpu/drm/i915/gt/intel_gt.h | 5 +
> > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
> > drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
> > drivers/gpu/drm/i915/i915_drv.h | 8 +
> > drivers/gpu/drm/i915/i915_pci.c | 3 +-
> > drivers/gpu/drm/i915/i915_reg.h | 2 +
> > drivers/gpu/drm/i915/intel_device_info.h | 2 +
> > drivers/misc/mei/Kconfig | 14 ++
> > drivers/misc/mei/Makefile | 3 +
> > drivers/misc/mei/bus-fixup.c | 25 +++
> > drivers/misc/mei/gsc-me.c | 259 +++++++++++++++++++++++
> > drivers/misc/mei/hw-me.c | 29 ++-
> > drivers/misc/mei/hw-me.h | 2 +
> > include/linux/mei_aux.h | 19 ++
> > 21 files changed, 633 insertions(+), 3 deletions(-)
> > create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.c
> > create mode 100644 drivers/gpu/drm/i915/gt/intel_gsc.h
> > create mode 100644 drivers/misc/mei/gsc-me.c
> > create mode 100644 include/linux/mei_aux.h
> >
Hi,
Yes, the series doesn't need an update, but on the other hand I don't
think we can update the config repo before the new config option is
merged, which we can't do without first running CI with the config
enabled, so we have a catch-22 situation. That's why I suggested that
you resend the series with an additional debug patch that enables the
new config option from within the i915 kconfig, so that CI runs properly
on it, but clearly marking that patch as something that is for CI only
and that we shouldn't merge.
We did the same for the mei-pxp config (here's an example:
https://patchwork.freedesktop.org/patch/460925/?series=96181&rev=2).
The alternative would be to merge an update to i915-infra kconfig/debug
before this series is merged and re-run CI on the existing series with
the updated config, but as mentioned above not sure if that's allowed.
If you can get it in then that's fine for me.
Daniele
On 3/28/2022 12:39 AM, Usyskin, Alexander wrote:
> Hi
>
> As I understand the config patch should go to https://gitlab.freedesktop.org/gfx-ci/i915-infra kconfig/debug, branch "master".
> Thus, this series does not need this change. Am I right?
>