[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (13):
firmware: qcom: scm: Add ipq4019 soc compatible
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts: ipq4019: Update ipq4019-dk01.1 board data
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Enable few peripherals for hk01 board
.../devicetree/bindings/firmware/qcom,scm.txt | 3 +-
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 32 ++-
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 135 +++++++++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 136 ++++++++++-
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++++++++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 262 ++++++++++++++++++++-
drivers/firmware/qcom_scm.c | 3 +
13 files changed, 875 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Add the compatible for ipq4019.
This does not need clocks to do scm calls.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Sricharan R <[email protected]>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++-
drivers/firmware/qcom_scm.c | 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 7b40054..fcf6979 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -11,9 +11,10 @@ Required properties:
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm-msm8996" for MSM8996 platforms
+ * "qcom,scm-ipq4019" for IPQ4019 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
- * No clock required for "qcom,scm-msm8996"
+ * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 5a7d6930..e778af7 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -603,6 +603,9 @@ static void qcom_scm_shutdown(struct platform_device *pdev)
{ .compatible = "qcom,scm-msm8996",
.data = NULL, /* no clocks */
},
+ { .compatible = "qcom,scm-ipq4019",
+ .data = NULL, /* no clocks */
+ },
{ .compatible = "qcom,scm",
.data = (void *)(SCM_HAS_CORE_CLK
| SCM_HAS_IFACE_CLK
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..e38fffa 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -25,7 +25,9 @@
aliases {
spi0 = &spi_0;
+ spi1 = &spi_1;
i2c0 = &i2c_0;
+ i2c1 = &i2c_1;
};
cpus {
@@ -104,6 +106,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019";
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -172,6 +180,22 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
@@ -184,9 +208,24 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
+ pcie0: pci@40000000 {
+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ reg = <0x40000000 0xf1d
+ 0x40000f20 0xa8
+ 0x80000 0x2000
+ 0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ status = "disabled";
+ };
+
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ nand: qpic-nand@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b59e99b..4f209fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000..871ac3f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+
+ soc {
+ qpic_bam: dma@7984000 {
+ status = "ok";
+ };
+
+ nand: qpic-nand@79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +++++++++++++++++++++++++
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b71487a..8c93fd0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
+ qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
new file mode 100644
index 0000000..4562f7f
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
+
+ soc {
+ pcie0: pci@40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ spi_1: spi@78b6000 { /* BLSP1 QUP2 */
+ status = "ok";
+ };
+
+ pinctrl@1000000 {
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 ++++++++
2 files changed, 9 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4f209fb..b71487a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..0843523
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 806fc56..7562650 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pinctrl@1000000 {
+ tlmm: pinctrl@1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -229,6 +229,161 @@
dma-names = "tx", "rx", "cmd";
status = "disabled";
};
+
+ pcie_phy0: phy@86000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x86000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie0: pci@20000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x20000000 0xf1d
+ 0x20000F20 0xa8
+ 0x80000 0x2000
+ 0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0x00d00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
+
+ pcie_phy1: phy@8e000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x8e000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie1: pci@10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d
+ 0x10000F20 0xa8
+ 0x88000 0x2000
+ 0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy1>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0x00d00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Add serial, i2c, bam, spi, qpic peripheral nodes.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++++++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2bc5dec..806fc56 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -124,6 +124,111 @@
clock-names = "core", "iface";
status = "disabled";
};
+
+ blsp_dma: dma@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07884000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ serial_blsp0: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ serial_blsp2: serial@78B1000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78B1000 0x200>;
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 4>,
+ <&blsp_dma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi_0: spi@78b5000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b5000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_0: i2c@78b6000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <400000>;
+ dmas = <&blsp_dma 15>, <&blsp_dma 14>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c_1: i2c@78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b7000 0x600>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 17>, <&blsp_dma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ qpic_bam: dma@7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: nand@79b0000 {
+ compatible = "qcom,ipq8074-nand";
+ reg = <0x79b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6a838b5..81dff867 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
aliases {
serial0 = &blsp1_uart5;
+ serial1 = &serial_blsp2;
};
chosen {
@@ -41,6 +42,47 @@
bias-disable;
};
};
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio42", "gpio43";
+ function = "blsp1_i2c";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pins {
+ mux {
+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
+ function = "blsp0_spi";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ hsuart_pins: hsuart_pins {
+ mux {
+ pins = "gpio46", "gpio47", "gpio48", "gpio49";
+ function = "blsp2_uart";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ qpic_pins: qpic_pins {
+ mux {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
};
serial@78b3000 {
@@ -48,5 +90,66 @@
pinctrl-names = "default";
status = "ok";
};
+
+ spi@78b5000 {
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a11", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ serial@78B1000 {
+ pinctrl-0 = <&hsuart_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ i2c_0@78b6000 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma@7984000 {
+ status = "ok";
+ };
+
+ nand@79b0000 {
+ pinctrl-0 = <&qpic_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
+ phy@86000 {
+ status = "ok";
+ };
+
+ phy@8e000 {
+ status = "ok";
+ };
+
+ pci@20000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+ };
+
+ pci@10000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Add the common data for all dk07 based boards.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83 +++++++++++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 0000000..37a2ea8
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+ compatible = "qcom,ipq4019";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_0_pins: serial0_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ blsp_dma: dma@7884000 {
+ status = "ok";
+ };
+
+ i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ qpic_bam: dma@7984000 {
+ status = "ok";
+ };
+
+ nand: qpic-nand@79b0000 {
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26 +++++++++++++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8c93fd0..0844087 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
+ qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
new file mode 100644
index 0000000..c1e909c
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk07.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
+
+ soc {
+ pinctrl@1000000 {
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Add the common parts for the dk04 boards.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129 ++++++++++++++++++++++++++
1 file changed, 129 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000..96ce081
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+ compatible = "qcom,ipq4019";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
+ soc {
+ pinctrl@1000000 {
+ serial_0_pins: serial0_pinmux {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+ };
+
+ serial_1_pins: serial1_pinmux {
+ mux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+ };
+
+ spi_0_pins: spi_0_pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c_0_pinmux {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+ };
+
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+ };
+
+ serial@78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial@78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ blsp_dma: dma@7884000 {
+ status = "ok";
+ };
+
+ spi_0: spi@78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ pcie0: pci@40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
The max opp frequency is 716MHZ. So update that.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e38fffa..2ee71c2 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000 1100000
200000 1100000
500000 1100000
- 666000 1100000
+ 716000 1100000
>;
clock-latency = <256000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Adds missing memory, reserved-memory nodes.
Signed-off-by: Sricharan R <[email protected]>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28 +++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ad0fbc9 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,34 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd1@87000000 {
+ /* Reserved for other subsystem */
+ reg = <0x87000000 0x500000>;
+ no-map;
+ };
+
+ wifi_dump@87500000 {
+ reg = <0x87500000 0x600000>;
+ no-map;
+ };
+
+ rsvd2@87B00000 {
+ /* Reserved for other subsystem */
+ reg = <0x87B00000 0x500000>;
+ no-map;
+ };
+ };
+
soc {
rng@22000 {
status = "ok";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On 2018-03-16 15:08, Sricharan R wrote:
> Now with the driver updates for some peripherals being there,
> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
> peripheral support.
>
> Signed-off-by: Sricharan R <[email protected]>
Reviwed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 134
> ++++++++++++++++++++++++++++++++++++
> 1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index 10d112a..e38fffa 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -25,7 +25,9 @@
>
> aliases {
> spi0 = &spi_0;
> + spi1 = &spi_1;
> i2c0 = &i2c_0;
> + i2c1 = &i2c_1;
> };
>
> cpus {
> @@ -104,6 +106,12 @@
> };
> };
>
> + firmware {
> + scm {
> + compatible = "qcom,scm-ipq4019";
> + };
> + };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts = <1 2 0xf08>,
> @@ -172,6 +180,22 @@
> clock-names = "core", "iface";
> #address-cells = <1>;
> #size-cells = <0>;
> + dmas = <&blsp_dma 5>, <&blsp_dma 4>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + spi_1: spi@78b6000 { /* BLSP1 QUP2 */
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x78b6000 0x600>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + dmas = <&blsp_dma 7>, <&blsp_dma 6>;
> + dma-names = "rx", "tx";
> status = "disabled";
> };
>
> @@ -184,9 +208,24 @@
> clock-names = "iface", "core";
> #address-cells = <1>;
> #size-cells = <0>;
> + dmas = <&blsp_dma 9>, <&blsp_dma 8>;
> + dma-names = "rx", "tx";
> status = "disabled";
> };
>
> + i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x78b8000 0x600>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + dmas = <&blsp_dma 11>, <&blsp_dma 10>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> cryptobam: dma@8e04000 {
> compatible = "qcom,bam-v1.7.0";
> @@ -293,6 +332,101 @@
> reg = <0x4ab000 0x4>;
> };
>
> + pcie0: pci@40000000 {
> + compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
> + reg = <0x40000000 0xf1d
> + 0x40000f20 0xa8
> + 0x80000 0x2000
> + 0x40100000 0x1000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
> + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a
> */
> + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> + clocks = <&gcc GCC_PCIE_AHB_CLK>,
> + <&gcc GCC_PCIE_AXI_M_CLK>,
> + <&gcc GCC_PCIE_AXI_S_CLK>;
> + clock-names = "aux",
> + "master_bus",
> + "slave_bus";
> +
> + resets = <&gcc PCIE_AXI_M_ARES>,
> + <&gcc PCIE_AXI_S_ARES>,
> + <&gcc PCIE_PIPE_ARES>,
> + <&gcc PCIE_AXI_M_VMIDMT_ARES>,
> + <&gcc PCIE_AXI_S_XPU_ARES>,
> + <&gcc PCIE_PARF_XPU_ARES>,
> + <&gcc PCIE_PHY_ARES>,
> + <&gcc PCIE_AXI_M_STICKY_ARES>,
> + <&gcc PCIE_PIPE_STICKY_ARES>,
> + <&gcc PCIE_PWR_ARES>,
> + <&gcc PCIE_AHB_ARES>,
> + <&gcc PCIE_PHY_AHB_ARES>;
> + reset-names = "axi_m",
> + "axi_s",
> + "pipe",
> + "axi_m_vmid",
> + "axi_s_xpu",
> + "parf",
> + "phy",
> + "axi_m_sticky",
> + "pipe_sticky",
> + "pwr",
> + "ahb",
> + "phy_ahb";
> +
> + status = "disabled";
> + };
> +
> + qpic_bam: dma@7984000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x7984000 0x1a000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QPIC_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + status = "disabled";
> + };
> +
> + nand: qpic-nand@79b0000 {
> + compatible = "qcom,ipq4019-nand";
> + reg = <0x79b0000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
> + dma-names = "tx", "rx", "cmd";
> + status = "disabled";
> +
> + nand@0 {
> + reg = <0>;
> +
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> + };
> + };
> +
> wifi0: wifi@a000000 {
> compatible = "qcom,ipq4019-wifi";
> reg = <0xa000000 0x200000>;
On 2018-03-16 15:08, Sricharan R wrote:
> The max opp frequency is 716MHZ. So update that.
>
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index e38fffa..2ee71c2 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -47,7 +47,7 @@
> 48000 1100000
> 200000 1100000
> 500000 1100000
> - 666000 1100000
> + 716000 1100000
> >;
> clock-latency = <256000>;
> };
On 2018-03-16 15:08, Sricharan R wrote:
> Adds missing memory, reserved-memory nodes.
>
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 28
> +++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> index e413b21e..ad0fbc9 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
> @@ -20,6 +20,34 @@
> model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
> compatible = "qcom,ipq4019";
>
> + memory {
> + device_type = "memory";
> + reg = <0x80000000 0x10000000>; /* 256MB */
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + rsvd1@87000000 {
> + /* Reserved for other subsystem */
> + reg = <0x87000000 0x500000>;
> + no-map;
> + };
> +
> + wifi_dump@87500000 {
> + reg = <0x87500000 0x600000>;
> + no-map;
> + };
> +
> + rsvd2@87B00000 {
> + /* Reserved for other subsystem */
> + reg = <0x87B00000 0x500000>;
> + no-map;
> + };
> + };
> +
> soc {
> rng@22000 {
> status = "ok";
On 2018-03-16 15:08, Sricharan R wrote:
> Add the common parts for the dk04 boards.
>
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 129
> ++++++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
> new file mode 100644
> index 0000000..96ce081
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
> + compatible = "qcom,ipq4019";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x80000000 0x10000000>; /* 256MB */
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + rsvd1@87000000 {
> + /* Reserved for other subsystem */
> + reg = <0x87000000 0x500000>;
> + no-map;
> + };
> +
> + wifi_dump@87500000 {
> + reg = <0x87500000 0x600000>;
> + no-map;
> + };
> +
> + rsvd2@87B00000 {
> + /* Reserved for other subsystem */
> + reg = <0x87B00000 0x500000>;
> + no-map;
> + };
> + };
> +
> + soc {
> + pinctrl@1000000 {
> + serial_0_pins: serial0_pinmux {
> + mux {
> + pins = "gpio16", "gpio17";
> + function = "blsp_uart0";
> + bias-disable;
> + };
> + };
> +
> + serial_1_pins: serial1_pinmux {
> + mux {
> + pins = "gpio8", "gpio9",
> + "gpio10", "gpio11";
> + function = "blsp_uart1";
> + bias-disable;
> + };
> + };
> +
> + spi_0_pins: spi_0_pinmux {
> + pinmux {
> + function = "blsp_spi0";
> + pins = "gpio13", "gpio14", "gpio15";
> + bias-disable;
> + };
> + pinmux_cs {
> + function = "gpio";
> + pins = "gpio12";
> + bias-disable;
> + output-high;
> + };
> + };
> +
> + i2c_0_pins: i2c_0_pinmux {
> + mux {
> + pins = "gpio20", "gpio21";
> + function = "blsp_i2c0";
> + bias-disable;
> + };
> + };
> +
> + nand_pins: nand_pins {
> + mux {
> + pins = "gpio53", "gpio55", "gpio56",
> + "gpio57", "gpio58", "gpio59",
> + "gpio60", "gpio62", "gpio63",
> + "gpio64", "gpio65", "gpio66",
> + "gpio67", "gpio68", "gpio69";
> + function = "qpic";
> + };
> + };
> + };
> +
> + serial@78af000 {
> + pinctrl-0 = <&serial_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + serial@78b0000 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + blsp_dma: dma@7884000 {
> + status = "ok";
> + };
> +
> + spi_0: spi@78b5000 { /* BLSP1 QUP1 */
> + pinctrl-0 = <&spi_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + cs-gpios = <&tlmm 12 0>;
> +
> + m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "n25q128a11";
> + spi-max-frequency = <24000000>;
> + };
> + };
> +
> + pcie0: pci@40000000 {
> + status = "ok";
> + perst-gpio = <&tlmm 38 0x1>;
> + };
> + };
> +};
On 2018-03-16 15:08, Sricharan R wrote:
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 20
> ++++++++++++++++++++
> 2 files changed, 21 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b59e99b..4f209fb 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -747,6 +747,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-apq8084-ifc6540.dtb \
> qcom-apq8084-mtp.dtb \
> qcom-ipq4019-ap.dk01.1-c1.dtb \
> + qcom-ipq4019-ap.dk04.1-c1.dtb \
> qcom-ipq8064-ap148.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
> new file mode 100644
> index 0000000..871ac3f
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019-ap.dk04.1.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
> +
> + soc {
> + qpic_bam: dma@7984000 {
> + status = "ok";
> + };
> +
> + nand: qpic-nand@79b0000 {
> + pinctrl-0 = <&nand_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> + };
> +};
On 2018-03-16 15:08, Sricharan R wrote:
> Add the common data for all dk07 based boards.
>
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 83
> +++++++++++++++++++++++++++
> 1 file changed, 83 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
> new file mode 100644
> index 0000000..37a2ea8
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
> + compatible = "qcom,ipq4019";
> +
> + memory {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>; /* 512MB */
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + rsvd1@87000000 {
> + /* Reserved for other subsystem */
> + reg = <0x87000000 0x500000>;
> + no-map;
> + };
> +
> + wifi_dump@87500000 {
> + reg = <0x87500000 0x600000>;
> + no-map;
> + };
> +
> + rsvd2@87B00000 {
> + /* Reserved for other subsystem */
> + reg = <0x87B00000 0x500000>;
> + no-map;
> + };
> + };
> +
> + soc {
> + pinctrl@1000000 {
> + serial_0_pins: serial0_pinmux {
> + mux {
> + pins = "gpio16", "gpio17";
> + function = "blsp_uart0";
> + bias-disable;
> + };
> + };
> +
> + i2c_0_pins: i2c_0_pinmux {
> + mux {
> + pins = "gpio20", "gpio21";
> + function = "blsp_i2c0";
> + bias-disable;
> + };
> + };
> + };
> +
> + serial@78af000 {
> + pinctrl-0 = <&serial_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + blsp_dma: dma@7884000 {
> + status = "ok";
> + };
> +
> + i2c_0: i2c@78b7000 { /* BLSP1 QUP2 */
> + pinctrl-0 = <&i2c_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + qpic_bam: dma@7984000 {
> + status = "ok";
> + };
> +
> + nand: qpic-nand@79b0000 {
> + status = "ok";
> + };
> + };
> +};
On 2018-03-16 15:08, Sricharan R wrote:
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 8 ++++++++
> 2 files changed, 9 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 4f209fb..b71487a 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -748,6 +748,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-apq8084-mtp.dtb \
> qcom-ipq4019-ap.dk01.1-c1.dtb \
> qcom-ipq4019-ap.dk04.1-c1.dtb \
> + qcom-ipq4019-ap.dk04.1-c3.dtb \
> qcom-ipq8064-ap148.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
> new file mode 100644
> index 0000000..0843523
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019-ap.dk04.1.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
> +};
On 2018-03-16 15:08, Sricharan R wrote:
> Signed-off-by: Sricharan R <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65
> +++++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b71487a..8c93fd0 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-ipq4019-ap.dk01.1-c1.dtb \
> qcom-ipq4019-ap.dk04.1-c1.dtb \
> qcom-ipq4019-ap.dk04.1-c3.dtb \
> + qcom-ipq4019-ap.dk07.1-c1.dtb \
> qcom-ipq8064-ap148.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
> new file mode 100644
> index 0000000..4562f7f
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
s/IPQ40xx/IPQ4019
with that.
Reviewed-by: Abhishek Sahu <[email protected]>
> +
> + soc {
> + pcie0: pci@40000000 {
> + status = "ok";
> + perst-gpio = <&tlmm 38 0x1>;
> + };
> +
> + spi_1: spi@78b6000 { /* BLSP1 QUP2 */
> + status = "ok";
> + };
> +
> + pinctrl@1000000 {
> + serial_1_pins: serial1_pinmux {
> + mux {
> + pins = "gpio8", "gpio9",
> + "gpio10", "gpio11";
> + function = "blsp_uart1";
> + bias-disable;
> + };
> + };
> +
> + spi_0_pins: spi_0_pinmux {
> + pinmux {
> + function = "blsp_spi0";
> + pins = "gpio13", "gpio14", "gpio15";
> + bias-disable;
> + };
> + pinmux_cs {
> + function = "gpio";
> + pins = "gpio12";
> + bias-disable;
> + output-high;
> + };
> + };
> + };
> +
> + serial@78b0000 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + spi_0: spi@78b5000 { /* BLSP1 QUP1 */
> + pinctrl-0 = <&spi_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + cs-gpios = <&tlmm 12 0>;
> +
> + m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + compatible = "n25q128a11";
> + spi-max-frequency = <24000000>;
> + };
> + };
> + };
> +};
On 2018-03-16 15:08, Sricharan R wrote:
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 26
> +++++++++++++++++++++++++
> 2 files changed, 27 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 8c93fd0..0844087 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -750,6 +750,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-ipq4019-ap.dk04.1-c1.dtb \
> qcom-ipq4019-ap.dk04.1-c3.dtb \
> qcom-ipq4019-ap.dk07.1-c1.dtb \
> + qcom-ipq4019-ap.dk07.1-c2.dtb \
> qcom-ipq8064-ap148.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
> new file mode 100644
> index 0000000..c1e909c
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
> +
> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1-C2";
> +
> + soc {
> + pinctrl@1000000 {
> + serial_1_pins: serial1_pinmux {
> + mux {
> + pins = "gpio8", "gpio9";
> + function = "blsp_uart1";
> + bias-disable;
> + };
> + };
> + };
> +
> + serial@78b0000 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> + };
> +};
On 2018-03-16 15:08, Sricharan R wrote:
> Add serial, i2c, bam, spi, qpic peripheral nodes.
>
> Signed-off-by: Sricharan R <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105
> ++++++++++++++++++++++++++++++++++
> 1 file changed, 105 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 2bc5dec..806fc56 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -124,6 +124,111 @@
> clock-names = "core", "iface";
> status = "disabled";
> };
> +
> + blsp_dma: dma@7884000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x07884000 0x2b000>;
we can remove leading zero. s/0x07884000/0x7884000
> + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + };
> +
> + serial_blsp0: serial@78af000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x78af000 0x200>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + serial_blsp2: serial@78B1000 {
For maintaining uniformity, we can have all address in lower case
s/78B1000/78b1000
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x78B1000 0x200>;
same thing, here also
> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 4>,
> + <&blsp_dma 5>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + spi_0: spi@78b5000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x78b5000 0x600>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + spi-max-frequency = <50000000>;
> + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + dmas = <&blsp_dma 12>, <&blsp_dma 13>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2c_0: i2c@78b6000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x78b6000 0x600>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <400000>;
remove one extra space. clock-frequency = <400000>;
> + dmas = <&blsp_dma 15>, <&blsp_dma 14>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + i2c_1: i2c@78b7000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x78b7000 0x600>;
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <100000>;
remove one extra space. clock-frequency = <100000>;
with above changes.
Reviewed-by: Abhishek Sahu <[email protected]>
> + dmas = <&blsp_dma 17>, <&blsp_dma 16>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + qpic_bam: dma@7984000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x7984000 0x1a000>;
> + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + status = "disabled";
> + };
> +
> + qpic_nand: nand@79b0000 {
> + compatible = "qcom,ipq8074-nand";
> + reg = <0x79b0000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
> + dma-names = "tx", "rx", "cmd";
> + status = "disabled";
> + };
> };
>
> cpus {
On 2018-03-16 15:08, Sricharan R wrote:
> Signed-off-by: Sricharan R <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103
> ++++++++++++++++++++++++++++++
> 1 file changed, 103 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> index 6a838b5..81dff867 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
> @@ -21,6 +21,7 @@
>
> aliases {
> serial0 = &blsp1_uart5;
> + serial1 = &serial_blsp2;
> };
>
> chosen {
> @@ -41,6 +42,47 @@
> bias-disable;
> };
> };
> +
> + i2c_0_pins: i2c_0_pinmux {
> + mux {
> + pins = "gpio42", "gpio43";
> + function = "blsp1_i2c";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + spi_0_pins: spi_0_pins {
> + mux {
> + pins = "gpio38", "gpio39", "gpio40", "gpio41";
> + function = "blsp0_spi";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + hsuart_pins: hsuart_pins {
> + mux {
> + pins = "gpio46", "gpio47", "gpio48", "gpio49";
> + function = "blsp2_uart";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + qpic_pins: qpic_pins {
> + mux {
> + pins = "gpio1", "gpio3", "gpio4",
> + "gpio5", "gpio6", "gpio7",
> + "gpio8", "gpio10", "gpio11",
> + "gpio12", "gpio13", "gpio14",
> + "gpio15", "gpio16", "gpio17";
> + function = "qpic";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> };
>
> serial@78b3000 {
> @@ -48,5 +90,66 @@
> pinctrl-names = "default";
> status = "ok";
> };
> +
> + spi@78b5000 {
> + pinctrl-0 = <&spi_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +
> + m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "n25q128a11", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <50000000>;
> + };
> + };
> +
> + serial@78B1000 {
s/78B1000/78b1000
With that,
Reviewed-by: Abhishek Sahu <[email protected]>
> + pinctrl-0 = <&hsuart_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + i2c_0@78b6000 {
> + pinctrl-0 = <&i2c_0_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> + };
> +
> + dma@7984000 {
> + status = "ok";
> + };
> +
> + nand@79b0000 {
> + pinctrl-0 = <&qpic_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +
> + nand@0 {
> + reg = <0>;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> + };
> + };
> +
> + phy@86000 {
> + status = "ok";
> + };
> +
> + phy@8e000 {
> + status = "ok";
> + };
> +
> + pci@20000000 {
> + status = "ok";
> + perst-gpio = <&tlmm 58 0x1>;
> + };
> +
> + pci@10000000 {
> + status = "ok";
> + perst-gpio = <&tlmm 61 0x1>;
> + };
> };
> };
On 2018-03-16 15:08, Sricharan R wrote:
> The driver/phy support for ipq8074 is available now.
> So enabling the nodes in DT.
>
> Signed-off-by: Sricharan R <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157
> +++++++++++++++++++++++++++++++++-
> 1 file changed, 156 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> index 806fc56..7562650 100644
> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
> @@ -24,7 +24,7 @@
> ranges = <0 0 0 0xffffffff>;
> compatible = "simple-bus";
>
> - pinctrl@1000000 {
> + tlmm: pinctrl@1000000 {
> compatible = "qcom,ipq8074-pinctrl";
> reg = <0x1000000 0x300000>;
> interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> @@ -229,6 +229,161 @@
> dma-names = "tx", "rx", "cmd";
> status = "disabled";
> };
> +
> + pcie_phy0: phy@86000 {
> + compatible = "qcom,ipq8074-qmp-pcie-phy";
> + reg = <0x86000 0x1000>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
> + clock-names = "pipe_clk";
> + clock-output-names = "pcie20_phy0_pipe_clk";
> +
> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> + };
> +
> + pcie0: pci@20000000 {
> + compatible = "qcom,pcie-ipq8074";
> + reg = <0x20000000 0xf1d
> + 0x20000F20 0xa8
s/0x20000F20/0x20000f20
> + 0x80000 0x2000
> + 0x20100000 0x1000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + phys = <&pcie_phy0>;
> + phy-names = "pciephy";
> +
> + ranges = <0x81000000 0 0x20200000 0x20200000
> + 0 0x00100000 /* downstream I/O */
we can remove trailing zeros from address.
s/0x00100000/0x100000
> + 0x82000000 0 0x20300000 0x20300000
> + 0 0x00d00000>; /* non-prefetchable memory */
s/0x00d00000/0xd00000
Same changes are for PCIE1 also.
With that.
Reviewed-by: Abhishek Sahu <[email protected]>
> +
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 75
> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 78
> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 79
> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 83
> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
> + <&gcc GCC_PCIE0_AXI_M_CLK>,
> + <&gcc GCC_PCIE0_AXI_S_CLK>,
> + <&gcc GCC_PCIE0_AHB_CLK>,
> + <&gcc GCC_PCIE0_AUX_CLK>;
> +
> + clock-names = "iface",
> + "axi_m",
> + "axi_s",
> + "ahb",
> + "aux";
> + resets = <&gcc GCC_PCIE0_PIPE_ARES>,
> + <&gcc GCC_PCIE0_SLEEP_ARES>,
> + <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
> + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
> + <&gcc GCC_PCIE0_AHB_ARES>,
> + <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
> + reset-names = "pipe",
> + "sleep",
> + "sticky",
> + "axi_m",
> + "axi_s",
> + "ahb",
> + "axi_m_sticky";
> + status = "disabled";
> + };
> +
> + pcie_phy1: phy@8e000 {
> + compatible = "qcom,ipq8074-qmp-pcie-phy";
> + reg = <0x8e000 0x1000>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
> + clock-names = "pipe_clk";
> + clock-output-names = "pcie20_phy1_pipe_clk";
> +
> + resets = <&gcc GCC_PCIE1_PHY_BCR>,
> + <&gcc GCC_PCIE1PHY_PHY_BCR>;
> + reset-names = "phy",
> + "common";
> + status = "disabled";
> + };
> +
> + pcie1: pci@10000000 {
> + compatible = "qcom,pcie-ipq8074";
> + reg = <0x10000000 0xf1d
> + 0x10000F20 0xa8
> + 0x88000 0x2000
> + 0x10100000 0x1000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + phys = <&pcie_phy1>;
> + phy-names = "pciephy";
> +
> + ranges = <0x81000000 0 0x10200000 0x10200000
> + 0 0x00100000 /* downstream I/O */
> + 0x82000000 0 0x10300000 0x10300000
> + 0 0x00d00000>; /* non-prefetchable memory */
> +
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 142
> + IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> + <0 0 0 2 &intc 0 143
> + IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 144
> + IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 145
> + IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> + clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
> + <&gcc GCC_PCIE1_AXI_M_CLK>,
> + <&gcc GCC_PCIE1_AXI_S_CLK>,
> + <&gcc GCC_PCIE1_AHB_CLK>,
> + <&gcc GCC_PCIE1_AUX_CLK>;
> + clock-names = "iface",
> + "axi_m",
> + "axi_s",
> + "ahb",
> + "aux";
> + resets = <&gcc GCC_PCIE1_PIPE_ARES>,
> + <&gcc GCC_PCIE1_SLEEP_ARES>,
> + <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
> + <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
> + <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
> + <&gcc GCC_PCIE1_AHB_ARES>,
> + <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
> + reset-names = "pipe",
> + "sleep",
> + "sticky",
> + "axi_m",
> + "axi_s",
> + "ahb",
> + "axi_m_sticky";
> + status = "disabled";
> + };
> };
>
> cpus {
On 2018-03-16 15:08, Sricharan R wrote:
> Now with the driver updates for some peripherals being there,
> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
> peripheral support.
>
> Signed-off-by: Sricharan R <[email protected]>
Reviewed-by: Abhishek Sahu <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 134
> ++++++++++++++++++++++++++++++++++++
> 1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index 10d112a..e38fffa 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -25,7 +25,9 @@
>
> aliases {
> spi0 = &spi_0;
> + spi1 = &spi_1;
> i2c0 = &i2c_0;
> + i2c1 = &i2c_1;
> };
>
> cpus {
> @@ -104,6 +106,12 @@
> };
> };
>
> + firmware {
> + scm {
> + compatible = "qcom,scm-ipq4019";
> + };
> + };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts = <1 2 0xf08>,
> @@ -172,6 +180,22 @@
> clock-names = "core", "iface";
> #address-cells = <1>;
> #size-cells = <0>;
> + dmas = <&blsp_dma 5>, <&blsp_dma 4>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
> +
> + spi_1: spi@78b6000 { /* BLSP1 QUP2 */
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0x78b6000 0x600>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + dmas = <&blsp_dma 7>, <&blsp_dma 6>;
> + dma-names = "rx", "tx";
> status = "disabled";
> };
>
> @@ -184,9 +208,24 @@
> clock-names = "iface", "core";
> #address-cells = <1>;
> #size-cells = <0>;
> + dmas = <&blsp_dma 9>, <&blsp_dma 8>;
> + dma-names = "rx", "tx";
> status = "disabled";
> };
>
> + i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0x78b8000 0x600>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + dmas = <&blsp_dma 11>, <&blsp_dma 10>;
> + dma-names = "rx", "tx";
> + status = "disabled";
> + };
>
> cryptobam: dma@8e04000 {
> compatible = "qcom,bam-v1.7.0";
> @@ -293,6 +332,101 @@
> reg = <0x4ab000 0x4>;
> };
>
> + pcie0: pci@40000000 {
> + compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
> + reg = <0x40000000 0xf1d
> + 0x40000f20 0xa8
> + 0x80000 0x2000
> + 0x40100000 0x1000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
> + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a
> */
> + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> + clocks = <&gcc GCC_PCIE_AHB_CLK>,
> + <&gcc GCC_PCIE_AXI_M_CLK>,
> + <&gcc GCC_PCIE_AXI_S_CLK>;
> + clock-names = "aux",
> + "master_bus",
> + "slave_bus";
> +
> + resets = <&gcc PCIE_AXI_M_ARES>,
> + <&gcc PCIE_AXI_S_ARES>,
> + <&gcc PCIE_PIPE_ARES>,
> + <&gcc PCIE_AXI_M_VMIDMT_ARES>,
> + <&gcc PCIE_AXI_S_XPU_ARES>,
> + <&gcc PCIE_PARF_XPU_ARES>,
> + <&gcc PCIE_PHY_ARES>,
> + <&gcc PCIE_AXI_M_STICKY_ARES>,
> + <&gcc PCIE_PIPE_STICKY_ARES>,
> + <&gcc PCIE_PWR_ARES>,
> + <&gcc PCIE_AHB_ARES>,
> + <&gcc PCIE_PHY_AHB_ARES>;
> + reset-names = "axi_m",
> + "axi_s",
> + "pipe",
> + "axi_m_vmid",
> + "axi_s_xpu",
> + "parf",
> + "phy",
> + "axi_m_sticky",
> + "pipe_sticky",
> + "pwr",
> + "ahb",
> + "phy_ahb";
> +
> + status = "disabled";
> + };
> +
> + qpic_bam: dma@7984000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0x7984000 0x1a000>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_QPIC_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + status = "disabled";
> + };
> +
> + nand: qpic-nand@79b0000 {
> + compatible = "qcom,ipq4019-nand";
> + reg = <0x79b0000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&gcc GCC_QPIC_CLK>,
> + <&gcc GCC_QPIC_AHB_CLK>;
> + clock-names = "core", "aon";
> +
> + dmas = <&qpic_bam 0>,
> + <&qpic_bam 1>,
> + <&qpic_bam 2>;
> + dma-names = "tx", "rx", "cmd";
> + status = "disabled";
> +
> + nand@0 {
> + reg = <0>;
> +
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> + nand-bus-width = <8>;
> + };
> + };
> +
> wifi0: wifi@a000000 {
> compatible = "qcom,ipq4019-wifi";
> reg = <0xa000000 0x200000>;
On 16/03/18 09:38, Sricharan R wrote:
> Now with the driver updates for some peripherals being there,
> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
> peripheral support.
>
> Signed-off-by: Sricharan R <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 134 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index 10d112a..e38fffa 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -25,7 +25,9 @@
[...]
> + pcie0: pci@40000000 {
> + compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
> + reg = <0x40000000 0xf1d
> + 0x40000f20 0xa8
> + 0x80000 0x2000
> + 0x40100000 0x1000>;
> + reg-names = "dbi", "elbi", "parf", "config";
> + device_type = "pci";
> + linux,pci-domain = <0>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
> + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
There is no such thing as IRQ_TYPE_NONE. Please replace this with the
actual trigger information.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
Hi Abhishek,
On 3/16/2018 4:50 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> The driver/phy support for ipq8074 is available now.
>> So enabling the nodes in DT.
>>
>> Signed-off-by: Sricharan R <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
>> 1 file changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 806fc56..7562650 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -24,7 +24,7 @@
>> ranges = <0 0 0 0xffffffff>;
>> compatible = "simple-bus";
>>
>> - pinctrl@1000000 {
>> + tlmm: pinctrl@1000000 {
>> compatible = "qcom,ipq8074-pinctrl";
>> reg = <0x1000000 0x300000>;
>> interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -229,6 +229,161 @@
>> dma-names = "tx", "rx", "cmd";
>> status = "disabled";
>> };
>> +
>> + pcie_phy0: phy@86000 {
>> + compatible = "qcom,ipq8074-qmp-pcie-phy";
>> + reg = <0x86000 0x1000>;
>> + #phy-cells = <0>;
>> + clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
>> + clock-names = "pipe_clk";
>> + clock-output-names = "pcie20_phy0_pipe_clk";
>> +
>> + resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> + <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> + reset-names = "phy",
>> + "common";
>> + status = "disabled";
>> + };
>> +
>> + pcie0: pci@20000000 {
>> + compatible = "qcom,pcie-ipq8074";
>> + reg = <0x20000000 0xf1d
>> + 0x20000F20 0xa8
>
> s/0x20000F20/0x20000f20
ok
>
>> + 0x80000 0x2000
>> + 0x20100000 0x1000>;
>> + reg-names = "dbi", "elbi", "parf", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <0>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + phys = <&pcie_phy0>;
>> + phy-names = "pciephy";
>> +
>> + ranges = <0x81000000 0 0x20200000 0x20200000
>> + 0 0x00100000 /* downstream I/O */
>
> we can remove trailing zeros from address.
> s/0x00100000/0x100000
>
>> + 0x82000000 0 0x20300000 0x20300000
>> + 0 0x00d00000>; /* non-prefetchable memory */
>
> s/0x00d00000/0xd00000
>
> Same changes are for PCIE1 also.
ok
>
> With that.
>
> Reviewed-by: Abhishek Sahu <[email protected]>
Thanks.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Hi Marc,
On 3/16/2018 5:47 PM, Marc Zyngier wrote:
> On 16/03/18 09:38, Sricharan R wrote:
>> Now with the driver updates for some peripherals being there,
>> add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
>> peripheral support.
>>
>> Signed-off-by: Sricharan R <[email protected]>
>> ---
>> arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 134 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> index 10d112a..e38fffa 100644
>> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
>> @@ -25,7 +25,9 @@
>
> [...]
>
>> + pcie0: pci@40000000 {
>> + compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
>> + reg = <0x40000000 0xf1d
>> + 0x40000f20 0xa8
>> + 0x80000 0x2000
>> + 0x40100000 0x1000>;
>> + reg-names = "dbi", "elbi", "parf", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <0>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <1>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
>> + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
>> +
>> + interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
>
> There is no such thing as IRQ_TYPE_NONE. Please replace this with the
> actual trigger information.
ok, will update this.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Hi Abhishek,
On 3/16/2018 4:27 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 103 ++++++++++++++++++++++++++++++
>> 1 file changed, 103 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> index 6a838b5..81dff867 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
>> @@ -21,6 +21,7 @@
>>
>> aliases {
>> serial0 = &blsp1_uart5;
>> + serial1 = &serial_blsp2;
>> };
>>
>> chosen {
>> @@ -41,6 +42,47 @@
>> bias-disable;
>> };
>> };
>> +
>> + i2c_0_pins: i2c_0_pinmux {
>> + mux {
>> + pins = "gpio42", "gpio43";
>> + function = "blsp1_i2c";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> + };
>> +
>> + spi_0_pins: spi_0_pins {
>> + mux {
>> + pins = "gpio38", "gpio39", "gpio40", "gpio41";
>> + function = "blsp0_spi";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> + };
>> +
>> + hsuart_pins: hsuart_pins {
>> + mux {
>> + pins = "gpio46", "gpio47", "gpio48", "gpio49";
>> + function = "blsp2_uart";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> + };
>> +
>> + qpic_pins: qpic_pins {
>> + mux {
>> + pins = "gpio1", "gpio3", "gpio4",
>> + "gpio5", "gpio6", "gpio7",
>> + "gpio8", "gpio10", "gpio11",
>> + "gpio12", "gpio13", "gpio14",
>> + "gpio15", "gpio16", "gpio17";
>> + function = "qpic";
>> + drive-strength = <8>;
>> + bias-disable;
>> + };
>> + };
>> +
>> };
>>
>> serial@78b3000 {
>> @@ -48,5 +90,66 @@
>> pinctrl-names = "default";
>> status = "ok";
>> };
>> +
>> + spi@78b5000 {
>> + pinctrl-0 = <&spi_0_pins>;
>> + pinctrl-names = "default";
>> + status = "ok";
>> +
>> + m25p80@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "n25q128a11", "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <50000000>;
>> + };
>> + };
>> +
>> + serial@78B1000 {
>
> s/78B1000/78b1000
>
> With that,
> Reviewed-by: Abhishek Sahu <[email protected]>
>
ok, Thanks.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On 3/16/2018 4:17 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Add serial, i2c, bam, spi, qpic peripheral nodes.
>>
>> Signed-off-by: Sricharan R <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq8074.dtsi | 105 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 105 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> index 2bc5dec..806fc56 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
>> @@ -124,6 +124,111 @@
>> clock-names = "core", "iface";
>> status = "disabled";
>> };
>> +
>> + blsp_dma: dma@7884000 {
>> + compatible = "qcom,bam-v1.7.0";
>> + reg = <0x07884000 0x2b000>;
>
> we can remove leading zero. s/0x07884000/0x7884000
>
>> + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "bam_clk";
>> + #dma-cells = <1>;
>> + qcom,ee = <0>;
>> + };
>> +
>> + serial_blsp0: serial@78af000 {
>> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> + reg = <0x78af000 0x200>;
>> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
>> + <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "core", "iface";
>> + status = "disabled";
>> + };
>> +
>> + serial_blsp2: serial@78B1000 {
>
> For maintaining uniformity, we can have all address in lower case
> s/78B1000/78b1000
>
>> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> + reg = <0x78B1000 0x200>;
>
> same thing, here also
>
>> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> + <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "core", "iface";
>> + dmas = <&blsp_dma 4>,
>> + <&blsp_dma 5>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + spi_0: spi@78b5000 {
>> + compatible = "qcom,spi-qup-v2.2.1";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x78b5000 0x600>;
>> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
>> + spi-max-frequency = <50000000>;
>> + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
>> + <&gcc GCC_BLSP1_AHB_CLK>;
>> + clock-names = "core", "iface";
>> + dmas = <&blsp_dma 12>, <&blsp_dma 13>;
>> + dma-names = "tx", "rx";
>> + status = "disabled";
>> + };
>> +
>> + i2c_0: i2c@78b6000 {
>> + compatible = "qcom,i2c-qup-v2.2.1";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x78b6000 0x600>;
>> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
>> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
>> + clock-names = "iface", "core";
>> + clock-frequency = <400000>;
>
> remove one extra space. clock-frequency = <400000>;
>
>> + dmas = <&blsp_dma 15>, <&blsp_dma 14>;
>> + dma-names = "rx", "tx";
>> + status = "disabled";
>> + };
>> +
>> + i2c_1: i2c@78b7000 {
>> + compatible = "qcom,i2c-qup-v2.2.1";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x78b7000 0x600>;
>> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
>> + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
>> + clock-names = "iface", "core";
>> + clock-frequency = <100000>;
>
> remove one extra space. clock-frequency = <100000>;
>
> with above changes.
>
> Reviewed-by: Abhishek Sahu <[email protected]>
>
Sure, will take care of all the above. Thanks
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On 3/16/2018 3:55 PM, Abhishek Sahu wrote:
> On 2018-03-16 15:08, Sricharan R wrote:
>> Signed-off-by: Sricharan R <[email protected]>
>> ---
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 65 +++++++++++++++++++++++++
>> 2 files changed, 66 insertions(+)
>> create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index b71487a..8c93fd0 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -749,6 +749,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
>> qcom-ipq4019-ap.dk01.1-c1.dtb \
>> qcom-ipq4019-ap.dk04.1-c1.dtb \
>> qcom-ipq4019-ap.dk04.1-c3.dtb \
>> + qcom-ipq4019-ap.dk07.1-c1.dtb \
>> qcom-ipq8064-ap148.dtb \
>> qcom-msm8660-surf.dtb \
>> qcom-msm8960-cdp.dtb \
>> diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> new file mode 100644
>> index 0000000..4562f7f
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
>> @@ -0,0 +1,65 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> +
>> +#include "qcom-ipq4019-ap.dk07.1.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK07.1-C1";
>
> s/IPQ40xx/IPQ4019
>
> with that.
>
> Reviewed-by: Abhishek Sahu <[email protected]>
Thanks, will update
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation