This patch extends Exynos SROM controller driver with ability to configure
controller outputs and enables SMSC9115 Ethernet chip on SMDK5410 board,
which is connected via SROMc bank #3.
With this patchset, support for the whole existing SMDK range can be added.
Actually, only bank number is different.
This patchset also depends on Exynos 5410 pinctrl support, introduced by
patches 0003 and 0004 from this set:
[PATCH v4 0/5] ARM: EXYNOS: ODROID-XU DT and LEDs
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330862.html
Pinctrl support is necessary in order to correctly configure
multifunctional pins of the Exynos chip.
v6 => v7:
- Fixed stupid error in Tacc description in the documentation
v5 => v6:
- Even more improvements to the documentation, fixed some errors and typos.
- Separated adding bus ranges from generic SROMc support
- Some stuff renamed for even better code readability
- Stylistic cleanups in the DTS (everything in alphabetic order, use named
constant name for interrupt config byte)
v4 => v5:
- Some cosmetic changes in the dtsi ("compatible" goes first)
- Use correctly specified ranges for the SROMc node
- Reuse existing properties where possible ("reg" for bank# and
"reg-io-width" for data width)
- Separated page-mode property from timings array
- More improvements to the documentation
v3 => v4:
- Devices are now added as subnodes, with additional properties. This allows
to cleary specify dependency. If configuration fails, error will be reported
and child devices will not be probed.
- These additional properties now have "samsung,srom-XXX" format
- Fixed code style, now better understood.
v2 => v3:
- Fixed up SROMc region size in the device tree
- Reordered patches, documentation goes first now
v1 => v2:
- Fixed some typos and bad labels in device tree
- Improved documentation
Pavel Fedin (4):
Documentation: dt-bindings: Describe SROMc configuration
ARM: dts: Add SROMc to Exynos 5410
drivers: exynos-srom: Add support for bank configuration
ARM: dts: Add Ethernet chip to SMDK5410
.../bindings/arm/samsung/exynos-srom.txt | 71 +++++++++++++++++++++-
arch/arm/boot/dts/exynos5410-smdk5410.dts | 41 +++++++++++++
arch/arm/boot/dts/exynos5410.dtsi | 11 ++++
arch/arm/mach-exynos/Kconfig | 2 +-
drivers/soc/samsung/Kconfig | 2 +-
drivers/soc/samsung/exynos-srom.c | 61 ++++++++++++++++++-
6 files changed, 182 insertions(+), 6 deletions(-)
--
2.4.4
Add documentation for new subnode properties, allowing bank configuration.
Based on u-boot implementation, but heavily reworked.
Also, fix size of SROMc mapping in the example.
Signed-off-by: Pavel Fedin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/arm/samsung/exynos-srom.txt | 71 +++++++++++++++++++++-
1 file changed, 69 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
index 33886d5..3ff2950 100644
--- a/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
@@ -5,8 +5,75 @@ Required properties:
- reg: offset and length of the register set
-Example:
+Optional properties:
+The SROM controller can be used to attach external peripherals. In this case
+extra properties, describing the bus behind it, should be specified as below:
+
+- #address-cells: Must be set to 2 to allow memory address translation
+
+- #size-cells: Must be set to 1 to allow CS address passing
+
+- ranges: Must be set up to reflect the memory layout with four integer values
+ per bank:
+ <bank-number> 0 <physical address of bank> <size>
+
+Sub-nodes:
+The actual device nodes should be added as subnodes to the SROMc node. These
+subnodes, except regular device specification, should contain the following
+properties, describing configuration of the relevant SROM bank:
+
+Required properties:
+- reg: bank number, base address (relative to start of the bank) and size of
+ the memory mapped for the device. Note that base address will be
+ typically 0 as this is the start of the bank.
+
+- samsung,srom-timing : array of 6 integers, specifying bank timings in the
+ following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
+ Each value is specified in cycles and has the following
+ meaning and valid range:
+ Tacp : Page mode access cycle at Page mode (0 - 15)
+ Tcah : Address holding time after CSn (0 - 15)
+ Tcoh : Chip selection hold on OEn (0 - 15)
+ Tacc : Access cycle (0 - 31, the actual time is N + 1)
+ Tcos : Chip selection set-up before OEn (0 - 15)
+ Tacs : Address set-up before CSn (0 - 15)
+
+Optional properties:
+- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used.
+
+- samsung,srom-page-mode : page mode configuration for the bank:
+ 0 - normal (one data)
+ 1 - four data
+ If omitted, default of 0 is used.
+
+Example: basic definition, no banks are configured
+ sromc@12570000 {
+ compatible = "samsung,exynos-srom";
+ reg = <0x12570000 0x14>;
+ };
+
+Example: SROMc with SMSC911x ethernet chip on bank 3
sromc@12570000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x04000000 0x20000 // Bank0
+ 1 0 0x05000000 0x20000 // Bank1
+ 2 0 0x06000000 0x20000 // Bank2
+ 3 0 0x07000000 0x20000>; // Bank3
+
compatible = "samsung,exynos-srom";
- reg = <0x12570000 0x10>;
+ reg = <0x12570000 0x14>;
+
+ ethernet@3 {
+ compatible = "smsc,lan9115";
+ reg = <3 0 0x10000>; // Bank 3, offset = 0
+ phy-mode = "mii";
+ interrupt-parent = <&gpx0>;
+ interrupts = <5 8>;
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
+ smsc,force-internal-phy;
+
+ samsung,srom-config = <1 9 12 1 9 1 1>;
+ };
};
--
2.4.4
This machine uses own SoC device tree file, add missing part.
Signed-off-by: Pavel Fedin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos5410.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 4603356..e2b58f8 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -101,6 +101,11 @@
reg = <0x10000000 0x100>;
};
+ sromc: sromc@12250000 {
+ compatible = "samsung,exynos-srom";
+ reg = <0x12250000 0x14>;
+ };
+
pmu_system_controller: system-controller@10040000 {
compatible = "samsung,exynos5410-pmu", "syscon";
reg = <0x10040000 0x5000>;
--
2.4.4
Implement handling properties in subnodes and adding child devices to the
system. Child devices will not be added if configuration fails.
Since the driver now does more than suspend-resume support, dependency on
CONFIG_PM is removed.
Signed-off-by: Pavel Fedin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/mach-exynos/Kconfig | 2 +-
drivers/soc/samsung/Kconfig | 2 +-
drivers/soc/samsung/exynos-srom.c | 61 +++++++++++++++++++++++++++++++++++++--
3 files changed, 61 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 83c85f5..c22dc42 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -16,7 +16,7 @@ menuconfig ARCH_EXYNOS
select ARM_GIC
select COMMON_CLK_SAMSUNG
select EXYNOS_THERMAL
- select EXYNOS_SROM if PM
+ select EXYNOS_SROM
select HAVE_ARM_SCU if SMP
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
index 2833b5b..ea4bc2a 100644
--- a/drivers/soc/samsung/Kconfig
+++ b/drivers/soc/samsung/Kconfig
@@ -8,6 +8,6 @@ config SOC_SAMSUNG
config EXYNOS_SROM
bool
- depends on ARM && ARCH_EXYNOS && PM
+ depends on ARM && ARCH_EXYNOS
endmenu
diff --git a/drivers/soc/samsung/exynos-srom.c b/drivers/soc/samsung/exynos-srom.c
index 57a232d..a4cf547 100644
--- a/drivers/soc/samsung/exynos-srom.c
+++ b/drivers/soc/samsung/exynos-srom.c
@@ -14,6 +14,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -67,11 +68,51 @@ static struct exynos_srom_reg_dump *exynos_srom_alloc_reg_dump(
return rd;
}
+static int exynos_srom_configure_bank(struct exynos_srom *srom,
+ struct device_node *np)
+{
+ u32 bank, width, pmc;
+ u32 timing[6];
+ u32 cs, bw;
+
+ if (of_property_read_u32(np, "reg", &bank))
+ return -EINVAL;
+ if (of_property_read_u32(np, "reg-io-width", &width))
+ width = 1;
+ if (of_property_read_u32(np, "samsung,srom-page-mode", &pmc))
+ pmc = 0;
+ if (of_property_read_u32_array(np, "samsung,srom-timing", timing,
+ ARRAY_SIZE(timing)))
+ return -EINVAL;
+
+ bank *= 4; /* Convert bank into shift/offset */
+
+ cs = 1 << EXYNOS_SROM_BW__BYTEENABLE__SHIFT;
+ if (width == 2)
+ cs |= 1 << EXYNOS_SROM_BW__DATAWIDTH__SHIFT;
+
+ bw = __raw_readl(srom->reg_base + EXYNOS_SROM_BW);
+ bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
+ __raw_writel(bw, srom->reg_base + EXYNOS_SROM_BW);
+
+ __raw_writel((pmc << EXYNOS_SROM_BCX__PMC__SHIFT) |
+ (timing[0] << EXYNOS_SROM_BCX__TACP__SHIFT) |
+ (timing[1] << EXYNOS_SROM_BCX__TCAH__SHIFT) |
+ (timing[2] << EXYNOS_SROM_BCX__TCOH__SHIFT) |
+ (timing[3] << EXYNOS_SROM_BCX__TACC__SHIFT) |
+ (timing[4] << EXYNOS_SROM_BCX__TCOS__SHIFT) |
+ (timing[5] << EXYNOS_SROM_BCX__TACS__SHIFT),
+ srom->reg_base + EXYNOS_SROM_BC0 + bank);
+
+ return 0;
+}
+
static int exynos_srom_probe(struct platform_device *pdev)
{
- struct device_node *np;
+ struct device_node *np, *child;
struct exynos_srom *srom;
struct device *dev = &pdev->dev;
+ bool bad_bank_config = false;
np = dev->of_node;
if (!np) {
@@ -100,7 +141,23 @@ static int exynos_srom_probe(struct platform_device *pdev)
return -ENOMEM;
}
- return 0;
+ for_each_child_of_node(np, child) {
+ if (exynos_srom_configure_bank(srom, child)) {
+ dev_err(dev,
+ "Could not decode bank configuration for %s\n",
+ child->name);
+ bad_bank_config = true;
+ }
+ }
+
+ /*
+ * If any bank failed to configure, we still provide suspend/resume,
+ * but do not probe child devices
+ */
+ if (bad_bank_config)
+ return 0;
+
+ return of_platform_populate(np, NULL, NULL, dev);
}
static int exynos_srom_remove(struct platform_device *pdev)
--
2.4.4
The chip is smsc9115, connected via SROMc bank 3. Additionally, some GPIO
initialization is required.
Signed-off-by: Pavel Fedin <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/exynos5410-smdk5410.dts | 41 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5410.dtsi | 6 +++++
2 files changed, 47 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index cebeaab..373abf7 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "exynos5410.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "Samsung SMDK5410 board based on EXYNOS5410";
compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
@@ -61,6 +62,46 @@
disable-wp;
};
+&pinctrl_0 {
+ srom_ctl: srom-ctl {
+ samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5",
+ "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3";
+ samsung,pin-function = <2>;
+ samsung,pin-drv = <0>;
+ };
+
+ srom_ebi: srom-ebi {
+ samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3",
+ "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7",
+ "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3",
+ "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7",
+ "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3",
+ "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7";
+ samsung,pin-function = <2>;
+ samsung,pin-pud = <3>;
+ samsung,pin-drv = <0>;
+ };
+};
+
+&sromc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&srom_ctl>, <&srom_ebi>;
+
+ ethernet@3 {
+ compatible = "smsc,lan9115";
+ reg = <3 0 0x10000>;
+ phy-mode = "mii";
+ interrupt-parent = <&gpx0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
+ smsc,force-internal-phy;
+
+ samsung,srom-page-mode = <1>;
+ samsung,srom-timing = <9 12 1 9 1 1>;
+ };
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index e2b58f8..9cfb814 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -104,6 +104,12 @@
sromc: sromc@12250000 {
compatible = "samsung,exynos-srom";
reg = <0x12250000 0x14>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x04000000 0x20000
+ 1 0 0x05000000 0x20000
+ 2 0 0x06000000 0x20000
+ 3 0 0x07000000 0x20000>;
};
pmu_system_controller: system-controller@10040000 {
--
2.4.4
On Fri, Nov 6, 2015 at 4:03 AM, Pavel Fedin <[email protected]> wrote:
> Add documentation for new subnode properties, allowing bank configuration.
> Based on u-boot implementation, but heavily reworked.
>
> Also, fix size of SROMc mapping in the example.
>
> Signed-off-by: Pavel Fedin <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/arm/samsung/exynos-srom.txt | 71 +++++++++++++++++++++-
> 1 file changed, 69 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
> index 33886d5..3ff2950 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/exynos-srom.txt
> @@ -5,8 +5,75 @@ Required properties:
>
> - reg: offset and length of the register set
>
> -Example:
> +Optional properties:
> +The SROM controller can be used to attach external peripherals. In this case
> +extra properties, describing the bus behind it, should be specified as below:
> +
> +- #address-cells: Must be set to 2 to allow memory address translation
2 is for CS# and offset.
> +
> +- #size-cells: Must be set to 1 to allow CS address passing
size is the size, not the address.
> +
> +- ranges: Must be set up to reflect the memory layout with four integer values
> + per bank:
> + <bank-number> 0 <physical address of bank> <size>
s/physical/parent/
You could have another level of translation above for the parent.
> +
> +Sub-nodes:
> +The actual device nodes should be added as subnodes to the SROMc node. These
> +subnodes, except regular device specification, should contain the following
> +properties, describing configuration of the relevant SROM bank:
> +
> +Required properties:
> +- reg: bank number, base address (relative to start of the bank) and size of
> + the memory mapped for the device. Note that base address will be
> + typically 0 as this is the start of the bank.
> +
> +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
> + following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
> + Each value is specified in cycles and has the following
> + meaning and valid range:
> + Tacp : Page mode access cycle at Page mode (0 - 15)
> + Tcah : Address holding time after CSn (0 - 15)
> + Tcoh : Chip selection hold on OEn (0 - 15)
> + Tacc : Access cycle (0 - 31, the actual time is N + 1)
> + Tcos : Chip selection set-up before OEn (0 - 15)
> + Tacs : Address set-up before CSn (0 - 15)
This is not easily extended. Perhaps a property per value instead.
> +
> +Optional properties:
> +- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used.
> +
> +- samsung,srom-page-mode : page mode configuration for the bank:
> + 0 - normal (one data)
> + 1 - four data
> + If omitted, default of 0 is used.
> +
> +Example: basic definition, no banks are configured
> + sromc@12570000 {
> + compatible = "samsung,exynos-srom";
> + reg = <0x12570000 0x14>;
> + };
> +
> +Example: SROMc with SMSC911x ethernet chip on bank 3
> sromc@12570000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0x04000000 0x20000 // Bank0
> + 1 0 0x05000000 0x20000 // Bank1
> + 2 0 0x06000000 0x20000 // Bank2
> + 3 0 0x07000000 0x20000>; // Bank3
> +
> compatible = "samsung,exynos-srom";
> - reg = <0x12570000 0x10>;
> + reg = <0x12570000 0x14>;
> +
> + ethernet@3 {
> + compatible = "smsc,lan9115";
> + reg = <3 0 0x10000>; // Bank 3, offset = 0
> + phy-mode = "mii";
> + interrupt-parent = <&gpx0>;
> + interrupts = <5 8>;
> + reg-io-width = <2>;
> + smsc,irq-push-pull;
> + smsc,force-internal-phy;
> +
> + samsung,srom-config = <1 9 12 1 9 1 1>;
This doesn't match the doc.
> + };
> };
> --
> 2.4.4
>
Hello!
> > +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
> > + following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
> > + Each value is specified in cycles and has the following
> > + meaning and valid range:
> > + Tacp : Page mode access cycle at Page mode (0 - 15)
> > + Tcah : Address holding time after CSn (0 - 15)
> > + Tcoh : Chip selection hold on OEn (0 - 15)
> > + Tacc : Access cycle (0 - 31, the actual time is N + 1)
> > + Tcos : Chip selection set-up before OEn (0 - 15)
> > + Tacs : Address set-up before CSn (0 - 15)
>
> This is not easily extended. Perhaps a property per value instead.
We had a discussion with Krzysztof about it, he agreed with this form of the property.
My concern was that it's just too much typing, and makes little sense because these
settings always go together. If register layout changes, or parameter set changes in
incompatible way, then it's another device, not exynos-srom anymore.
So would you agree with that, or is your position strong?
> > compatible = "samsung,exynos-srom";
> > - reg = <0x12570000 0x10>;
> > + reg = <0x12570000 0x14>;
> > +
> > + ethernet@3 {
> > + compatible = "smsc,lan9115";
> > + reg = <3 0 0x10000>; // Bank 3, offset = 0
> > + phy-mode = "mii";
> > + interrupt-parent = <&gpx0>;
> > + interrupts = <5 8>;
> > + reg-io-width = <2>;
> > + smsc,irq-push-pull;
> > + smsc,force-internal-phy;
> > +
> > + samsung,srom-config = <1 9 12 1 9 1 1>;
>
> This doesn't match the doc.
Damn, overlooked. :(
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia
On Wed, Nov 11, 2015 at 12:44 AM, Pavel Fedin <[email protected]> wrote:
> Hello!
>
>> > +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
>> > + following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
>> > + Each value is specified in cycles and has the following
>> > + meaning and valid range:
>> > + Tacp : Page mode access cycle at Page mode (0 - 15)
>> > + Tcah : Address holding time after CSn (0 - 15)
>> > + Tcoh : Chip selection hold on OEn (0 - 15)
>> > + Tacc : Access cycle (0 - 31, the actual time is N + 1)
>> > + Tcos : Chip selection set-up before OEn (0 - 15)
>> > + Tacs : Address set-up before CSn (0 - 15)
>>
>> This is not easily extended. Perhaps a property per value instead.
>
> We had a discussion with Krzysztof about it, he agreed with this form of the property.
> My concern was that it's just too much typing, and makes little sense because these
> settings always go together. If register layout changes, or parameter set changes in
> incompatible way, then it's another device, not exynos-srom anymore.
> So would you agree with that, or is your position strong?
I'm thinking for a new version of the controller which could add (or
remove) new timing parameters, but then I guess you can interpret the
field differently based on the compatible string. Anyway, your problem
to deal with.
Rob
On 12.11.2015 05:43, Rob Herring wrote:
> On Wed, Nov 11, 2015 at 12:44 AM, Pavel Fedin <[email protected]> wrote:
>> Hello!
>>
>>>> +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
>>>> + following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
>>>> + Each value is specified in cycles and has the following
>>>> + meaning and valid range:
>>>> + Tacp : Page mode access cycle at Page mode (0 - 15)
>>>> + Tcah : Address holding time after CSn (0 - 15)
>>>> + Tcoh : Chip selection hold on OEn (0 - 15)
>>>> + Tacc : Access cycle (0 - 31, the actual time is N + 1)
>>>> + Tcos : Chip selection set-up before OEn (0 - 15)
>>>> + Tacs : Address set-up before CSn (0 - 15)
>>>
>>> This is not easily extended. Perhaps a property per value instead.
>>
>> We had a discussion with Krzysztof about it, he agreed with this form of the property.
>> My concern was that it's just too much typing, and makes little sense because these
>> settings always go together. If register layout changes, or parameter set changes in
>> incompatible way, then it's another device, not exynos-srom anymore.
>> So would you agree with that, or is your position strong?
>
> I'm thinking for a new version of the controller which could add (or
> remove) new timing parameters, but then I guess you can interpret the
> field differently based on the compatible string. Anyway, your problem
> to deal with.
Actually I also preferred properties per one timing... but finally
agreed on simpler approach.
Adding new parameters to the array is still possible (because the order
matters) and removal as well (by ignoring some indices). All ARMv7
Exynos SoCs have exactly the same registers for SROM controller
(Exynos3250, Exynos4, Exynos5). On newer Exynos ARMv8 (Exynos5433 and
Exynos7420) I don't know because it is not documented.
Best regards,
Krzysztof
Hello!
> >> > +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
> >> > + following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
> >> > + Each value is specified in cycles and has the following
> >> > + meaning and valid range:
> >> > + Tacp : Page mode access cycle at Page mode (0 - 15)
> >> > + Tcah : Address holding time after CSn (0 - 15)
> >> > + Tcoh : Chip selection hold on OEn (0 - 15)
> >> > + Tacc : Access cycle (0 - 31, the actual time is N + 1)
> >> > + Tcos : Chip selection set-up before OEn (0 - 15)
> >> > + Tacs : Address set-up before CSn (0 - 15)
> >>
> >> This is not easily extended. Perhaps a property per value instead.
> >
> > We had a discussion with Krzysztof about it, he agreed with this form of the property.
> > My concern was that it's just too much typing, and makes little sense because these
> > settings always go together. If register layout changes, or parameter set changes in
> > incompatible way, then it's another device, not exynos-srom anymore.
> > So would you agree with that, or is your position strong?
>
> I'm thinking for a new version of the controller which could add (or
> remove) new timing parameters, but then I guess you can interpret the
> field differently based on the compatible string. Anyway, your problem
> to deal with.
Of course, my thought is that if compatible string is different,
then it's already a different device. And of course it would have different parameters.
So, OK, i'll post new version with fixed documentation today.
Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia