This series enables the MMC controller in the T-Head TH1520 SoC and
enables the eMMC and microSD on both the BeagleV Ahead and the Sipeed
LicheePi 4A.
The drivers/mmc/host patches from v6 were applied by Ulf and are already
in the linux-next [1][2] as well as the bindings patch [3]. Thus v7 was
only a defconfig patch and three device tree patches. This v8 is a
followup to change the dwcmshc node names to match the documentation.
Jisheng - can you apply the dts patches to your for-next tree?
I tested with the riscv defconfig on the Ahead [4] and LPi4a [5]. I only
tested eMMC and microSD and plan to enable SDIO WiFi in the future.
References:
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=49f23745b064cdb6270402403ef58125d78ba183
[2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=aff35fbc7830510ef7cbcf8e32a041a55de3dc51
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=af076680db846ed54b00b9a763473d1043446993
[4] https://gist.github.com/pdp7/881342620ec1509685f23a387e2fc8d7
[5] https://gist.github.com/pdp7/97017ad88d83fccac18eba69bff817b7
Changes in PATCH v8:
- change dwcmshc node labels to match TH1520 System Reference Manual:
emmc, sdio0, sdio1
Changes in PATCH v7:
//lore.kernel.org/r/[email protected]
- fix sorting of DT properties in the mmc nodes
Changes in PATCH v6:
https://lore.kernel.org/linux-riscv/[email protected]/
- set the mmc nodes to disabled in the th1520.dtsi
Changes in PATCH v5:
https://lore.kernel.org/r/[email protected]
- fix logic in th1520_sdhci_set_phy() to correctly check that both
MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIO are set in host->mmc->caps2
- add Acked-by's from Adrian
Changes in PATCH v4:
https://lore.kernel.org/linux-riscv/[email protected]/
- set DWCMSHC_CARD_IS_EMMC when (MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO)
as checking MMC_CAP_NONREMOVABLE is not sufficient
- change prefix of phy functions from th1520 to dwcmshc as they are not
th1520 specific
- remove unneeded check of priv in dwcmshc_phy_1_8v_init()
- remove unneeded check of auto-tuning in th1520_execute_tuning()
- fix order of new nodes in th1520-beaglev-ahead.dts: move sdhci_clk
before uart_sclk, move mmc0 and mmc1 before uart0
- fix comment typos pointed out by Adrian
- add trailers that I missed from v2
Changes in PATCH v3:
https://lore.kernel.org/r/[email protected]
- always call th1520_sdhci_set_phy() in th1520_set_uhs_signaling()
and not only when timing is MMC_TIMING_MMC_HS400. This allows the
microSD slot to work as th1520_phy_3_3v_init() is called from
th1520_sdhci_set_phy().
- add mmc1 node for mmc controller connected to the microSD slot
- add enable mmc1 and add properties for microSD on the Ahead and LPi4A
Changes in PATCH v2:
https://lore.kernel.org/r/[email protected]
- make use of BIT(), GENMASK(), FIELD_PREP(), FIELD_GET()
- add EXPORT_SYMBOL_GPL(__sdhci_execute_tuning)
- call th1520_phy_1_8v_init() when FLAG_IO_FIXED_1V8 is set
- set DWCMSHC_CARD_IS_EMMC when mmc caps contains MMC_CAP_NONREMOVABLE
- remove manipulation of AT_CTRL_AT_EN from th1520_set_uhs_signaling()
- remove unneccessary cycle of enabling and disabling AT_CTRL_AT_EN in
th1520_execute_tuning()
- remove th1520_phy_1_8v_init_no_pull()
- remove th1520_phy_3_3v_init_no_pull()
- remove FLAG_PULL_UP_EN from priv->flags
- remove thead,phy-pull-up device tree property
Changes in PACH v1:
https://lore.kernel.org/all/[email protected]/
- ADMA mode now works correctly due to a patch from Jisheng on the list
("riscv: dts: thead: set dma-noncoherent to soc bus") and this commit
from Icenowy that is now merged: 8eb8fe67e2c8 ("riscv: errata: fix
T-Head dcache.cva encoding").
- Expose __sdhci_execute_tuning from sdhci.c so that it can be called
from th1520_execute_tuning()
- Refactor the define macros for all the PHY related registers to make
it easier to understand the bit fields that the code is manipulating
- Replace magic numbers in the PHY register writes with proper defines
- Replace non_removable in dwcmshc_priv with check of mmc_host.caps
- Drop dt prop "thead,io-fixed-1v8" and instead check for existing
properties: "mmc-ddr-1_8v", "mmc-hs200-1_8v", or "mmc-hs400-1_8v"
- Rename dt prop from "thead,pull-up" to "thead,phy-pull-up" and
improve the description in the dt binding
- Replace pull_up_en in dwcmshc_priv with bit field in new flags field
- Create th1520_set_uhs_signaling() and call dwcmshc_set_uhs_signaling()
from it instead of adding th1520 code to dwcmshc_set_uhs_signaling()
- Return -EIO instead of -1 upon errors in th1520_execute_tuning()
Changes in RFC v2:
https://lore.kernel.org/linux-riscv/[email protected]/
- Expand dwcmshc_priv based on driver in the T-Head 5.10 kernel:
delay_line, non_removable, pull_up_en, io_fixed_1v8
- New boolean property "thead,pull-up" indicates phy pull-up config
- New boolean property "thead,io-fixed-1v8" indicates that io voltage
should be set to 1.8V during reset
- Add th1520_phy_1_8v_init() as voltage_switch op
- Add th1520_execute_tuning() as the platform_execute_tuning op
- Added th1520_sdhci_reset() as the .reset op. This function will set
io voltage to 1.8V after calling the standard sdhci_reset() function.
- Modified dwcmshc_set_uhs_signaling() to enable SDHCI_CTRL_VDD_180 when
io_fixed_1v8 is true
- Add many defines for register offsets and settings based on the mmc
support in the T-Head downstream v5.10 kernel
RFC v1 series:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Drew Fustini <[email protected]>
---
Drew Fustini (4):
riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520
riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 20 +++++++++++++
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 +++++++++++++
arch/riscv/boot/dts/thead/th1520.dtsi | 34 ++++++++++++++++++++++
arch/riscv/configs/defconfig | 2 ++
4 files changed, 76 insertions(+)
---
base-commit: 1f5c003694fab4b1ba6cbdcc417488b975c088d0
change-id: 20231129-th1520_mmc_dts-e472bcc70d0d
Best regards,
--
Drew Fustini <[email protected]>
Add emmc node properties for the eMMC device and add sdio0 node
properties for the microSD slot. Set the frequency for the sdhci
reference clock.
Signed-off-by: Drew Fustini <[email protected]>
---
.../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index a802ab110429..1365d3a512a3 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -29,6 +29,10 @@ &apb_clk {
clock-frequency = <62500000>;
};
+&sdhci_clk {
+ clock-frequency = <198000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
@@ -36,3 +40,19 @@ &uart_sclk {
&dmac0 {
status = "okay";
};
+
+&emmc {
+ bus-width = <8>;
+ max-frequency = <198000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ max-frequency = <198000000>;
+ status = "okay";
+};
--
2.34.1
Add emmc node properties for the eMMC device and add sdio0 node
properties for the microSD slot. Set the frequency for the sdhci
reference clock.
Signed-off-by: Drew Fustini <[email protected]>
---
arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index 70e8042c8304..d9b4de9e4757 100644
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -48,6 +48,10 @@ &apb_clk {
clock-frequency = <62500000>;
};
+&sdhci_clk {
+ clock-frequency = <198000000>;
+};
+
&uart_sclk {
clock-frequency = <100000000>;
};
@@ -56,6 +60,22 @@ &dmac0 {
status = "okay";
};
+&emmc {
+ bus-width = <8>;
+ max-frequency = <198000000>;
+ mmc-hs400-1_8v;
+ non-removable;
+ no-sdio;
+ no-sd;
+ status = "okay";
+};
+
+&sdio0 {
+ bus-width = <4>;
+ max-frequency = <198000000>;
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
--
2.34.1
On Wed, Dec 6, 2023 at 4:09 PM Drew Fustini <[email protected]> wrote:
>
> Add emmc node properties for the eMMC device and add sdio0 node
> properties for the microSD slot. Set the frequency for the sdhci
> reference clock.
>
> Signed-off-by: Drew Fustini <[email protected]>
> ---
> .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> index a802ab110429..1365d3a512a3 100644
> --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> @@ -29,6 +29,10 @@ &apb_clk {
> clock-frequency = <62500000>;
> };
>
> +&sdhci_clk {
> + clock-frequency = <198000000>;
> +};
> +
> &uart_sclk {
> clock-frequency = <100000000>;
> };
> @@ -36,3 +40,19 @@ &uart_sclk {
> &dmac0 {
> status = "okay";
> };
> +
> +&emmc {
> + bus-width = <8>;
> + max-frequency = <198000000>;
> + mmc-hs400-1_8v;
> + non-removable;
> + no-sdio;
> + no-sd;
> + status = "okay";
> +};
> +
> +&sdio0 {
> + bus-width = <4>;
> + max-frequency = <198000000>;
> + status = "okay";
> +};
>
> --
> 2.34.1
>
Reviewed-by: Guo Ren <[email protected]>
--
Best Regards
Guo Ren
On Wed, Dec 6, 2023 at 4:09 PM Drew Fustini <[email protected]> wrote:
>
> Add emmc node properties for the eMMC device and add sdio0 node
> properties for the microSD slot. Set the frequency for the sdhci
> reference clock.
>
> Signed-off-by: Drew Fustini <[email protected]>
> ---
> arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> index 70e8042c8304..d9b4de9e4757 100644
> --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
> @@ -48,6 +48,10 @@ &apb_clk {
> clock-frequency = <62500000>;
> };
>
> +&sdhci_clk {
> + clock-frequency = <198000000>;
> +};
> +
> &uart_sclk {
> clock-frequency = <100000000>;
> };
> @@ -56,6 +60,22 @@ &dmac0 {
> status = "okay";
> };
>
> +&emmc {
> + bus-width = <8>;
> + max-frequency = <198000000>;
> + mmc-hs400-1_8v;
> + non-removable;
> + no-sdio;
> + no-sd;
> + status = "okay";
> +};
> +
> +&sdio0 {
> + bus-width = <4>;
> + max-frequency = <198000000>;
> + status = "okay";
> +};
> +
> &uart0 {
> status = "okay";
> };
>
> --
> 2.34.1
>
Maybe, we could share some parts with th1520-lichee-module-4a.dtsi.
Others, LGTM.|
Reviewed-by: Guo Ren <[email protected]>
--
Best Regards
Guo Ren
On Wed, Dec 06, 2023 at 12:09:20AM -0800, Drew Fustini wrote:
> This series enables the MMC controller in the T-Head TH1520 SoC and
> enables the eMMC and microSD on both the BeagleV Ahead and the Sipeed
> LicheePi 4A.
>
> The drivers/mmc/host patches from v6 were applied by Ulf and are already
> in the linux-next [1][2] as well as the bindings patch [3]. Thus v7 was
> only a defconfig patch and three device tree patches. This v8 is a
> followup to change the dwcmshc node names to match the documentation.
>
> Jisheng - can you apply the dts patches to your for-next tree?
>
> I tested with the riscv defconfig on the Ahead [4] and LPi4a [5]. I only
> tested eMMC and microSD and plan to enable SDIO WiFi in the future.
Thank Drew, for this patch series:
Reviewed-by: Jisheng Zhang <[email protected]>
I asked Conor's help to take T-HEAD SoC dts patches.
>
> References:
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=49f23745b064cdb6270402403ef58125d78ba183
> [2] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=aff35fbc7830510ef7cbcf8e32a041a55de3dc51
> [3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=af076680db846ed54b00b9a763473d1043446993
> [4] https://gist.github.com/pdp7/881342620ec1509685f23a387e2fc8d7
> [5] https://gist.github.com/pdp7/97017ad88d83fccac18eba69bff817b7
>
> Changes in PATCH v8:
> - change dwcmshc node labels to match TH1520 System Reference Manual:
> emmc, sdio0, sdio1
>
> Changes in PATCH v7:
> //lore.kernel.org/r/[email protected]
> - fix sorting of DT properties in the mmc nodes
>
> Changes in PATCH v6:
> https://lore.kernel.org/linux-riscv/[email protected]/
> - set the mmc nodes to disabled in the th1520.dtsi
>
> Changes in PATCH v5:
> https://lore.kernel.org/r/[email protected]
> - fix logic in th1520_sdhci_set_phy() to correctly check that both
> MMC_CAP2_NO_SD and MMC_CAP2_NO_SDIO are set in host->mmc->caps2
> - add Acked-by's from Adrian
>
> Changes in PATCH v4:
> https://lore.kernel.org/linux-riscv/[email protected]/
> - set DWCMSHC_CARD_IS_EMMC when (MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO)
> as checking MMC_CAP_NONREMOVABLE is not sufficient
> - change prefix of phy functions from th1520 to dwcmshc as they are not
> th1520 specific
> - remove unneeded check of priv in dwcmshc_phy_1_8v_init()
> - remove unneeded check of auto-tuning in th1520_execute_tuning()
> - fix order of new nodes in th1520-beaglev-ahead.dts: move sdhci_clk
> before uart_sclk, move mmc0 and mmc1 before uart0
> - fix comment typos pointed out by Adrian
> - add trailers that I missed from v2
>
> Changes in PATCH v3:
> https://lore.kernel.org/r/[email protected]
> - always call th1520_sdhci_set_phy() in th1520_set_uhs_signaling()
> and not only when timing is MMC_TIMING_MMC_HS400. This allows the
> microSD slot to work as th1520_phy_3_3v_init() is called from
> th1520_sdhci_set_phy().
> - add mmc1 node for mmc controller connected to the microSD slot
> - add enable mmc1 and add properties for microSD on the Ahead and LPi4A
>
> Changes in PATCH v2:
> https://lore.kernel.org/r/[email protected]
> - make use of BIT(), GENMASK(), FIELD_PREP(), FIELD_GET()
> - add EXPORT_SYMBOL_GPL(__sdhci_execute_tuning)
> - call th1520_phy_1_8v_init() when FLAG_IO_FIXED_1V8 is set
> - set DWCMSHC_CARD_IS_EMMC when mmc caps contains MMC_CAP_NONREMOVABLE
> - remove manipulation of AT_CTRL_AT_EN from th1520_set_uhs_signaling()
> - remove unneccessary cycle of enabling and disabling AT_CTRL_AT_EN in
> th1520_execute_tuning()
> - remove th1520_phy_1_8v_init_no_pull()
> - remove th1520_phy_3_3v_init_no_pull()
> - remove FLAG_PULL_UP_EN from priv->flags
> - remove thead,phy-pull-up device tree property
>
> Changes in PACH v1:
> https://lore.kernel.org/all/[email protected]/
> - ADMA mode now works correctly due to a patch from Jisheng on the list
> ("riscv: dts: thead: set dma-noncoherent to soc bus") and this commit
> from Icenowy that is now merged: 8eb8fe67e2c8 ("riscv: errata: fix
> T-Head dcache.cva encoding").
> - Expose __sdhci_execute_tuning from sdhci.c so that it can be called
> from th1520_execute_tuning()
> - Refactor the define macros for all the PHY related registers to make
> it easier to understand the bit fields that the code is manipulating
> - Replace magic numbers in the PHY register writes with proper defines
> - Replace non_removable in dwcmshc_priv with check of mmc_host.caps
> - Drop dt prop "thead,io-fixed-1v8" and instead check for existing
> properties: "mmc-ddr-1_8v", "mmc-hs200-1_8v", or "mmc-hs400-1_8v"
> - Rename dt prop from "thead,pull-up" to "thead,phy-pull-up" and
> improve the description in the dt binding
> - Replace pull_up_en in dwcmshc_priv with bit field in new flags field
> - Create th1520_set_uhs_signaling() and call dwcmshc_set_uhs_signaling()
> from it instead of adding th1520 code to dwcmshc_set_uhs_signaling()
> - Return -EIO instead of -1 upon errors in th1520_execute_tuning()
>
> Changes in RFC v2:
> https://lore.kernel.org/linux-riscv/[email protected]/
> - Expand dwcmshc_priv based on driver in the T-Head 5.10 kernel:
> delay_line, non_removable, pull_up_en, io_fixed_1v8
> - New boolean property "thead,pull-up" indicates phy pull-up config
> - New boolean property "thead,io-fixed-1v8" indicates that io voltage
> should be set to 1.8V during reset
> - Add th1520_phy_1_8v_init() as voltage_switch op
> - Add th1520_execute_tuning() as the platform_execute_tuning op
> - Added th1520_sdhci_reset() as the .reset op. This function will set
> io voltage to 1.8V after calling the standard sdhci_reset() function.
> - Modified dwcmshc_set_uhs_signaling() to enable SDHCI_CTRL_VDD_180 when
> io_fixed_1v8 is true
> - Add many defines for register offsets and settings based on the mmc
> support in the T-Head downstream v5.10 kernel
>
> RFC v1 series:
> https://lore.kernel.org/r/[email protected]
>
> Signed-off-by: Drew Fustini <[email protected]>
> ---
> Drew Fustini (4):
> riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520
> riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
> riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
> riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
>
> arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 20 +++++++++++++
> .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 +++++++++++++
> arch/riscv/boot/dts/thead/th1520.dtsi | 34 ++++++++++++++++++++++
> arch/riscv/configs/defconfig | 2 ++
> 4 files changed, 76 insertions(+)
> ---
> base-commit: 1f5c003694fab4b1ba6cbdcc417488b975c088d0
> change-id: 20231129-th1520_mmc_dts-e472bcc70d0d
>
> Best regards,
> --
> Drew Fustini <[email protected]>
>
From: Conor Dooley <[email protected]>
On Wed, 06 Dec 2023 00:09:20 -0800, Drew Fustini wrote:
> This series enables the MMC controller in the T-Head TH1520 SoC and
> enables the eMMC and microSD on both the BeagleV Ahead and the Sipeed
> LicheePi 4A.
>
> The drivers/mmc/host patches from v6 were applied by Ulf and are already
> in the linux-next [1][2] as well as the bindings patch [3]. Thus v7 was
> only a defconfig patch and three device tree patches. This v8 is a
> followup to change the dwcmshc node names to match the documentation.
>
> [...]
Applied to riscv-dt-for-next, thanks! The defconfig patch is Palmer's
to take :)
[2/4] riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
https://git.kernel.org/conor/c/a77f02e84896
[3/4] riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
https://git.kernel.org/conor/c/18d92a03b319
[4/4] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
https://git.kernel.org/conor/c/b6b5028473ce
Thanks,
Conor.
On Tue, Dec 12, 2023 at 07:13:25PM +0000, Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> On Wed, 06 Dec 2023 00:09:20 -0800, Drew Fustini wrote:
> > This series enables the MMC controller in the T-Head TH1520 SoC and
> > enables the eMMC and microSD on both the BeagleV Ahead and the Sipeed
> > LicheePi 4A.
> >
> > The drivers/mmc/host patches from v6 were applied by Ulf and are already
> > in the linux-next [1][2] as well as the bindings patch [3]. Thus v7 was
> > only a defconfig patch and three device tree patches. This v8 is a
> > followup to change the dwcmshc node names to match the documentation.
> >
> > [...]
>
> Applied to riscv-dt-for-next, thanks! The defconfig patch is Palmer's
> to take :)
>
> [2/4] riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
> https://git.kernel.org/conor/c/a77f02e84896
> [3/4] riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
> https://git.kernel.org/conor/c/18d92a03b319
> [4/4] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
> https://git.kernel.org/conor/c/b6b5028473ce
Hi Palmer,
I don't see this in fixes or for-next. Could you pick it up please?
I've tested that Lichee Pi 4a and Ahead boot okay on 6.8-rc4 once
'CONFIG_MMC_SDHCI_OF_DWCMSHC=y' is set.
Thanks,
Drew
On Tue, 12 Dec 2023 11:13:25 PST (-0800), Conor Dooley wrote:
> From: Conor Dooley <[email protected]>
>
> On Wed, 06 Dec 2023 00:09:20 -0800, Drew Fustini wrote:
>> This series enables the MMC controller in the T-Head TH1520 SoC and
>> enables the eMMC and microSD on both the BeagleV Ahead and the Sipeed
>> LicheePi 4A.
>>
>> The drivers/mmc/host patches from v6 were applied by Ulf and are already
>> in the linux-next [1][2] as well as the bindings patch [3]. Thus v7 was
>> only a defconfig patch and three device tree patches. This v8 is a
>> followup to change the dwcmshc node names to match the documentation.
>>
>> [...]
>
> Applied to riscv-dt-for-next, thanks! The defconfig patch is Palmer's
> to take :)
Sorry I missed this. It's on my staging branch, but I'm still debugging
some boot hangs post-merge so it might take a bit to show up on
linux-next...
>
> [2/4] riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
> https://git.kernel.org/conor/c/a77f02e84896
> [3/4] riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
> https://git.kernel.org/conor/c/18d92a03b319
> [4/4] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
> https://git.kernel.org/conor/c/b6b5028473ce
>
> Thanks,
> Conor.
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[email protected]>:
On Wed, 06 Dec 2023 00:09:20 -0800 you wrote:
> This series enables the MMC controller in the T-Head TH1520 SoC and
> enables the eMMC and microSD on both the BeagleV Ahead and the Sipeed
> LicheePi 4A.
>
> The drivers/mmc/host patches from v6 were applied by Ulf and are already
> in the linux-next [1][2] as well as the bindings patch [3]. Thus v7 was
> only a defconfig patch and three device tree patches. This v8 is a
> followup to change the dwcmshc node names to match the documentation.
>
> [...]
Here is the summary with links:
- [v8,1/4] riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520
https://git.kernel.org/riscv/c/45e0b0fd6dc5
- [v8,2/4] riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
(no matching commit)
- [v8,3/4] riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
(no matching commit)
- [v8,4/4] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
On Wed, 2023-12-06 at 00:09 -0800, Drew Fustini wrote:
> Add emmc node properties for the eMMC device and add sdio0 node
> properties for the microSD slot. Set the frequency for the sdhci
> reference clock.
Hi Drew,
I've been using the emmc on LicheePi 4A for a while without any problem,
but when I try the microSD slot I get:
[ 0.531804] mmc1: SDHCI controller on ffe7090000.mmc [ffe7090000.mmc] using ADMA 64-bit
[ 0.842674] mmc1: Tuning failed, falling back to fixed sampling clock
[ 0.855139] mmc1: tuning execution failed: -5
[ 0.859609] mmc1: error -5 whilst initialising SD card
[ 11.359879] mmc1: Timeout waiting for hardware cmd interrupt.
[ 11.365661] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 11.372105] mmc1: sdhci: Sys addr: 0x00000001 | Version: 0x00000005
[ 11.378547] mmc1: sdhci: Blk size: 0x00007040 | Blk cnt: 0x00000000
[ 11.384989] mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000010
[ 11.391432] mmc1: sdhci: Present: 0x03ff0000 | Host ctl: 0x00000017
[ 11.397873] mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000000
[ 11.404312] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000000f
[ 11.410753] mmc1: sdhci: Timeout: 0x00000004 | Int stat: 0x00000000
[ 11.417192] mmc1: sdhci: Int enab: 0x00000020 | Sig enab: 0x00000020
[ 11.423633] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[ 11.430073] mmc1: sdhci: Caps: 0x3f69c881 | Caps_1: 0x08008177
[ 11.436513] mmc1: sdhci: Cmd: 0x00000102 | Max curr: 0x00191919
[ 11.442954] mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x07725f7f
[ 11.449394] mmc1: sdhci: Resp[2]: 0x32db7900 | Resp[3]: 0x00400e00
[ 11.455835] mmc1: sdhci: Host ctl2: 0x0000300b
[ 11.460280] mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000882220
[ 11.467416] mmc1: sdhci: ============================================
[ 11.563828] mmc1: Tuning failed, falling back to fixed sampling clock
[ 11.576053] mmc1: tuning execution failed: -5
[ 11.646438] mmc1: new high speed SDXC card at address aaaa
[ 11.653170] mmcblk1: mmc1:aaaa SR256 238 GiB
I can write something into the SD card and read it back though. But
this makes me reluctant to use the SD card for "some real thing" afraid
of a data loss.
The SD card is a SanDisk Extreme Pro 256GB (rated "U3, A2, V30").
Any idea how to debug this issue further? (Maybe I should try change
the SD card first but I'd like to discuss the issue before paying money
for another card.)
> Signed-off-by: Drew Fustini <[email protected]>
> ---
> .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> index a802ab110429..1365d3a512a3 100644
> --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> @@ -29,6 +29,10 @@ &apb_clk {
> clock-frequency = <62500000>;
> };
>
> +&sdhci_clk {
> + clock-frequency = <198000000>;
> +};
> +
> &uart_sclk {
> clock-frequency = <100000000>;
> };
> @@ -36,3 +40,19 @@ &uart_sclk {
> &dmac0 {
> status = "okay";
> };
> +
> +&emmc {
> + bus-width = <8>;
> + max-frequency = <198000000>;
> + mmc-hs400-1_8v;
> + non-removable;
> + no-sdio;
> + no-sd;
> + status = "okay";
> +};
> +
> +&sdio0 {
> + bus-width = <4>;
> + max-frequency = <198000000>;
> + status = "okay";
> +};
--
Xi Ruoyao <[email protected]>
School of Aerospace Science and Technology, Xidian University
On Sat, Mar 02, 2024 at 10:13:55PM +0800, Xi Ruoyao wrote:
> On Wed, 2023-12-06 at 00:09 -0800, Drew Fustini wrote:
> > Add emmc node properties for the eMMC device and add sdio0 node
> > properties for the microSD slot. Set the frequency for the sdhci
> > reference clock.
>
> Hi Drew,
>
> I've been using the emmc on LicheePi 4A for a while without any problem,
> but when I try the microSD slot I get:
>
> [ 0.531804] mmc1: SDHCI controller on ffe7090000.mmc [ffe7090000.mmc] using ADMA 64-bit
> [ 0.842674] mmc1: Tuning failed, falling back to fixed sampling clock
> [ 0.855139] mmc1: tuning execution failed: -5
> [ 0.859609] mmc1: error -5 whilst initialising SD card
> [ 11.359879] mmc1: Timeout waiting for hardware cmd interrupt.
> [ 11.365661] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
> [ 11.372105] mmc1: sdhci: Sys addr: 0x00000001 | Version: 0x00000005
> [ 11.378547] mmc1: sdhci: Blk size: 0x00007040 | Blk cnt: 0x00000000
> [ 11.384989] mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000010
> [ 11.391432] mmc1: sdhci: Present: 0x03ff0000 | Host ctl: 0x00000017
> [ 11.397873] mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000000
> [ 11.404312] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000000f
> [ 11.410753] mmc1: sdhci: Timeout: 0x00000004 | Int stat: 0x00000000
> [ 11.417192] mmc1: sdhci: Int enab: 0x00000020 | Sig enab: 0x00000020
> [ 11.423633] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
> [ 11.430073] mmc1: sdhci: Caps: 0x3f69c881 | Caps_1: 0x08008177
> [ 11.436513] mmc1: sdhci: Cmd: 0x00000102 | Max curr: 0x00191919
> [ 11.442954] mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x07725f7f
> [ 11.449394] mmc1: sdhci: Resp[2]: 0x32db7900 | Resp[3]: 0x00400e00
> [ 11.455835] mmc1: sdhci: Host ctl2: 0x0000300b
> [ 11.460280] mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000882220
> [ 11.467416] mmc1: sdhci: ============================================
> [ 11.563828] mmc1: Tuning failed, falling back to fixed sampling clock
> [ 11.576053] mmc1: tuning execution failed: -5
> [ 11.646438] mmc1: new high speed SDXC card at address aaaa
> [ 11.653170] mmcblk1: mmc1:aaaa SR256 238 GiB
>
> I can write something into the SD card and read it back though. But
> this makes me reluctant to use the SD card for "some real thing" afraid
> of a data loss.
>
> The SD card is a SanDisk Extreme Pro 256GB (rated "U3, A2, V30").
>
> Any idea how to debug this issue further? (Maybe I should try change
> the SD card first but I'd like to discuss the issue before paying money
> for another card.)
Revy informed me that downclocking from 198 MHz to 100 MHz [1] has been
observed to solve this problem. Could you try the following dts patch?
Also, I have noticed the T-Head's 5.10 vendor kernel does have some
updates in sdhci-of-dwcmshc.c related to tuning. I'll look at porting
those to the upstream driving.
Thanks,
Drew
[1] https://github.com/revyos/thead-kernel/pull/62
[2] https://github.com/revyos/thead-kernel/commit/afef388b8e26f0d77f9d2261b6e57991941a213f#diff-ba729b399f3cb86d6a2503890c3626a6426c1572a54f24cd7ab3337f5fc75674
------ [cut here] --------
From db4d406fc15c76317993a39a72061d3df47e86f0 Mon Sep 17 00:00:00 2001
From: Drew Fustini <[email protected]>
Date: Sat, 2 Mar 2024 08:21:50 -0800
Subject: [PATCH] riscv: dts: thead: downgrade microSD to 100 MHz max
Downgrade max freq for microSD controller from 198 MHz to 100 MHz to
avoid timeout errors.
Signed-off-by: Drew Fustini <[email protected]>
---
arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 1365d3a512a3..d6ae671f94a9 100644
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -53,6 +53,6 @@ &emmc {
&sdio0 {
bus-width = <4>;
- max-frequency = <198000000>;
+ max-frequency = <100000000>;
status = "okay";
};
--
2.34.1
On Sat, 2024-03-02 at 08:25 -0800, Drew Fustini wrote:
> On Sat, Mar 02, 2024 at 10:13:55PM +0800, Xi Ruoyao wrote:
> > On Wed, 2023-12-06 at 00:09 -0800, Drew Fustini wrote:
> > > Add emmc node properties for the eMMC device and add sdio0 node
> > > properties for the microSD slot. Set the frequency for the sdhci
> > > reference clock.
> >
> > Hi Drew,
> >
> > I've been using the emmc on LicheePi 4A for a while without any problem,
> > but when I try the microSD slot I get:
> >
> > [ 0.531804] mmc1: SDHCI controller on ffe7090000.mmc [ffe7090000.mmc] using ADMA 64-bit
> > [ 0.842674] mmc1: Tuning failed, falling back to fixed sampling clock
> > [ 0.855139] mmc1: tuning execution failed: -5
> > [ 0.859609] mmc1: error -5 whilst initialising SD card
> > [ 11.359879] mmc1: Timeout waiting for hardware cmd interrupt.
> > [ 11.365661] mmc1: sdhci: ============ SDHCI REGISTER DUMP ===========
> > [ 11.372105] mmc1: sdhci: Sys addr: 0x00000001 | Version: 0x00000005
> > [ 11.378547] mmc1: sdhci: Blk size: 0x00007040 | Blk cnt: 0x00000000
> > [ 11.384989] mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000010
> > [ 11.391432] mmc1: sdhci: Present: 0x03ff0000 | Host ctl: 0x00000017
> > [ 11.397873] mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000000
> > [ 11.404312] mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000000f
> > [ 11.410753] mmc1: sdhci: Timeout: 0x00000004 | Int stat: 0x00000000
> > [ 11.417192] mmc1: sdhci: Int enab: 0x00000020 | Sig enab: 0x00000020
> > [ 11.423633] mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
> > [ 11.430073] mmc1: sdhci: Caps: 0x3f69c881 | Caps_1: 0x08008177
> > [ 11.436513] mmc1: sdhci: Cmd: 0x00000102 | Max curr: 0x00191919
> > [ 11.442954] mmc1: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x07725f7f
> > [ 11.449394] mmc1: sdhci: Resp[2]: 0x32db7900 | Resp[3]: 0x00400e00
> > [ 11.455835] mmc1: sdhci: Host ctl2: 0x0000300b
> > [ 11.460280] mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x0000000000882220
> > [ 11.467416] mmc1: sdhci: ============================================
> > [ 11.563828] mmc1: Tuning failed, falling back to fixed sampling clock
> > [ 11.576053] mmc1: tuning execution failed: -5
> > [ 11.646438] mmc1: new high speed SDXC card at address aaaa
> > [ 11.653170] mmcblk1: mmc1:aaaa SR256 238 GiB
> >
> > I can write something into the SD card and read it back though. But
> > this makes me reluctant to use the SD card for "some real thing" afraid
> > of a data loss.
> >
> > The SD card is a SanDisk Extreme Pro 256GB (rated "U3, A2, V30").
> >
> > Any idea how to debug this issue further? (Maybe I should try change
> > the SD card first but I'd like to discuss the issue before paying money
> > for another card.)
>
> Revy informed me that downclocking from 198 MHz to 100 MHz [1] has been
> observed to solve this problem. Could you try the following dts patch?
I'm still getting the same error.
> Also, I have noticed the T-Head's 5.10 vendor kernel does have some
> updates in sdhci-of-dwcmshc.c related to tuning. I'll look at porting
> those to the upstream driving.
Maybe to solve the problem we need both the downclocking and these
changes then...
--
Xi Ruoyao <[email protected]>
School of Aerospace Science and Technology, Xidian University
Hi Xi, Drew
I have the same problem with SD on my LicheePi 4A.
After some investigations I found how to fix this tuning error.
Here is the patch that increases tuning loop count from
40(MAX_TUNING_LOOP at sdhci.c) to 128.
diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c
b/drivers/mmc/host/sdhci-of-dwcmshc.c
index 8d6cfb648096..da8f5820fb69 100644
--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
@@ -706,6 +706,7 @@ static int th1520_execute_tuning(struct sdhci_host
*host, u32 opcode)
/* perform tuning */
sdhci_start_tuning(host);
+ host->tuning_loop_count = 128:
host->tuning_err = __sdhci_execute_tuning(host, opcode);
if (host->tuning_err) {
/* disable auto-tuning upon tuning error */
After that change tuning works fine. The same value of loop count is
used in RevyOS BSP
https://github.com/revyos/thead-kernel/blob/c6d4e5df18a17903d012ffd89e67d0ee5ce6cf2d/drivers/mmc/host/sdhci-of-dwcmshc.c#L185
Honestly, it looks a little bit strange for me.
It seems that the tuning algorithm requires to move through
all the taps of delay line(128 taps?) even if we use THRESHOLD_MODE
instend LARGEST_WIN_MODE (I mean bit 2 in AT_CTRL_R(0x540) register).
Xi, could you also test my fix on your board?
Best regards,
Maksim
On Wed, 2024-03-20 at 15:28 +0300, Maxim Kiselev wrote:
> Hi Xi, Drew
>
> I have the same problem with SD on my LicheePi 4A.
>
> After some investigations I found how to fix this tuning error.
> Here is the patch that increases tuning loop count from
> 40(MAX_TUNING_LOOP at sdhci.c) to 128.
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c
> b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 8d6cfb648096..da8f5820fb69 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -706,6 +706,7 @@ static int th1520_execute_tuning(struct sdhci_host
> *host, u32 opcode)
>
> /* perform tuning */
> sdhci_start_tuning(host);
> + host->tuning_loop_count = 128:
> host->tuning_err = __sdhci_execute_tuning(host, opcode);
> if (host->tuning_err) {
> /* disable auto-tuning upon tuning error */
>
> After that change tuning works fine. The same value of loop count is
> used in RevyOS BSP
> https://github.com/revyos/thead-kernel/blob/c6d4e5df18a17903d012ffd89e67d0ee5ce6cf2d/drivers/mmc/host/sdhci-of-dwcmshc.c#L185
>
> Honestly, it looks a little bit strange for me.
>
> It seems that the tuning algorithm requires to move through
> all the taps of delay line(128 taps?) even if we use THRESHOLD_MODE
> instend LARGEST_WIN_MODE (I mean bit 2 in AT_CTRL_R(0x540) register).
>
> Xi, could you also test my fix on your board?
I'll try it this weekend. Now having some work with "real time
priority" to do :(.
--
Xi Ruoyao <[email protected]>
School of Aerospace Science and Technology, Xidian University
On Wed, Mar 20, 2024 at 03:28:19PM +0300, Maxim Kiselev wrote:
> Hi Xi, Drew
>
> I have the same problem with SD on my LicheePi 4A.
>
> After some investigations I found how to fix this tuning error.
> Here is the patch that increases tuning loop count from
> 40(MAX_TUNING_LOOP at sdhci.c) to 128.
>
> diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c
> b/drivers/mmc/host/sdhci-of-dwcmshc.c
> index 8d6cfb648096..da8f5820fb69 100644
> --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> @@ -706,6 +706,7 @@ static int th1520_execute_tuning(struct sdhci_host
> *host, u32 opcode)
>
> /* perform tuning */
> sdhci_start_tuning(host);
> + host->tuning_loop_count = 128:
> host->tuning_err = __sdhci_execute_tuning(host, opcode);
> if (host->tuning_err) {
> /* disable auto-tuning upon tuning error */
>
> After that change tuning works fine. The same value of loop count is
> used in RevyOS BSP
> https://github.com/revyos/thead-kernel/blob/c6d4e5df18a17903d012ffd89e67d0ee5ce6cf2d/drivers/mmc/host/sdhci-of-dwcmshc.c#L185
>
> Honestly, it looks a little bit strange for me.
>
> It seems that the tuning algorithm requires to move through
> all the taps of delay line(128 taps?) even if we use THRESHOLD_MODE
> instend LARGEST_WIN_MODE (I mean bit 2 in AT_CTRL_R(0x540) register).
>
> Xi, could you also test my fix on your board?
Thanks for figuring this out!
When I was upstreaming support, I noticed __sdhci_execute_tuning() in
T-Head's version of sdhci-of-dwcmshc.c seemed to duplicate what already
existed in drivers/mmc/host/sdhci.c. I had thought T-Head copied it
because it was a static function.
9cc811a342be ("mmc: sdhci: add __sdhci_execute_tuning() to header")
allowed me to remove __sdhci_execute_tuning() from sdhci-of-dwcmshc.
However, I overlooked this resulted in changing the tuning loop from
128 back to the upstream default of 40.
Before this change, the microSD did work for me on the lpi4 but I would
see the following:
[ 4.182483] mmc1: Tuning failed, falling back to fixed sampling clock
[ 4.189022] sdhci-dwcmshc ffe7090000.mmc: tuning failed: -11
[ 4.194734] mmc1: tuning execution failed: -5
[ 4.287899] mmc1: new high speed SDHC card at address aaaa
[ 4.299763] mmcblk1: mmc1:aaaa SD32G 29.7 GiB
[ 4.316963] mmcblk1: p1 p2
root@lpi4amain:~# cat /sys/kernel/debug/mmc1/ios
clock: 50000000 Hz
actual clock: 49500000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 2 (sd high-speed)
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
With the change to 128, I no longer see the tuning failure and the
microSD continues to work okay:
[ 4.307040] mmc1: new ultra high speed SDR104 SDHC card at address aaaa
[ 4.320462] mmcblk1: mmc1:aaaa SD32G 29.7 GiB
[ 4.338646] mmcblk1: p1 p2
root@lpi4amain:/sys/kernel/debug/mmc1# cat ios
clock: 198000000 Hz
actual clock: 198000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
This has the benefit of the card now works at 198 MHz in SDR104 mode
instead of 50 MHz when tuning failed.
Tested-by: Drew Fustini <[email protected]>
thanks,
drew
On Sat, 2024-03-23 at 18:25 -0700, Drew Fustini wrote:
> On Wed, Mar 20, 2024 at 03:28:19PM +0300, Maxim Kiselev wrote:
> > Hi Xi, Drew
> >
> > I have the same problem with SD on my LicheePi 4A.
> >
> > After some investigations I found how to fix this tuning error.
> > Here is the patch that increases tuning loop count from
> > 40(MAX_TUNING_LOOP at sdhci.c) to 128.
> >
> > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c
> > b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > index 8d6cfb648096..da8f5820fb69 100644
> > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
> > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
> > @@ -706,6 +706,7 @@ static int th1520_execute_tuning(struct
> > sdhci_host
> > *host, u32 opcode)
> >
> > /* perform tuning */
> > sdhci_start_tuning(host);
> > + host->tuning_loop_count = 128:
> > host->tuning_err = __sdhci_execute_tuning(host, opcode);
> > if (host->tuning_err) {
> > /* disable auto-tuning upon tuning error */
> >
> > After that change tuning works fine. The same value of loop count is
> > used in RevyOS BSP
> > https://github.com/revyos/thead-kernel/blob/c6d4e5df18a17903d012ffd89e67d0ee5ce6cf2d/drivers/mmc/host/sdhci-of-dwcmshc.c#L185
> >
> > Honestly, it looks a little bit strange for me.
> >
> > It seems that the tuning algorithm requires to move through
> > all the taps of delay line(128 taps?) even if we use THRESHOLD_MODE
> > instend LARGEST_WIN_MODE (I mean bit 2 in AT_CTRL_R(0x540)
> > register).
> >
> > Xi, could you also test my fix on your board?
It works for me as well. I'm now getting:
[ 0.854357] mmc1: new ultra high speed SDR104 SDXC card at address aaaa
[ 0.862267] mmcblk1: mmc1:aaaa SR256 238 GiB
[ 0.876623] mmcblk1: p1
Tested-by: Xi Ruoyao <[email protected]>
Thanks a lot!
> Thanks for figuring this out!
>
> When I was upstreaming support, I noticed __sdhci_execute_tuning() in
> T-Head's version of sdhci-of-dwcmshc.c seemed to duplicate what already
> existed in drivers/mmc/host/sdhci.c. I had thought T-Head copied it
> because it was a static function.
>
> 9cc811a342be ("mmc: sdhci: add __sdhci_execute_tuning() to header")
> allowed me to remove __sdhci_execute_tuning() from sdhci-of-dwcmshc.
> However, I overlooked this resulted in changing the tuning loop from
> 128 back to the upstream default of 40.
>
> Before this change, the microSD did work for me on the lpi4 but I would
> see the following:
>
> [ 4.182483] mmc1: Tuning failed, falling back to fixed sampling
> clock
> [ 4.189022] sdhci-dwcmshc ffe7090000.mmc: tuning failed: -11
> [ 4.194734] mmc1: tuning execution failed: -5
> [ 4.287899] mmc1: new high speed SDHC card at address aaaa
> [ 4.299763] mmcblk1: mmc1:aaaa SD32G 29.7 GiB
> [ 4.316963] mmcblk1: p1 p2
>
> root@lpi4amain:~# cat /sys/kernel/debug/mmc1/ios
> clock: 50000000 Hz
> actual clock: 49500000 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 2 (4 bits)
> timing spec: 2 (sd high-speed)
> signal voltage: 0 (3.30 V)
> driver type: 0 (driver type B)
>
> With the change to 128, I no longer see the tuning failure and the
> microSD continues to work okay:
>
> [ 4.307040] mmc1: new ultra high speed SDR104 SDHC card at address
> aaaa
> [ 4.320462] mmcblk1: mmc1:aaaa SD32G 29.7 GiB
> [ 4.338646] mmcblk1: p1 p2
>
> root@lpi4amain:/sys/kernel/debug/mmc1# cat ios
> clock: 198000000 Hz
> actual clock: 198000000 Hz
> vdd: 21 (3.3 ~ 3.4 V)
> bus mode: 2 (push-pull)
> chip select: 0 (don't care)
> power mode: 2 (on)
> bus width: 2 (4 bits)
> timing spec: 6 (sd uhs SDR104)
> signal voltage: 1 (1.80 V)
> driver type: 0 (driver type B)
>
> This has the benefit of the card now works at 198 MHz in SDR104 mode
> instead of 50 MHz when tuning failed.
>
> Tested-by: Drew Fustini <[email protected]>
--
Xi Ruoyao <[email protected]>
School of Aerospace Science and Technology, Xidian University