This patch series adds the relevant phy and controller
configurations for enabling USB on IPQ9754
Depends on:
https://lore.kernel.org/all/[email protected]/
Varadarajan Narayanan (8):
usb: dwc3: core: Handle fladj becoming zero
dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
clk: qcom: gcc-ipq9574: Add USB related clocks
phy: qcom-qusb2: add QUSB2 support for IPQ9574
phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
arm64: dts: qcom: ipq9574: Add USB related nodes
arm64: dts: qcom: ipq9574: Enable USB
.../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 1 +
.../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 4 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++
drivers/clk/qcom/gcc-ipq9574.c | 35 ++++++
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 130 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +
drivers/usb/dwc3/core.c | 27 +++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
9 files changed, 295 insertions(+)
--
2.7.4
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
index e81a382..fef0572 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml
@@ -21,6 +21,7 @@ properties:
enum:
- qcom,ipq6018-qmp-usb3-phy
- qcom,ipq8074-qmp-usb3-phy
+ - qcom,ipq9574-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,qcm2290-qmp-usb3-phy
--
2.7.4
Document the compatible string used for the qusb2 phy in IPQ9574.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index 7f403e7..c426f78 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -25,6 +25,7 @@ properties:
- qcom,qcm2290-qusb2-phy
- qcom,sdm660-qusb2-phy
- qcom,ipq6018-qusb2-phy
+ - qcom,ipq9574-qusb2-phy
- qcom,sm4250-qusb2-phy
- qcom,sm6115-qusb2-phy
- items:
--
2.7.4
Add the clocks needed for enabling USB in IPQ9574
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
drivers/clk/qcom/gcc-ipq9574.c | 35 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
2 files changed, 37 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 1bf33d5..85cc6a5 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -2041,6 +2041,39 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &usb0_pipe_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_sleep_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
@@ -4008,6 +4041,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index c89e96d..96b7c0b 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -214,4 +214,6 @@
#define GCC_SNOC_PCIE1_1LANE_S_CLK 205
#define GCC_SNOC_PCIE2_2LANE_S_CLK 206
#define GCC_SNOC_PCIE3_2LANE_S_CLK 207
+#define GCC_USB0_PIPE_CLK 208
+#define GCC_USB0_SLEEP_CLK 209
#endif
--
2.7.4
In dwc3_ref_clk_period, the computation
fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
fladj -= 125000;
could turn out to be zero. If fladj is zero, the following
FIELD_PREP clears out that field and the user overridden value
set in the DTS using "snps,quirk-frame-length-adjustment" is
lost. Ensure to retain the user overridden value if the above
evaluates to 0.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
drivers/usb/dwc3/core.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 476b636..63af83b 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -401,6 +401,33 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc)
fladj -= 125000;
/*
+ * Since rate = NSEC_PER_SEC / period and period = NSEC_PER_SEC / rate
+ * above calculation could turn out to be zero.
+ *
+ * if (dwc->ref_clk)
+ * 125000 * NSEC_PER_SEC 125000 * NSEC_PER_SEC
+ * --------------------- => ---------------------
+ * rate * period rate * NSEC_PER_SEC
+ * ------------
+ * rate
+ * else
+ * 125000 * NSEC_PER_SEC 125000 * NSEC_PER_SEC
+ * --------------------- => ---------------------
+ * rate * period NSEC_PER_SEC * period
+ * ------------
+ * period
+ * Hence, the calculation
+ * div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period)
+ * returns 125000ULL and fladj -= 125000 sets fladj to zero.
+ * If fladj is zero, the following FIELD_PREP clears out that
+ * field and the user overridden value set in the DTS using
+ * "snps,quirk-frame-length-adjustment" is lost. Ensure to retain
+ * the user overridden value if the above calculation evaluates to 0.
+ */
+ if (fladj == 0)
+ fladj = FIELD_GET(DWC3_GFLADJ_REFCLK_FLADJ_MASK, dwc->fladj);
+
+ /*
* The documented 240MHz constant is scaled by 2 to get PLS1 as well.
*/
decr = 480000000 / rate;
--
2.7.4
Add USB phy and controller related nodes
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2bb4053..319b5bd 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -215,6 +215,98 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ ssphy_0: ssphy@7D000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x7D000 0x1C4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: lane@7D200 {
+ reg = <0x0007D200 0x130>, /* Tx */
+ <0x0007D400 0x200>, /* Rx */
+ <0x0007D800 0x1F8>, /* PCS */
+ <0x0007D600 0x044>; /* PCS misc */
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: qusb@7B000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x07B000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ usb3: usb3@8A00000 {
+ compatible = "qcom,dwc3";
+ reg = <0x8AF8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "sys_noc_axi",
+ "anoc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <200000000>,
+ <200000000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ dwc_0: dwc3@8A00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8A00000 0xcd00>;
+ clock-names = "ref";
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,dis_ep_cache_eviction;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
+ dr_mode = "host";
+ };
+ };
+
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1bc>; /* Serdes PLL */
--
2.7.4
Turn on USB related nodes
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
index 8a6caae..6a06ca4 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -121,3 +121,7 @@
&xo_board_clk {
clock-frequency = <24000000>;
};
+
+&usb3 { status = "ok"; };
+&ssphy_0 { status = "ok"; };
+&qusb_phy_0 { status = "ok"; };
--
2.7.4
Add the phy init sequence for the Super Speed ports found
on IPQ9574.
Signed-off-by: Sivaprakash Murugesan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 2ef638b..c59413b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -915,6 +915,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
.compatible = "qcom,msm8953-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qusb2-phy",
+ .data = &ipq6018_phy_cfg,
+ }, {
.compatible = "qcom,msm8996-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
--
2.7.4
Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
Reused clock and reset list from existing targets.
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 130 ++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index a49711c..a44c15b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -91,9 +91,15 @@ enum qphy_reg_layout {
/* PCS registers */
QPHY_SW_RESET,
QPHY_START_CTRL,
+ QPHY_FLL_CNTRL1,
+ QPHY_FLL_CNTRL2,
+ QPHY_FLL_CNT_VAL_L,
+ QPHY_FLL_CNT_VAL_H_TOL,
+ QPHY_FLL_MAN_CODE,
QPHY_PCS_STATUS,
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
QPHY_PCS_POWER_DOWN_CONTROL,
/* Keep last to ensure regs_layout arrays are properly initialized */
QPHY_LAYOUT_SIZE
@@ -139,6 +145,103 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
};
+static const unsigned int usb3phy_regs_layout[] = {
+ [QPHY_FLL_CNTRL1] = 0xc0,
+ [QPHY_FLL_CNTRL2] = 0xc4,
+ [QPHY_FLL_CNT_VAL_L] = 0xc8,
+ [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
+ [QPHY_FLL_MAN_CODE] = 0xd0,
+ [QPHY_SW_RESET] = 0x00,
+ [QPHY_START_CTRL] = 0x08,
+ [QPHY_PCS_STATUS] = 0x17c,
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1558,6 +1661,10 @@ static const char * const qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll",
};
+static const char * const ipq9574_phy_clk_l[] = {
+ "aux", "cfg_ahb",
+};
+
static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
.serdes = 0,
.pcs = 0x0200,
@@ -1939,6 +2046,26 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
.regs = qmp_v3_usb3phy_regs_layout,
};
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+ .lanes = 1,
+
+ .serdes_tbl = ipq9574_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+ .tx_tbl = ipq9574_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+ .rx_tbl = ipq9574_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+ .pcs_tbl = ipq9574_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+ .clk_list = ipq9574_phy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = usb3phy_regs_layout,
+};
+
static void qmp_usb_configure_lane(void __iomem *base,
const struct qmp_phy_init_tbl tbl[],
int num,
@@ -2607,6 +2734,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
.compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
.data = &sc8280xp_usb3_uniphy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qmp-usb3-phy",
+ .data = &ipq9574_usb3phy_cfg,
+ }, {
.compatible = "qcom,sdm845-qmp-usb3-phy",
.data = &qmp_v3_usb3phy_cfg,
}, {
--
2.7.4
On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
<[email protected]> wrote:
>
> Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> Reused clock and reset list from existing targets.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 130 ++++++++++++++++++++++++++++++++
> 1 file changed, 130 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> index a49711c..a44c15b 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> @@ -91,9 +91,15 @@ enum qphy_reg_layout {
> /* PCS registers */
> QPHY_SW_RESET,
> QPHY_START_CTRL,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
You don't seem to be using indirect register addressing for these
registers, so these bits are unused and can be dropped.
> QPHY_PCS_STATUS,
> QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> QPHY_PCS_POWER_DOWN_CONTROL,
> /* Keep last to ensure regs_layout arrays are properly initialized */
> QPHY_LAYOUT_SIZE
> @@ -139,6 +145,103 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> };
>
> +static const unsigned int usb3phy_regs_layout[] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> @@ -1558,6 +1661,10 @@ static const char * const qmp_phy_vreg_l[] = {
> "vdda-phy", "vdda-pll",
> };
>
> +static const char * const ipq9574_phy_clk_l[] = {
Please move clocks to the clocks section.
> + "aux", "cfg_ahb",
> +};
> +
> static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> .serdes = 0,
> .pcs = 0x0200,
> @@ -1939,6 +2046,26 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
> .regs = qmp_v3_usb3phy_regs_layout,
> };
>
> +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
Please keep the data sorted.
> + .lanes = 1,
> +
> + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> + .tx_tbl = ipq9574_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> + .rx_tbl = ipq9574_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> + .clk_list = ipq9574_phy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +};
You will get an undefined symbol error here.
> +
> static void qmp_usb_configure_lane(void __iomem *base,
> const struct qmp_phy_init_tbl tbl[],
> int num,
> @@ -2607,6 +2734,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
> .data = &sc8280xp_usb3_uniphy_cfg,
> }, {
> + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> + .data = &ipq9574_usb3phy_cfg,
> + }, {
Please choose a less random place for your driver data. The match
table is sorted, please keep it this way.
> .compatible = "qcom,sdm845-qmp-usb3-phy",
> .data = &qmp_v3_usb3phy_cfg,
> }, {
> --
> 2.7.4
>
--
With best wishes
Dmitry
On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
<[email protected]> wrote:
>
> Add the phy init sequence for the Super Speed ports found
> on IPQ9574.
>
> Signed-off-by: Sivaprakash Murugesan <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 2ef638b..c59413b 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -915,6 +915,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
> .compatible = "qcom,msm8953-qusb2-phy",
> .data = &msm8996_phy_cfg,
> }, {
> + .compatible = "qcom,ipq9574-qusb2-phy",
> + .data = &ipq6018_phy_cfg,
> + }, {
The table is sorted. Please keep it this way.
> .compatible = "qcom,msm8996-qusb2-phy",
> .data = &msm8996_phy_cfg,
> }, {
> --
> 2.7.4
>
--
With best wishes
Dmitry
On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
<[email protected]> wrote:
>
> Turn on USB related nodes
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> index 8a6caae..6a06ca4 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -121,3 +121,7 @@
> &xo_board_clk {
> clock-frequency = <24000000>;
> };
> +
> +&usb3 { status = "ok"; };
> +&ssphy_0 { status = "ok"; };
> +&qusb_phy_0 { status = "ok"; };
Please follow an example of how it is done on other platforms. DT
nodes are sorted, newlines and empty lines are inserted in proper
places.
> --
> 2.7.4
>
--
With best wishes
Dmitry
On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
<[email protected]> wrote:
>
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..319b5bd 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -215,6 +215,98 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + ssphy_0: ssphy@7D000 {
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x7D000 0x1C4>;
> + #clock-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy","common";
> + status = "disabled";
> +
> + usb0_ssphy: lane@7D200 {
Please use newer style device bindings for new PHYs.
> + reg = <0x0007D200 0x130>, /* Tx */
> + <0x0007D400 0x200>, /* Rx */
> + <0x0007D800 0x1F8>, /* PCS */
> + <0x0007D600 0x044>; /* PCS misc */
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_usb0_pipe_clk_src";
No, this clock doesn't originate from gcc, so the gcc prefix is incorrect.
> + };
> + };
> +
> + qusb_phy_0: qusb@7B000 {
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x07B000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + usb3: usb3@8A00000 {
You know the drill. This node is in the wrong place.
> + compatible = "qcom,dwc3";
> + reg = <0x8AF8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
Please fix the indentation of the lists.
> +
> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
Why do you assign clock rates to the NOC clocks? Should they be set
using the interconnect instead?
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <200000000>,
> + <200000000>,
> + <24000000>;
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: dwc3@8A00000 {
> + compatible = "snps,dwc3";
> + reg = <0x8A00000 0xcd00>;
> + clock-names = "ref";
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
clocks before clock-names
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
> + phy-names = "usb2-phy", "usb3-phy";
> + tx-fifo-resize;
> + snps,dis_ep_cache_eviction;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
> + dr_mode = "host";
> + };
> + };
> +
> pcie0_phy: phy@84000 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> --
> 2.7.4
>
--
With best wishes
Dmitry
On Thu, 2 Mar 2023 at 11:56, Varadarajan Narayanan
<[email protected]> wrote:
>
> Document the compatible string used for the qusb2 phy in IPQ9574.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> index 7f403e7..c426f78 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> @@ -25,6 +25,7 @@ properties:
> - qcom,qcm2290-qusb2-phy
> - qcom,sdm660-qusb2-phy
> - qcom,ipq6018-qusb2-phy
Please movef ipq6018 to the proper place and then put ipq9574 next to it.
> + - qcom,ipq9574-qusb2-phy
> - qcom,sm4250-qusb2-phy
> - qcom,sm6115-qusb2-phy
> - items:
> --
> 2.7.4
>
--
With best wishes
Dmitry
On Thu, 2 Mar 2023 at 11:56, Varadarajan Narayanan
<[email protected]> wrote:
>
> Add the clocks needed for enabling USB in IPQ9574
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> drivers/clk/qcom/gcc-ipq9574.c | 35 ++++++++++++++++++++++++++++
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
> 2 files changed, 37 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 1bf33d5..85cc6a5 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -2041,6 +2041,39 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
> },
> };
>
> +static struct clk_branch gcc_usb0_pipe_clk = {
> + .halt_reg = 0x2c054,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x2c054,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb0_pipe_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &usb0_pipe_clk_src.clkr.hw },
Please move the closing bracket to the next line.
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_sleep_clk = {
> + .halt_reg = 0x2c058,
> + .clkr = {
> + .enable_reg = 0x2c058,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb0_sleep_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_sleep_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
> F(144000, P_XO, 16, 12, 125),
> F(400000, P_XO, 12, 1, 5),
> @@ -4008,6 +4041,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
> [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
> [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
> + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
> + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
> [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index c89e96d..96b7c0b 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -214,4 +214,6 @@
> #define GCC_SNOC_PCIE1_1LANE_S_CLK 205
> #define GCC_SNOC_PCIE2_2LANE_S_CLK 206
> #define GCC_SNOC_PCIE3_2LANE_S_CLK 207
> +#define GCC_USB0_PIPE_CLK 208
> +#define GCC_USB0_SLEEP_CLK 209
> #endif
> --
> 2.7.4
>
--
With best wishes
Dmitry
On 02/03/2023 10:55, Varadarajan Narayanan wrote:
> Document the compatible string used for the qusb2 phy in IPQ9574.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
I just acked the same patch... what's happening here?
Best regards,
Krzysztof
On 02/03/2023 10:55, Varadarajan Narayanan wrote:
> Turn on USB related nodes
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> index 8a6caae..6a06ca4 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -121,3 +121,7 @@
> &xo_board_clk {
> clock-frequency = <24000000>;
> };
> +
> +&usb3 { status = "ok"; };
> +&ssphy_0 { status = "ok"; };
> +&qusb_phy_0 { status = "ok"; };
I already replied to this... so just NAK. Explanation is in my previous
reply to the same mail.
Best regards,
Krzysztof
On 02/03/2023 10:55, Varadarajan Narayanan wrote:
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..319b5bd 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -215,6 +215,98 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + ssphy_0: ssphy@7D000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x7D000 0x1C4>;
> + #clock-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> + clock-names = "aux", "cfg_ahb";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy","common";
> + status = "disabled";
> +
> + usb0_ssphy: lane@7D200 {
> + reg = <0x0007D200 0x130>, /* Tx */
> + <0x0007D400 0x200>, /* Rx */
> + <0x0007D800 0x1F8>, /* PCS */
> + <0x0007D600 0x044>; /* PCS misc */
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "gcc_usb0_pipe_clk_src";
> + };
> + };
> +
> + qusb_phy_0: qusb@7B000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x07B000 0x180>;
Lowercase hex everywhere.
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb", "ref";
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + usb3: usb3@8A00000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
> + compatible = "qcom,dwc3";
> + reg = <0x8AF8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <200000000>,
> + <200000000>,
> + <24000000>;
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: dwc3@8A00000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).
Best regards,
Krzysztof
On 3/2/2023 9:53 PM, Dmitry Baryshkov wrote:
> On Thu, 2 Mar 2023 at 11:56, Varadarajan Narayanan
> <[email protected]> wrote:
>> Document the compatible string used for the qusb2 phy in IPQ9574.
>>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>> index 7f403e7..c426f78 100644
>> --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>> @@ -25,6 +25,7 @@ properties:
>> - qcom,qcm2290-qusb2-phy
>> - qcom,sdm660-qusb2-phy
>> - qcom,ipq6018-qusb2-phy
> Please movef ipq6018 to the proper place and then put ipq9574 next to it.
Sure.
Thanks
Varada
>
>> + - qcom,ipq9574-qusb2-phy
>> - qcom,sm4250-qusb2-phy
>> - qcom,sm6115-qusb2-phy
>> - items:
>> --
>> 2.7.4
>>
>
On 3/2/2023 9:54 PM, Dmitry Baryshkov wrote:
> On Thu, 2 Mar 2023 at 11:56, Varadarajan Narayanan
> <[email protected]> wrote:
>> Add the clocks needed for enabling USB in IPQ9574
>>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> drivers/clk/qcom/gcc-ipq9574.c | 35 ++++++++++++++++++++++++++++
>> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
>> 2 files changed, 37 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
>> index 1bf33d5..85cc6a5 100644
>> --- a/drivers/clk/qcom/gcc-ipq9574.c
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -2041,6 +2041,39 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
>> },
>> };
>>
>> +static struct clk_branch gcc_usb0_pipe_clk = {
>> + .halt_reg = 0x2c054,
>> + .halt_check = BRANCH_HALT_DELAY,
>> + .clkr = {
>> + .enable_reg = 0x2c054,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb0_pipe_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &usb0_pipe_clk_src.clkr.hw },
> Please move the closing bracket to the next line.
Sure. Will post a revised patch.
Thanks
Varada
>
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_usb0_sleep_clk = {
>> + .halt_reg = 0x2c058,
>> + .clkr = {
>> + .enable_reg = 0x2c058,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gcc_usb0_sleep_clk",
>> + .parent_hws = (const struct clk_hw *[]){
>> + &gcc_sleep_clk_src.clkr.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + .ops = &clk_branch2_ops,
>> + },
>> + },
>> +};
>> +
>> static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
>> F(144000, P_XO, 16, 12, 125),
>> F(400000, P_XO, 12, 1, 5),
>> @@ -4008,6 +4041,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
>> [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
>> [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
>> [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
>> + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
>> + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
>> [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
>> [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
>> [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
>> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> index c89e96d..96b7c0b 100644
>> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> @@ -214,4 +214,6 @@
>> #define GCC_SNOC_PCIE1_1LANE_S_CLK 205
>> #define GCC_SNOC_PCIE2_2LANE_S_CLK 206
>> #define GCC_SNOC_PCIE3_2LANE_S_CLK 207
>> +#define GCC_USB0_PIPE_CLK 208
>> +#define GCC_USB0_SLEEP_CLK 209
>> #endif
>> --
>> 2.7.4
>>
>
On 3/2/2023 9:47 PM, Dmitry Baryshkov wrote:
> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
> <[email protected]> wrote:
>> Add the phy init sequence for the Super Speed ports found
>> on IPQ9574.
>>
>> Signed-off-by: Sivaprakash Murugesan <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index 2ef638b..c59413b 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -915,6 +915,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
>> .compatible = "qcom,msm8953-qusb2-phy",
>> .data = &msm8996_phy_cfg,
>> }, {
>> + .compatible = "qcom,ipq9574-qusb2-phy",
>> + .data = &ipq6018_phy_cfg,
>> + }, {
> The table is sorted. Please keep it this way.
Sorry, didn't notice that. Will post a revised patch.
Thanks
Varada
>
>> .compatible = "qcom,msm8996-qusb2-phy",
>> .data = &msm8996_phy_cfg,
>> }, {
>> --
>> 2.7.4
>>
>
On 3/2/2023 9:46 PM, Dmitry Baryshkov wrote:
> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
> <[email protected]> wrote:
>> Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
>> Reused clock and reset list from existing targets.
>>
>> Signed-off-by: Praveenkumar I <[email protected]>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 130 ++++++++++++++++++++++++++++++++
>> 1 file changed, 130 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
>> index a49711c..a44c15b 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
>> @@ -91,9 +91,15 @@ enum qphy_reg_layout {
>> /* PCS registers */
>> QPHY_SW_RESET,
>> QPHY_START_CTRL,
>> + QPHY_FLL_CNTRL1,
>> + QPHY_FLL_CNTRL2,
>> + QPHY_FLL_CNT_VAL_L,
>> + QPHY_FLL_CNT_VAL_H_TOL,
>> + QPHY_FLL_MAN_CODE,
> You don't seem to be using indirect register addressing for these
> registers, so these bits are unused and can be dropped.
>
>> QPHY_PCS_STATUS,
>> QPHY_PCS_AUTONOMOUS_MODE_CTRL,
>> QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
>> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
>> QPHY_PCS_POWER_DOWN_CONTROL,
>> /* Keep last to ensure regs_layout arrays are properly initialized */
>> QPHY_LAYOUT_SIZE
>> @@ -139,6 +145,103 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
>> [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
>> };
>>
>> +static const unsigned int usb3phy_regs_layout[] = {
>> + [QPHY_FLL_CNTRL1] = 0xc0,
>> + [QPHY_FLL_CNTRL2] = 0xc4,
>> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
>> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
>> + [QPHY_FLL_MAN_CODE] = 0xd0,
>> + [QPHY_SW_RESET] = 0x00,
>> + [QPHY_START_CTRL] = 0x08,
>> + [QPHY_PCS_STATUS] = 0x17c,
>> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
>> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
>> + [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
>> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
>> +};
>> +
>> +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
>> + /* PLL and Loop filter settings */
>> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
>> + /* SSC settings */
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
>> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
>> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
>> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
>> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
>> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
>> +};
>> +
>> +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
>> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
>> +};
>> +
>> static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
>> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
>> QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
>> @@ -1558,6 +1661,10 @@ static const char * const qmp_phy_vreg_l[] = {
>> "vdda-phy", "vdda-pll",
>> };
>>
>> +static const char * const ipq9574_phy_clk_l[] = {
> Please move clocks to the clocks section.
>
>> + "aux", "cfg_ahb",
>> +};
>> +
>> static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
>> .serdes = 0,
>> .pcs = 0x0200,
>> @@ -1939,6 +2046,26 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
>> .regs = qmp_v3_usb3phy_regs_layout,
>> };
>>
>> +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> Please keep the data sorted.
>
>> + .lanes = 1,
>> +
>> + .serdes_tbl = ipq9574_usb3_serdes_tbl,
>> + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
>> + .tx_tbl = ipq9574_usb3_tx_tbl,
>> + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
>> + .rx_tbl = ipq9574_usb3_rx_tbl,
>> + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
>> + .pcs_tbl = ipq9574_usb3_pcs_tbl,
>> + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
>> + .clk_list = ipq9574_phy_clk_l,
>> + .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
>> + .reset_list = msm8996_usb3phy_reset_l,
>> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
>> + .vreg_list = qmp_phy_vreg_l,
>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>> + .regs = usb3phy_regs_layout,
>> +};
> You will get an undefined symbol error here.
>
>> +
>> static void qmp_usb_configure_lane(void __iomem *base,
>> const struct qmp_phy_init_tbl tbl[],
>> int num,
>> @@ -2607,6 +2734,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
>> .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
>> .data = &sc8280xp_usb3_uniphy_cfg,
>> }, {
>> + .compatible = "qcom,ipq9574-qmp-usb3-phy",
>> + .data = &ipq9574_usb3phy_cfg,
>> + }, {
> Please choose a less random place for your driver data. The match
> table is sorted, please keep it this way.
>
>> .compatible = "qcom,sdm845-qmp-usb3-phy",
>> .data = &qmp_v3_usb3phy_cfg,
>> }, {
>> --
>> 2.7.4
Thanks for the feedback. Will make the corrections and post a revised patch.
Thanks
Varada
On 3/3/2023 1:09 PM, Krzysztof Kozlowski wrote:
> On 02/03/2023 10:55, Varadarajan Narayanan wrote:
>> Add USB phy and controller related nodes
>>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 92 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 2bb4053..319b5bd 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -215,6 +215,98 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>>
>> + ssphy_0: ssphy@7D000 {
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
>
>> + compatible = "qcom,ipq9574-qmp-usb3-phy";
>> + reg = <0x7D000 0x1C4>;
>> + #clock-cells = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_USB0_AUX_CLK>,
>> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
>> + clock-names = "aux", "cfg_ahb";
>> +
>> + resets = <&gcc GCC_USB0_PHY_BCR>,
>> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
>> + reset-names = "phy","common";
>> + status = "disabled";
>> +
>> + usb0_ssphy: lane@7D200 {
>> + reg = <0x0007D200 0x130>, /* Tx */
>> + <0x0007D400 0x200>, /* Rx */
>> + <0x0007D800 0x1F8>, /* PCS */
>> + <0x0007D600 0x044>; /* PCS misc */
>> + #phy-cells = <0>;
>> + clocks = <&gcc GCC_USB0_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_usb0_pipe_clk_src";
>> + };
>> + };
>> +
>> + qusb_phy_0: qusb@7B000 {
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
>
>> + compatible = "qcom,ipq9574-qusb2-phy";
>> + reg = <0x07B000 0x180>;
> Lowercase hex everywhere.
>
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
>> + <&xo_board_clk>;
>> + clock-names = "cfg_ahb", "ref";
>> +
>> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
>> + status = "disabled";
>> + };
>> +
>> + usb3: usb3@8A00000 {
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
>
>> + compatible = "qcom,dwc3";
>> + reg = <0x8AF8800 0x400>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_SNOC_USB_CLK>,
>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>> + <&gcc GCC_USB0_MASTER_CLK>,
>> + <&gcc GCC_USB0_SLEEP_CLK>,
>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> +
>> + clock-names = "sys_noc_axi",
>> + "anoc_axi",
>> + "master",
>> + "sleep",
>> + "mock_utmi";
>> +
>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>> + <&gcc GCC_USB0_MASTER_CLK>,
>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> + assigned-clock-rates = <200000000>,
>> + <200000000>,
>> + <200000000>,
>> + <24000000>;
>> +
>> + resets = <&gcc GCC_USB_BCR>;
>> + status = "disabled";
>> +
>> + dwc_0: dwc3@8A00000 {
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
>
>
> Best regards,
> Krzysztof
>
Sorry. Will rectify and post a new version.
Thank
Varada
On 3/2/2023 9:48 PM, Dmitry Baryshkov wrote:
> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
> <[email protected]> wrote:
>> Turn on USB related nodes
>>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> index 8a6caae..6a06ca4 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -121,3 +121,7 @@
>> &xo_board_clk {
>> clock-frequency = <24000000>;
>> };
>> +
>> +&usb3 { status = "ok"; };
>> +&ssphy_0 { status = "ok"; };
>> +&qusb_phy_0 { status = "ok"; };
> Please follow an example of how it is done on other platforms. DT
> nodes are sorted, newlines and empty lines are inserted in proper
> places.
>
>> --
>> 2.7.4
Will rectify and post a new version.
Thanks
Varada
>
Dmitry,
On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
> <[email protected]> wrote:
>> Add USB phy and controller related nodes
>>
>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 92 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 2bb4053..319b5bd 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -215,6 +215,98 @@
>> #size-cells = <1>;
>> ranges = <0 0 0 0xffffffff>;
>>
>> + ssphy_0: ssphy@7D000 {
>> + compatible = "qcom,ipq9574-qmp-usb3-phy";
>> + reg = <0x7D000 0x1C4>;
>> + #clock-cells = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_USB0_AUX_CLK>,
>> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
>> + clock-names = "aux", "cfg_ahb";
>> +
>> + resets = <&gcc GCC_USB0_PHY_BCR>,
>> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
>> + reset-names = "phy","common";
>> + status = "disabled";
>> +
>> + usb0_ssphy: lane@7D200 {
> Please use newer style device bindings for new PHYs.
>
>> + reg = <0x0007D200 0x130>, /* Tx */
>> + <0x0007D400 0x200>, /* Rx */
>> + <0x0007D800 0x1F8>, /* PCS */
>> + <0x0007D600 0x044>; /* PCS misc */
>> + #phy-cells = <0>;
>> + clocks = <&gcc GCC_USB0_PIPE_CLK>;
>> + clock-names = "pipe0";
>> + clock-output-names = "gcc_usb0_pipe_clk_src";
> No, this clock doesn't originate from gcc, so the gcc prefix is incorrect.
>
>> + };
>> + };
>> +
>> + qusb_phy_0: qusb@7B000 {
>> + compatible = "qcom,ipq9574-qusb2-phy";
>> + reg = <0x07B000 0x180>;
>> + #phy-cells = <0>;
>> +
>> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
>> + <&xo_board_clk>;
>> + clock-names = "cfg_ahb", "ref";
>> +
>> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
>> + status = "disabled";
>> + };
>> +
>> + usb3: usb3@8A00000 {
> You know the drill. This node is in the wrong place.
>
>> + compatible = "qcom,dwc3";
>> + reg = <0x8AF8800 0x400>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + clocks = <&gcc GCC_SNOC_USB_CLK>,
>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>> + <&gcc GCC_USB0_MASTER_CLK>,
>> + <&gcc GCC_USB0_SLEEP_CLK>,
>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> +
>> + clock-names = "sys_noc_axi",
>> + "anoc_axi",
>> + "master",
>> + "sleep",
>> + "mock_utmi";
> Please fix the indentation of the lists.
>
>> +
>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> Why do you assign clock rates to the NOC clocks? Should they be set
> using the interconnect instead?
The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz respectively
and are not scaled. These clocks are for the interface between the USB
block and the SNOC/ANOC. Do we still need to use interconnect?
>> + <&gcc GCC_USB0_MASTER_CLK>,
>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> + assigned-clock-rates = <200000000>,
>> + <200000000>,
>> + <200000000>,
>> + <24000000>;
>> +
>> + resets = <&gcc GCC_USB_BCR>;
>> + status = "disabled";
>> +
>> + dwc_0: dwc3@8A00000 {
>> + compatible = "snps,dwc3";
>> + reg = <0x8A00000 0xcd00>;
>> + clock-names = "ref";
>> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> clocks before clock-names
>
>> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
>> + phy-names = "usb2-phy", "usb3-phy";
>> + tx-fifo-resize;
>> + snps,dis_ep_cache_eviction;
>> + snps,is-utmi-l1-suspend;
>> + snps,hird-threshold = /bits/ 8 <0x0>;
>> + snps,dis_u2_susphy_quirk;
>> + snps,dis_u3_susphy_quirk;
>> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
>> + dr_mode = "host";
>> + };
>> + };
>> +
>> pcie0_phy: phy@84000 {
>> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> reg = <0x00084000 0x1bc>; /* Serdes PLL */
>> --
>> 2.7.4
Will address these and post a new revision.
Thanks
Varada
On 06/03/2023 13:26, Varadarajan Narayanan wrote:
> Dmitry,
>
> On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
>> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
>> <[email protected]> wrote:
>>> Add USB phy and controller related nodes
>>>
>>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92
>>> +++++++++++++++++++++++++++++++++++
>>> 1 file changed, 92 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> index 2bb4053..319b5bd 100644
>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
[skipped]
>>> + usb3: usb3@8A00000 {
>> You know the drill. This node is in the wrong place.
>>
>>> + compatible = "qcom,dwc3";
>>> + reg = <0x8AF8800 0x400>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>>> +
>>> + clocks = <&gcc GCC_SNOC_USB_CLK>,
>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>> + <&gcc GCC_USB0_SLEEP_CLK>,
>>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>> +
>>> + clock-names = "sys_noc_axi",
>>> + "anoc_axi",
>>> + "master",
>>> + "sleep",
>>> + "mock_utmi";
>> Please fix the indentation of the lists.
>>
>>> +
>>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>> Why do you assign clock rates to the NOC clocks? Should they be set
>> using the interconnect instead?
>
> The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz respectively
> and are not scaled. These clocks are for the interface between the USB
> block and the SNOC/ANOC. Do we still need to use interconnect?
Maybe I misunderstand something here. If the snoc and anoc speeds are at
350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz?
Is it enough to call clk_prepare_enable() for these clocks or the rate
really needs to be set?
>
>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>> + assigned-clock-rates = <200000000>,
>>> + <200000000>,
>>> + <200000000>,
>>> + <24000000>;
>>> +
>>> + resets = <&gcc GCC_USB_BCR>;
>>> + status = "disabled";
>>> +
>>> + dwc_0: dwc3@8A00000 {
>>> + compatible = "snps,dwc3";
>>> + reg = <0x8A00000 0xcd00>;
>>> + clock-names = "ref";
>>> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>> clocks before clock-names
>>
>>> + interrupts = <GIC_SPI 140
>>> IRQ_TYPE_LEVEL_HIGH>;
>>> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
>>> + phy-names = "usb2-phy", "usb3-phy";
>>> + tx-fifo-resize;
>>> + snps,dis_ep_cache_eviction;
>>> + snps,is-utmi-l1-suspend;
>>> + snps,hird-threshold = /bits/ 8 <0x0>;
>>> + snps,dis_u2_susphy_quirk;
>>> + snps,dis_u3_susphy_quirk;
>>> + snps,quirk-frame-length-adjustment =
>>> <0x0A87F0A0>;
>>> + dr_mode = "host";
>>> + };
>>> + };
>>> +
>>> pcie0_phy: phy@84000 {
>>> compatible =
>>> "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>>> reg = <0x00084000 0x1bc>; /* Serdes PLL */
>>> --
>>> 2.7.4
>
> Will address these and post a new revision.
>
> Thanks
>
> Varada
>
--
With best wishes
Dmitry
On 3/6/2023 5:21 PM, Dmitry Baryshkov wrote:
> On 06/03/2023 13:26, Varadarajan Narayanan wrote:
>> Dmitry,
>>
>> On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
>>> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
>>> <[email protected]> wrote:
>>>> Add USB phy and controller related nodes
>>>>
>>>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92
>>>> +++++++++++++++++++++++++++++++++++
>>>> 1 file changed, 92 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> index 2bb4053..319b5bd 100644
>>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>
> [skipped]
>
>
>>>> + usb3: usb3@8A00000 {
>>> You know the drill. This node is in the wrong place.
>>>
>>>> + compatible = "qcom,dwc3";
>>>> + reg = <0x8AF8800 0x400>;
>>>> + #address-cells = <1>;
>>>> + #size-cells = <1>;
>>>> + ranges;
>>>> +
>>>> + clocks = <&gcc GCC_SNOC_USB_CLK>,
>>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>>> + <&gcc GCC_USB0_SLEEP_CLK>,
>>>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>>> +
>>>> + clock-names = "sys_noc_axi",
>>>> + "anoc_axi",
>>>> + "master",
>>>> + "sleep",
>>>> + "mock_utmi";
>>> Please fix the indentation of the lists.
>>>
>>>> +
>>>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
>>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>>> Why do you assign clock rates to the NOC clocks? Should they be set
>>> using the interconnect instead?
>>
>> The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz
>> respectively and are not scaled. These clocks are for the interface
>> between the USB block and the SNOC/ANOC. Do we still need to use
>> interconnect?
>
> Maybe I misunderstand something here. If the snoc and anoc speeds are
> at 350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz?
>
> Is it enough to call clk_prepare_enable() for these clocks or the rate
> really needs to be set?
The rate of 200MHz is not being set for the SNOC/ANOC. It is for the
NIU that connects the USB and SNOC/ANOC. The reason for setting the
rate to 200MHz is to configure the RCG parent for these interface
clocks. That said can we configure this RCG standalone in the driver
and enable these clocks?
Thanks
Varada
>
>
>>
>>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>>> + <&gcc
>>>> GCC_USB0_MOCK_UTMI_CLK>;
>>>> + assigned-clock-rates = <200000000>,
>>>> + <200000000>,
>>>> + <200000000>,
>>>> + <24000000>;
>>>> +
>>>> + resets = <&gcc GCC_USB_BCR>;
>>>> + status = "disabled";
>>>> +
>>>> + dwc_0: dwc3@8A00000 {
>>>> + compatible = "snps,dwc3";
>>>> + reg = <0x8A00000 0xcd00>;
>>>> + clock-names = "ref";
>>>> + clocks = <&gcc
>>>> GCC_USB0_MOCK_UTMI_CLK>;
>>> clocks before clock-names
>>>
>>>> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>>>> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
>>>> + phy-names = "usb2-phy", "usb3-phy";
>>>> + tx-fifo-resize;
>>>> + snps,dis_ep_cache_eviction;
>>>> + snps,is-utmi-l1-suspend;
>>>> + snps,hird-threshold = /bits/ 8 <0x0>;
>>>> + snps,dis_u2_susphy_quirk;
>>>> + snps,dis_u3_susphy_quirk;
>>>> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
>>>> + dr_mode = "host";
>>>> + };
>>>> + };
>>>> +
>>>> pcie0_phy: phy@84000 {
>>>> compatible =
>>>> "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>>>> reg = <0x00084000 0x1bc>; /* Serdes PLL */
>>>> --
>>>> 2.7.4
>>
>> Will address these and post a new revision.
>>
>> Thanks
>>
>> Varada
>>
>
On 07/03/2023 08:36, Varadarajan Narayanan wrote:
>
> On 3/6/2023 5:21 PM, Dmitry Baryshkov wrote:
>> On 06/03/2023 13:26, Varadarajan Narayanan wrote:
>>> Dmitry,
>>>
>>> On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
>>>> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
>>>> <[email protected]> wrote:
>>>>> Add USB phy and controller related nodes
>>>>>
>>>>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92
>>>>> +++++++++++++++++++++++++++++++++++
>>>>> 1 file changed, 92 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>>> index 2bb4053..319b5bd 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> [skipped]
>>
>>
>>>>> + usb3: usb3@8A00000 {
>>>> You know the drill. This node is in the wrong place.
>>>>
>>>>> + compatible = "qcom,dwc3";
>>>>> + reg = <0x8AF8800 0x400>;
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <1>;
>>>>> + ranges;
>>>>> +
>>>>> + clocks = <&gcc GCC_SNOC_USB_CLK>,
>>>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>>>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>>>> + <&gcc GCC_USB0_SLEEP_CLK>,
>>>>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>>>> +
>>>>> + clock-names = "sys_noc_axi",
>>>>> + "anoc_axi",
>>>>> + "master",
>>>>> + "sleep",
>>>>> + "mock_utmi";
>>>> Please fix the indentation of the lists.
>>>>
>>>>> +
>>>>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
>>>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>>>> Why do you assign clock rates to the NOC clocks? Should they be set
>>>> using the interconnect instead?
>>>
>>> The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz
>>> respectively and are not scaled. These clocks are for the interface
>>> between the USB block and the SNOC/ANOC. Do we still need to use
>>> interconnect?
>>
>> Maybe I misunderstand something here. If the snoc and anoc speeds are
>> at 350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz?
>>
>> Is it enough to call clk_prepare_enable() for these clocks or the rate
>> really needs to be set?
>
> The rate of 200MHz is not being set for the SNOC/ANOC. It is for the
> NIU that connects the USB and SNOC/ANOC. The reason for setting the
> rate to 200MHz is to configure the RCG parent for these interface
> clocks. That said can we configure this RCG standalone in the driver
> and enable these clocks?
We discussed this separately with Georgi Djakov. Let me quote his IRC
message: "it sounds like this is for USB port that connects to the NOC.
if bandwidth scaling is not needed (or other interconnect
configuration), then maybe this can go without interconnect provider
driver."
However as we discover more and more about this platform (e.g. PCIe
using the aggre_noc region to setup some magic registers, see [1]), I'm
more and more biased towards suggesting implementing the interconnect
driver to setup all these tiny little things. With the DT tree being an
ABI, it is much preferable to overestimate the needs rather than
underestimating them (and having to cope with the backwards
compatibility issues).
Generally I think that PCIe/USB/whatever should not poke into NoC
registers or NoC/NIU clocks directly (because this is a very
platform-specific item). Rather than that it should tell the
icc/opp/whatever subsystem, "please configure the SoC for me to work".
[1]
https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Thanks
> Varada
>
>
>>
>>
>>>
>>>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>>>> + <&gcc
>>>>> GCC_USB0_MOCK_UTMI_CLK>;
>>>>> + assigned-clock-rates = <200000000>,
>>>>> + <200000000>,
>>>>> + <200000000>,
>>>>> + <24000000>;
>>>>> +
>>>>> + resets = <&gcc GCC_USB_BCR>;
>>>>> + status = "disabled";
>>>>> +
>>>>> + dwc_0: dwc3@8A00000 {
>>>>> + compatible = "snps,dwc3";
>>>>> + reg = <0x8A00000 0xcd00>;
>>>>> + clock-names = "ref";
>>>>> + clocks = <&gcc
>>>>> GCC_USB0_MOCK_UTMI_CLK>;
>>>> clocks before clock-names
>>>>
>>>>> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>>>>> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
>>>>> + phy-names = "usb2-phy", "usb3-phy";
>>>>> + tx-fifo-resize;
>>>>> + snps,dis_ep_cache_eviction;
>>>>> + snps,is-utmi-l1-suspend;
>>>>> + snps,hird-threshold = /bits/ 8 <0x0>;
>>>>> + snps,dis_u2_susphy_quirk;
>>>>> + snps,dis_u3_susphy_quirk;
>>>>> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
>>>>> + dr_mode = "host";
>>>>> + };
>>>>> + };
>>>>> +
>>>>> pcie0_phy: phy@84000 {
>>>>> compatible =
>>>>> "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>>>>> reg = <0x00084000 0x1bc>; /* Serdes PLL */
>>>>> --
>>>>> 2.7.4
>>>
>>> Will address these and post a new revision.
>>>
>>> Thanks
>>>
>>> Varada
>>>
>>
--
With best wishes
Dmitry
On 3/7/2023 5:19 PM, Dmitry Baryshkov wrote:
> On 07/03/2023 08:36, Varadarajan Narayanan wrote:
>>
>> On 3/6/2023 5:21 PM, Dmitry Baryshkov wrote:
>>> On 06/03/2023 13:26, Varadarajan Narayanan wrote:
>>>> Dmitry,
>>>>
>>>> On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
>>>>> On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
>>>>> <[email protected]> wrote:
>>>>>> Add USB phy and controller related nodes
>>>>>>
>>>>>> Signed-off-by: Varadarajan Narayanan <[email protected]>
>>>>>> ---
>>>>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92
>>>>>> +++++++++++++++++++++++++++++++++++
>>>>>> 1 file changed, 92 insertions(+)
>>>>>>
>>>>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>>>> index 2bb4053..319b5bd 100644
>>>>>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>
>>> [skipped]
>>>
>>>
>>>>>> + usb3: usb3@8A00000 {
>>>>> You know the drill. This node is in the wrong place.
>>>>>
>>>>>> + compatible = "qcom,dwc3";
>>>>>> + reg = <0x8AF8800 0x400>;
>>>>>> + #address-cells = <1>;
>>>>>> + #size-cells = <1>;
>>>>>> + ranges;
>>>>>> +
>>>>>> + clocks = <&gcc GCC_SNOC_USB_CLK>,
>>>>>> + <&gcc GCC_ANOC_USB_AXI_CLK>,
>>>>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>>>>> + <&gcc GCC_USB0_SLEEP_CLK>,
>>>>>> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>>>>>> +
>>>>>> + clock-names = "sys_noc_axi",
>>>>>> + "anoc_axi",
>>>>>> + "master",
>>>>>> + "sleep",
>>>>>> + "mock_utmi";
>>>>> Please fix the indentation of the lists.
>>>>>
>>>>>> +
>>>>>> + assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
>>>>>> + <&gcc
>>>>>> GCC_ANOC_USB_AXI_CLK>,
>>>>> Why do you assign clock rates to the NOC clocks? Should they be set
>>>>> using the interconnect instead?
>>>>
>>>> The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz
>>>> respectively and are not scaled. These clocks are for the interface
>>>> between the USB block and the SNOC/ANOC. Do we still need to use
>>>> interconnect?
>>>
>>> Maybe I misunderstand something here. If the snoc and anoc speeds
>>> are at 350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz?
>>>
>>> Is it enough to call clk_prepare_enable() for these clocks or the
>>> rate really needs to be set?
>>
>> The rate of 200MHz is not being set for the SNOC/ANOC. It is for the
>> NIU that connects the USB and SNOC/ANOC. The reason for setting the
>> rate to 200MHz is to configure the RCG parent for these interface
>> clocks. That said can we configure this RCG standalone in the driver
>> and enable these clocks?
>
> We discussed this separately with Georgi Djakov. Let me quote his IRC
> message: "it sounds like this is for USB port that connects to the
> NOC. if bandwidth scaling is not needed (or other interconnect
> configuration), then maybe this can go without interconnect provider
> driver."
>
> However as we discover more and more about this platform (e.g. PCIe
> using the aggre_noc region to setup some magic registers, see [1]),
> I'm more and more biased towards suggesting implementing the
> interconnect driver to setup all these tiny little things. With the DT
> tree being an ABI, it is much preferable to overestimate the needs
> rather than underestimating them (and having to cope with the
> backwards compatibility issues).
>
> Generally I think that PCIe/USB/whatever should not poke into NoC
> registers or NoC/NIU clocks directly (because this is a very
> platform-specific item). Rather than that it should tell the
> icc/opp/whatever subsystem, "please configure the SoC for me to work".
>
> [1]
> https://lore.kernel.org/linux-arm-msm/[email protected]/
Sure, will post a new revision that uses interconnect subsystem.
Thanks
Varada
>>>>>> + <&gcc GCC_USB0_MASTER_CLK>,
>>>>>> + <&gcc
>>>>>> GCC_USB0_MOCK_UTMI_CLK>;
>>>>>> + assigned-clock-rates = <200000000>,
>>>>>> + <200000000>,
>>>>>> + <200000000>,
>>>>>> + <24000000>;
>>>>>> +
>>>>>> + resets = <&gcc GCC_USB_BCR>;
>>>>>> + status = "disabled";
>>>>>> +
>>>>>> + dwc_0: dwc3@8A00000 {
>>>>>> + compatible = "snps,dwc3";
>>>>>> + reg = <0x8A00000 0xcd00>;
>>>>>> + clock-names = "ref";
>>>>>> + clocks = <&gcc
>>>>>> GCC_USB0_MOCK_UTMI_CLK>;
>>>>> clocks before clock-names
>>>>>
>>>>>> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> + phys = <&qusb_phy_0>, <&usb0_ssphy>;
>>>>>> + phy-names = "usb2-phy", "usb3-phy";
>>>>>> + tx-fifo-resize;
>>>>>> + snps,dis_ep_cache_eviction;
>>>>>> + snps,is-utmi-l1-suspend;
>>>>>> + snps,hird-threshold = /bits/ 8
>>>>>> <0x0>;
>>>>>> + snps,dis_u2_susphy_quirk;
>>>>>> + snps,dis_u3_susphy_quirk;
>>>>>> + snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
>>>>>> + dr_mode = "host";
>>>>>> + };
>>>>>> + };
>>>>>> +
>>>>>> pcie0_phy: phy@84000 {
>>>>>> compatible =
>>>>>> "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>>>>>> reg = <0x00084000 0x1bc>; /* Serdes PLL */
>>>>>> --
>>>>>> 2.7.4
>>>>
>>>> Will address these and post a new revision.
>>>>
>>>> Thanks
>>>>
>>>> Varada
>>>>
>>>
>
Dmitry,
On Tue, Mar 07, 2023 at 01:49:40PM +0200, Dmitry Baryshkov wrote:
> On 07/03/2023 08:36, Varadarajan Narayanan wrote:
> >
> >On 3/6/2023 5:21 PM, Dmitry Baryshkov wrote:
> >>On 06/03/2023 13:26, Varadarajan Narayanan wrote:
> >>>Dmitry,
> >>>
> >>>On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
> >>>>On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
> >>>><[email protected]> wrote:
> >>>>>Add USB phy and controller related nodes
> >>>>>
> >>>>>Signed-off-by: Varadarajan Narayanan <[email protected]>
> >>>>>---
> >>>>>? arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92
> >>>>>+++++++++++++++++++++++++++++++++++
> >>>>>? 1 file changed, 92 insertions(+)
> >>>>>
> >>>>>diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >>>>>b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >>>>>index 2bb4053..319b5bd 100644
> >>>>>--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >>>>>+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >>
> >>[skipped]
> >>
> >>
> >>>>>+?????????????? usb3: usb3@8A00000 {
> >>>>You know the drill. This node is in the wrong place.
> >>>>
> >>>>>+?????????????????????? compatible = "qcom,dwc3";
> >>>>>+?????????????????????? reg = <0x8AF8800 0x400>;
> >>>>>+?????????????????????? #address-cells = <1>;
> >>>>>+?????????????????????? #size-cells = <1>;
> >>>>>+?????????????????????? ranges;
> >>>>>+
> >>>>>+?????????????????????? clocks = <&gcc GCC_SNOC_USB_CLK>,
> >>>>>+?????????????????????????????? <&gcc GCC_ANOC_USB_AXI_CLK>,
> >>>>>+?????????????????????????????? <&gcc GCC_USB0_MASTER_CLK>,
> >>>>>+?????????????????????????????? <&gcc GCC_USB0_SLEEP_CLK>,
> >>>>>+?????????????????????????????? <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >>>>>+
> >>>>>+?????????????????????? clock-names = "sys_noc_axi",
> >>>>>+?????????????????????????????? "anoc_axi",
> >>>>>+?????????????????????????????? "master",
> >>>>>+?????????????????????????????? "sleep",
> >>>>>+?????????????????????????????? "mock_utmi";
> >>>>Please fix the indentation of the lists.
> >>>>
> >>>>>+
> >>>>>+?????????????????????? assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
> >>>>>+???????????????????????????????????????? <&gcc GCC_ANOC_USB_AXI_CLK>,
> >>>>Why do you assign clock rates to the NOC clocks? Should they be set
> >>>>using the interconnect instead?
> >>>
> >>>The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz
> >>>respectively and are not scaled. These clocks are for the interface
> >>>between the USB block and the SNOC/ANOC. Do we still need to use
> >>>interconnect?
> >>
> >>Maybe I misunderstand something here. If the snoc and anoc speeds are at
> >>350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz?
> >>
> >>Is it enough to call clk_prepare_enable() for these clocks or the rate
> >>really needs to be set?
> >
> >The rate of 200MHz is not being set for the SNOC/ANOC. It is for the
> >NIU that connects the USB and SNOC/ANOC. The reason for setting the
> >rate to 200MHz is to configure the RCG parent for these interface
> >clocks. That said can we configure this RCG standalone in the driver
> >and enable these clocks?
>
> We discussed this separately with Georgi Djakov. Let me quote his IRC
> message: "it sounds like this is for USB port that connects to the NOC. if
> bandwidth scaling is not needed (or other interconnect configuration), then
> maybe this can go without interconnect provider driver."
>
> However as we discover more and more about this platform (e.g. PCIe using
> the aggre_noc region to setup some magic registers, see [1]), I'm more and
> more biased towards suggesting implementing the interconnect driver to setup
> all these tiny little things. With the DT tree being an ABI, it is much
> preferable to overestimate the needs rather than underestimating them (and
> having to cope with the backwards compatibility issues).
>
> Generally I think that PCIe/USB/whatever should not poke into NoC registers
> or NoC/NIU clocks directly (because this is a very platform-specific item).
> Rather than that it should tell the icc/opp/whatever subsystem, "please
> configure the SoC for me to work".
>
> [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
Dmitry,
Can we remove the interconnect clocks in the next patch
version (and assume that the boot loader configures them)?
And add these clocks once the interconnect support is available.
Thanks
Varada
>
> >
> >Thanks
> >Varada
> >
> >
> >>
> >>
> >>>
> >>>>>+ <&gcc GCC_USB0_MASTER_CLK>,
> >>>>>+???????????????????????????????????????? <&gcc
> >>>>>GCC_USB0_MOCK_UTMI_CLK>;
> >>>>>+?????????????????????? assigned-clock-rates = <200000000>,
> >>>>>+ <200000000>,
> >>>>>+ <200000000>,
> >>>>>+ <24000000>;
> >>>>>+
> >>>>>+?????????????????????? resets = <&gcc GCC_USB_BCR>;
> >>>>>+?????????????????????? status = "disabled";
> >>>>>+
> >>>>>+?????????????????????? dwc_0: dwc3@8A00000 {
> >>>>>+?????????????????????????????? compatible = "snps,dwc3";
> >>>>>+?????????????????????????????? reg = <0x8A00000 0xcd00>;
> >>>>>+?????????????????????????????? clock-names = "ref";
> >>>>>+?????????????????????????????? clocks = <&gcc
> >>>>>GCC_USB0_MOCK_UTMI_CLK>;
> >>>>clocks before clock-names
> >>>>
> >>>>>+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> >>>>>+?????????????????????????????? phys = <&qusb_phy_0>, <&usb0_ssphy>;
> >>>>>+?????????????????????????????? phy-names = "usb2-phy", "usb3-phy";
> >>>>>+?????????????????????????????? tx-fifo-resize;
> >>>>>+?????????????????????????????? snps,dis_ep_cache_eviction;
> >>>>>+?????????????????????????????? snps,is-utmi-l1-suspend;
> >>>>>+?????????????????????????????? snps,hird-threshold = /bits/ 8 <0x0>;
> >>>>>+?????????????????????????????? snps,dis_u2_susphy_quirk;
> >>>>>+?????????????????????????????? snps,dis_u3_susphy_quirk;
> >>>>>+ snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
> >>>>>+?????????????????????????????? dr_mode = "host";
> >>>>>+?????????????????????? };
> >>>>>+?????????????? };
> >>>>>+
> >>>>>???????????????? pcie0_phy: phy@84000 {
> >>>>>???????????????????????? compatible =
> >>>>>"qcom,ipq9574-qmp-gen3x1-pcie-phy";
> >>>>>???????????????????????? reg = <0x00084000 0x1bc>; /* Serdes PLL */
> >>>>>--
> >>>>>2.7.4
> >>>
> >>>Will address these and post a new revision.
> >>>
> >>>Thanks
> >>>
> >>>Varada
> >>>
> >>
>
> --
> With best wishes
> Dmitry
>
On Thu, Mar 16, 2023 at 12:00:09PM +0530, Varadarajan Narayanan wrote:
> Dmitry,
>
> On Tue, Mar 07, 2023 at 01:49:40PM +0200, Dmitry Baryshkov wrote:
> > On 07/03/2023 08:36, Varadarajan Narayanan wrote:
> > >
> > >On 3/6/2023 5:21 PM, Dmitry Baryshkov wrote:
> > >>On 06/03/2023 13:26, Varadarajan Narayanan wrote:
> > >>>Dmitry,
> > >>>
> > >>>On 3/2/2023 9:52 PM, Dmitry Baryshkov wrote:
> > >>>>On Thu, 2 Mar 2023 at 11:57, Varadarajan Narayanan
> > >>>><[email protected]> wrote:
> > >>>>>Add USB phy and controller related nodes
> > >>>>>
> > >>>>>Signed-off-by: Varadarajan Narayanan <[email protected]>
> > >>>>>---
> > >>>>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 92
> > >>>>>+++++++++++++++++++++++++++++++++++
> > >>>>> 1 file changed, 92 insertions(+)
> > >>>>>
> > >>>>>diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > >>>>>b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > >>>>>index 2bb4053..319b5bd 100644
> > >>>>>--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > >>>>>+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > >>
> > >>[skipped]
> > >>
> > >>
> > >>>>>+ usb3: usb3@8A00000 {
> > >>>>You know the drill. This node is in the wrong place.
> > >>>>
> > >>>>>+ compatible = "qcom,dwc3";
> > >>>>>+ reg = <0x8AF8800 0x400>;
> > >>>>>+ #address-cells = <1>;
> > >>>>>+ #size-cells = <1>;
> > >>>>>+ ranges;
> > >>>>>+
> > >>>>>+ clocks = <&gcc GCC_SNOC_USB_CLK>,
> > >>>>>+ <&gcc GCC_ANOC_USB_AXI_CLK>,
> > >>>>>+ <&gcc GCC_USB0_MASTER_CLK>,
> > >>>>>+ <&gcc GCC_USB0_SLEEP_CLK>,
> > >>>>>+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > >>>>>+
> > >>>>>+ clock-names = "sys_noc_axi",
> > >>>>>+ "anoc_axi",
> > >>>>>+ "master",
> > >>>>>+ "sleep",
> > >>>>>+ "mock_utmi";
> > >>>>Please fix the indentation of the lists.
> > >>>>
> > >>>>>+
> > >>>>>+ assigned-clocks = <&gcc GCC_SNOC_USB_CLK>,
> > >>>>>+ <&gcc GCC_ANOC_USB_AXI_CLK>,
> > >>>>Why do you assign clock rates to the NOC clocks? Should they be set
> > >>>>using the interconnect instead?
> > >>>
> > >>>The SNOC and ANOC run at a fixed speed of 350MHz and 342MHz
> > >>>respectively and are not scaled. These clocks are for the interface
> > >>>between the USB block and the SNOC/ANOC. Do we still need to use
> > >>>interconnect?
> > >>
> > >>Maybe I misunderstand something here. If the snoc and anoc speeds are at
> > >>350 MHz and 342 MHz, why do you assign clock-rates of 200 MHz?
> > >>
> > >>Is it enough to call clk_prepare_enable() for these clocks or the rate
> > >>really needs to be set?
> > >
> > >The rate of 200MHz is not being set for the SNOC/ANOC. It is for the
> > >NIU that connects the USB and SNOC/ANOC. The reason for setting the
> > >rate to 200MHz is to configure the RCG parent for these interface
> > >clocks. That said can we configure this RCG standalone in the driver
> > >and enable these clocks?
> >
> > We discussed this separately with Georgi Djakov. Let me quote his IRC
> > message: "it sounds like this is for USB port that connects to the NOC. if
> > bandwidth scaling is not needed (or other interconnect configuration), then
> > maybe this can go without interconnect provider driver."
> >
> > However as we discover more and more about this platform (e.g. PCIe using
> > the aggre_noc region to setup some magic registers, see [1]), I'm more and
> > more biased towards suggesting implementing the interconnect driver to setup
> > all these tiny little things. With the DT tree being an ABI, it is much
> > preferable to overestimate the needs rather than underestimating them (and
> > having to cope with the backwards compatibility issues).
> >
> > Generally I think that PCIe/USB/whatever should not poke into NoC registers
> > or NoC/NIU clocks directly (because this is a very platform-specific item).
> > Rather than that it should tell the icc/opp/whatever subsystem, "please
> > configure the SoC for me to work".
> >
> > [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
>
> Dmitry,
> Can we remove the interconnect clocks in the next patch
> version (and assume that the boot loader configures them)?
>
> And add these clocks once the interconnect support is available.
>
Yes, that should work. If you do not care about interconnect scaling, then let
the bootloader set whatever fixed bandwidth is required for the peripherals.
Thinking from the usecase perspective of these router chipsets, you won't need
interconnect provider driver as of now.
Thanks,
Mani
> Thanks
> Varada
>
> >
> > >
> > >Thanks
> > >Varada
> > >
> > >
> > >>
> > >>
> > >>>
> > >>>>>+ <&gcc GCC_USB0_MASTER_CLK>,
> > >>>>>+ <&gcc
> > >>>>>GCC_USB0_MOCK_UTMI_CLK>;
> > >>>>>+ assigned-clock-rates = <200000000>,
> > >>>>>+ <200000000>,
> > >>>>>+ <200000000>,
> > >>>>>+ <24000000>;
> > >>>>>+
> > >>>>>+ resets = <&gcc GCC_USB_BCR>;
> > >>>>>+ status = "disabled";
> > >>>>>+
> > >>>>>+ dwc_0: dwc3@8A00000 {
> > >>>>>+ compatible = "snps,dwc3";
> > >>>>>+ reg = <0x8A00000 0xcd00>;
> > >>>>>+ clock-names = "ref";
> > >>>>>+ clocks = <&gcc
> > >>>>>GCC_USB0_MOCK_UTMI_CLK>;
> > >>>>clocks before clock-names
> > >>>>
> > >>>>>+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > >>>>>+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
> > >>>>>+ phy-names = "usb2-phy", "usb3-phy";
> > >>>>>+ tx-fifo-resize;
> > >>>>>+ snps,dis_ep_cache_eviction;
> > >>>>>+ snps,is-utmi-l1-suspend;
> > >>>>>+ snps,hird-threshold = /bits/ 8 <0x0>;
> > >>>>>+ snps,dis_u2_susphy_quirk;
> > >>>>>+ snps,dis_u3_susphy_quirk;
> > >>>>>+ snps,quirk-frame-length-adjustment = <0x0A87F0A0>;
> > >>>>>+ dr_mode = "host";
> > >>>>>+ };
> > >>>>>+ };
> > >>>>>+
> > >>>>> pcie0_phy: phy@84000 {
> > >>>>> compatible =
> > >>>>>"qcom,ipq9574-qmp-gen3x1-pcie-phy";
> > >>>>> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> > >>>>>--
> > >>>>>2.7.4
> > >>>
> > >>>Will address these and post a new revision.
> > >>>
> > >>>Thanks
> > >>>
> > >>>Varada
> > >>>
> > >>
> >
> > --
> > With best wishes
> > Dmitry
> >
--
மணிவண்ணன் சதாசிவம்
This patch series adds the relevant phy and controller
configurations for enabling USB on IPQ9754
Depends on:
https://lore.kernel.org/all/[email protected]/
[v2]:
- Incorporated review comments regarding coding styler,
maintaining sorted order of entries and unused phy register
offsets
- Removed NOC clock entries from DT node (will be implemented
later with interconnect support)
- Fixed 'make dtbs_check' errors/warnings
[v1]:
https://lore.kernel.org/linux-arm-msm/[email protected]/T/
Varadarajan Narayanan (8):
dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
dt-bindings: usb: dwc3: Add IPQ9574 compatible
clk: qcom: gcc-ipq9574: Add USB related clocks
phy: qcom-qusb2: add QUSB2 support for IPQ9574
phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
arm64: dts: qcom: ipq9574: Add USB related nodes
arm64: dts: qcom: ipq9574: Enable USB
.../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 22 ++++
.../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 +-
.../devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 +++
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++
drivers/clk/qcom/gcc-ipq9574.c | 37 +++++++
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 +++++++++++++++++++++
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
9 files changed, 284 insertions(+), 1 deletion(-)
--
2.7.4
Document the compatible string used for the qusb2 phy in IPQ9574.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Moved ipq6018 to the proper place and placed ipq9574
next to it as suggested by Dmitry
---
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index 7f403e7..eaecf9b 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -19,12 +19,13 @@ properties:
- items:
- enum:
- qcom,ipq8074-qusb2-phy
+ - qcom,ipq6018-qusb2-phy
+ - qcom,ipq9574-qusb2-phy
- qcom,msm8953-qusb2-phy
- qcom,msm8996-qusb2-phy
- qcom,msm8998-qusb2-phy
- qcom,qcm2290-qusb2-phy
- qcom,sdm660-qusb2-phy
- - qcom,ipq6018-qusb2-phy
- qcom,sm4250-qusb2-phy
- qcom,sm6115-qusb2-phy
- items:
--
2.7.4
Add the clocks needed for enabling USB in IPQ9574
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Fixed coding style issues
---
drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 1bf33d5..06b724a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -2041,6 +2041,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
@@ -4008,6 +4043,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index c89e96d..96b7c0b 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -214,4 +214,6 @@
#define GCC_SNOC_PCIE1_1LANE_S_CLK 205
#define GCC_SNOC_PCIE2_2LANE_S_CLK 206
#define GCC_SNOC_PCIE3_2LANE_S_CLK 207
+#define GCC_USB0_PIPE_CLK 208
+#define GCC_USB0_SLEEP_CLK 209
#endif
--
2.7.4
Add the phy init sequence for the Super Speed ports found
on IPQ9574.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Place the entry such that the list continues to be sorted
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 2ef638b..bec6e40 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -912,6 +912,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qusb2-phy",
+ .data = &ipq6018_phy_cfg,
+ }, {
.compatible = "qcom,msm8953-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
--
2.7.4
Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
Reused clock and reset list from existing targets.
Signed-off-by: Praveenkumar I <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 ++++++++++++++++++++++++++++++++
1 file changed, 119 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index a49711c..51894b9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -94,6 +94,7 @@ enum qphy_reg_layout {
QPHY_PCS_STATUS,
QPHY_PCS_AUTONOMOUS_MODE_CTRL,
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
+ QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
QPHY_PCS_POWER_DOWN_CONTROL,
/* Keep last to ensure regs_layout arrays are properly initialized */
QPHY_LAYOUT_SIZE
@@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
};
+static const unsigned int usb3phy_regs_layout[] = {
+ [QPHY_SW_RESET] = 0x00,
+ [QPHY_START_CTRL] = 0x08,
+ [QPHY_PCS_STATUS] = 0x17c,
+ [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
+ [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
+ [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
}
/* list of clocks required by phy */
+static const char * const ipq9574_phy_clk_l[] = {
+ "aux", "cfg_ahb",
+};
+
static const char * const msm8996_phy_clk_l[] = {
"aux", "cfg_ahb", "ref",
};
@@ -1586,6 +1682,26 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.regs = qmp_v3_usb3phy_regs_layout,
};
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+ .lanes = 1,
+
+ .serdes_tbl = ipq9574_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+ .tx_tbl = ipq9574_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+ .rx_tbl = ipq9574_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+ .pcs_tbl = ipq9574_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+ .clk_list = ipq9574_phy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
+ .reset_list = msm8996_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = usb3phy_regs_layout,
+};
+
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.lanes = 1,
@@ -2589,6 +2705,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-usb3-phy",
.data = &ipq8074_usb3phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qmp-usb3-phy",
+ .data = &ipq9574_usb3phy_cfg,
+ }, {
.compatible = "qcom,msm8996-qmp-usb3-phy",
.data = &msm8996_usb3phy_cfg,
}, {
--
2.7.4
Add USB phy and controller related nodes
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper
interconnect support)
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2bb4053..513da74 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -829,6 +829,92 @@
msi-parent = <&v2m0>;
status = "disabled";
};
+
+ qusb_phy_0: phy@7b000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x07b000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@7d000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x7d000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: phy@7d200 {
+ reg = <0x0007d200 0x130>, /* tx */
+ <0x0007d400 0x200>, /* rx */
+ <0x0007d800 0x1f8>, /* pcs */
+ <0x0007d600 0x044>; /* pcs misc */
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb0_pipe_clk";
+ };
+ };
+
+ usb3: usb3@8a00000 {
+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+ reg = <0x8af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "sys_noc_axi",
+ "anoc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
};
rpm-glink {
--
2.7.4
Turn on USB related nodes
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Changes in v2:
- Fix node placement and coding style
- "ok" -> "okay"
---
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
index 8a6caae..d0d18e5 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -57,6 +57,10 @@
status = "okay";
};
+&qusb_phy_0 {
+ status = "okay";
+};
+
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
@@ -84,6 +88,10 @@
clock-frequency = <32000>;
};
+&ssphy_0 {
+ status = "okay";
+};
+
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@@ -118,6 +126,10 @@
};
};
+&usb3 {
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <24000000>;
};
--
2.7.4
On 21 March 2023 11:54:19 GMT+03:00, Varadarajan Narayanan <[email protected]> wrote:
>Document the compatible string used for the qusb2 phy in IPQ9574.
>
>Acked-by: Krzysztof Kozlowski <[email protected]>
>Signed-off-by: Varadarajan Narayanan <[email protected]>
>
>---
> Changes in v2:
> - Moved ipq6018 to the proper place and placed ipq9574
> next to it as suggested by Dmitry
>---
> Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
>diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>index 7f403e7..eaecf9b 100644
>--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
>@@ -19,12 +19,13 @@ properties:
> - items:
> - enum:
> - qcom,ipq8074-qusb2-phy
>+ - qcom,ipq6018-qusb2-phy
>+ - qcom,ipq9574-qusb2-phy
This still isn't sorted
> - qcom,msm8953-qusb2-phy
> - qcom,msm8996-qusb2-phy
> - qcom,msm8998-qusb2-phy
> - qcom,qcm2290-qusb2-phy
> - qcom,sdm660-qusb2-phy
>- - qcom,ipq6018-qusb2-phy
> - qcom,sm4250-qusb2-phy
> - qcom,sm6115-qusb2-phy
> - items:
--
With best wishes
Dmitry
On 21 March 2023 11:54:25 GMT+03:00, Varadarajan Narayanan <[email protected]> wrote:
>Add USB phy and controller related nodes
>
>Signed-off-by: Varadarajan Narayanan <[email protected]>
>
>---
> Changes in v2:
> - Fixed issues flagged by Krzysztof
> - Fix issues reported by make dtbs_check
> - Remove NOC related clocks (to be added with proper
> interconnect support)
>---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>index 2bb4053..513da74 100644
>--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>@@ -829,6 +829,92 @@
> msi-parent = <&v2m0>;
> status = "disabled";
> };
The last device node is pci@28000000. Thus you are trying to add all usb nodes at the wrong place. Please move them so that all nodes are still sorted by the address part.
>+
>+ qusb_phy_0: phy@7b000 {
>+ compatible = "qcom,ipq9574-qusb2-phy";
>+ reg = <0x07b000 0x180>;
>+ #phy-cells = <0>;
>+
>+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
>+ <&xo_board_clk>;
>+ clock-names = "cfg_ahb", "ref";
>+
>+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
>+ status = "disabled";
>+ };
>+
>+ ssphy_0: phy@7d000 {
>+ compatible = "qcom,ipq9574-qmp-usb3-phy";
>+ reg = <0x7d000 0x1c4>;
>+ #clock-cells = <1>;
>+ #address-cells = <1>;
>+ #size-cells = <1>;
>+ ranges;
>+
>+ clocks = <&gcc GCC_USB0_AUX_CLK>,
>+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
>+ clock-names = "aux", "cfg_ahb";
>+
>+ resets = <&gcc GCC_USB0_PHY_BCR>,
>+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
>+ reset-names = "phy","common";
>+ status = "disabled";
>+
>+ usb0_ssphy: phy@7d200 {
>+ reg = <0x0007d200 0x130>, /* tx */
>+ <0x0007d400 0x200>, /* rx */
>+ <0x0007d800 0x1f8>, /* pcs */
>+ <0x0007d600 0x044>; /* pcs misc */
>+ #phy-cells = <0>;
>+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
>+ clock-names = "pipe0";
>+ clock-output-names = "usb0_pipe_clk";
>+ };
>+ };
>+
>+ usb3: usb3@8a00000 {
>+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
>+ reg = <0x8af8800 0x400>;
>+ #address-cells = <1>;
>+ #size-cells = <1>;
>+ ranges;
>+
>+ clocks = <&gcc GCC_SNOC_USB_CLK>,
>+ <&gcc GCC_ANOC_USB_AXI_CLK>,
>+ <&gcc GCC_USB0_MASTER_CLK>,
>+ <&gcc GCC_USB0_SLEEP_CLK>,
>+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>+
>+ clock-names = "sys_noc_axi",
>+ "anoc_axi",
>+ "master",
>+ "sleep",
>+ "mock_utmi";
>+
>+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
>+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>+ assigned-clock-rates = <200000000>,
>+ <24000000>;
>+
>+ resets = <&gcc GCC_USB_BCR>;
>+ status = "disabled";
>+
>+ dwc_0: usb@8a00000 {
>+ compatible = "snps,dwc3";
>+ reg = <0x8a00000 0xcd00>;
>+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
>+ clock-names = "ref";
>+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
>+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
>+ phy-names = "usb2-phy", "usb3-phy";
>+ tx-fifo-resize;
>+ snps,is-utmi-l1-suspend;
>+ snps,hird-threshold = /bits/ 8 <0x0>;
>+ snps,dis_u2_susphy_quirk;
>+ snps,dis_u3_susphy_quirk;
>+ dr_mode = "host";
>+ };
>+ };
> };
>
> rpm-glink {
--
With best wishes
Dmitry
On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> This patch series adds the relevant phy and controller
> configurations for enabling USB on IPQ9754
I got this as a reply to the v1 thread. Please don't do that
and send it as a new mail thread the next time around.
Konrad
>
> Depends on:
> https://lore.kernel.org/all/[email protected]/
>
> [v2]:
> - Incorporated review comments regarding coding styler,
> maintaining sorted order of entries and unused phy register
> offsets
> - Removed NOC clock entries from DT node (will be implemented
> later with interconnect support)
> - Fixed 'make dtbs_check' errors/warnings
>
> [v1]:
> https://lore.kernel.org/linux-arm-msm/[email protected]/T/
>
> Varadarajan Narayanan (8):
> dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
> dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
> dt-bindings: usb: dwc3: Add IPQ9574 compatible
> clk: qcom: gcc-ipq9574: Add USB related clocks
> phy: qcom-qusb2: add QUSB2 support for IPQ9574
> phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
> arm64: dts: qcom: ipq9574: Add USB related nodes
> arm64: dts: qcom: ipq9574: Enable USB
>
> .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 22 ++++
> .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 +-
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
> arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 +++
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++
> drivers/clk/qcom/gcc-ipq9574.c | 37 +++++++
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 +++++++++++++++++++++
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +
> include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
> 9 files changed, 284 insertions(+), 1 deletion(-)
>
On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> Reused clock and reset list from existing targets.
>
> Signed-off-by: Praveenkumar I <[email protected]>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
>
> ---
> Changes in v2:
> - Removed unused phy register offsets
> - Moved the clock entries to the correct place
> - Maintain sorted order
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 ++++++++++++++++++++++++++++++++
> 1 file changed, 119 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> index a49711c..51894b9 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> @@ -94,6 +94,7 @@ enum qphy_reg_layout {
> QPHY_PCS_STATUS,
> QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> QPHY_PCS_POWER_DOWN_CONTROL,
> /* Keep last to ensure regs_layout arrays are properly initialized */
> QPHY_LAYOUT_SIZE
> @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> };
>
> +static const unsigned int usb3phy_regs_layout[] = {
> + [QPHY_SW_RESET] = 0x00,
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_STATUS] = 0x17c,
> + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
Please be consistent with hex captitalization.
Konrad
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> @@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> }
>
> /* list of clocks required by phy */
> +static const char * const ipq9574_phy_clk_l[] = {
> + "aux", "cfg_ahb",
> +};
> +
> static const char * const msm8996_phy_clk_l[] = {
> "aux", "cfg_ahb", "ref",
> };
> @@ -1586,6 +1682,26 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> .regs = qmp_v3_usb3phy_regs_layout,
> };
>
> +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> + .lanes = 1,
> +
> + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> + .tx_tbl = ipq9574_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> + .rx_tbl = ipq9574_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> + .clk_list = ipq9574_phy_clk_l,
> + .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
> + .reset_list = msm8996_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = usb3phy_regs_layout,
> +};
> +
> static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> .lanes = 1,
>
> @@ -2589,6 +2705,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> .compatible = "qcom,ipq8074-qmp-usb3-phy",
> .data = &ipq8074_usb3phy_cfg,
> }, {
> + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> + .data = &ipq9574_usb3phy_cfg,
> + }, {
> .compatible = "qcom,msm8996-qmp-usb3-phy",
> .data = &msm8996_usb3phy_cfg,
> }, {
Quoting Varadarajan Narayanan (2023-03-21 01:54:22)
> Add the clocks needed for enabling USB in IPQ9574
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
>
> ---
Acked-by: Stephen Boyd <[email protected]>
On Tue, Mar 21, 2023 at 02:17:13PM +0300, Dmitry Baryshkov wrote:
>
>
> On 21 March 2023 11:54:19 GMT+03:00, Varadarajan Narayanan <[email protected]> wrote:
> >Document the compatible string used for the qusb2 phy in IPQ9574.
> >
> >Acked-by: Krzysztof Kozlowski <[email protected]>
> >Signed-off-by: Varadarajan Narayanan <[email protected]>
> >
> >---
> > Changes in v2:
> > - Moved ipq6018 to the proper place and placed ipq9574
> > next to it as suggested by Dmitry
> >---
> > Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> >diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> >index 7f403e7..eaecf9b 100644
> >--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> >+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
> >@@ -19,12 +19,13 @@ properties:
> > - items:
> > - enum:
> > - qcom,ipq8074-qusb2-phy
> >+ - qcom,ipq6018-qusb2-phy
> >+ - qcom,ipq9574-qusb2-phy
>
> This still isn't sorted
Sorry. Will fix this.
Thanks
Varada
>
> > - qcom,msm8953-qusb2-phy
> > - qcom,msm8996-qusb2-phy
> > - qcom,msm8998-qusb2-phy
> > - qcom,qcm2290-qusb2-phy
> > - qcom,sdm660-qusb2-phy
> >- - qcom,ipq6018-qusb2-phy
> > - qcom,sm4250-qusb2-phy
> > - qcom,sm6115-qusb2-phy
> > - items:
>
> --
> With best wishes
> Dmitry
On Tue, Mar 21, 2023 at 02:23:26PM +0300, Dmitry Baryshkov wrote:
>
>
> On 21 March 2023 11:54:25 GMT+03:00, Varadarajan Narayanan <[email protected]> wrote:
> >Add USB phy and controller related nodes
> >
> >Signed-off-by: Varadarajan Narayanan <[email protected]>
> >
> >---
> > Changes in v2:
> > - Fixed issues flagged by Krzysztof
> > - Fix issues reported by make dtbs_check
> > - Remove NOC related clocks (to be added with proper
> > interconnect support)
> >---
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 86 insertions(+)
> >
> >diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >index 2bb4053..513da74 100644
> >--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> >@@ -829,6 +829,92 @@
> > msi-parent = <&v2m0>;
> > status = "disabled";
> > };
>
> The last device node is pci@28000000. Thus you are trying to
> add all usb nodes at the wrong place. Please move them so that
> all nodes are still sorted by the address part.
Ok. Will reorder them.
Thanks
Varada
>
>
> >+
> >+ qusb_phy_0: phy@7b000 {
> >+ compatible = "qcom,ipq9574-qusb2-phy";
> >+ reg = <0x07b000 0x180>;
> >+ #phy-cells = <0>;
> >+
> >+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> >+ <&xo_board_clk>;
> >+ clock-names = "cfg_ahb", "ref";
> >+
> >+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> >+ status = "disabled";
> >+ };
> >+
> >+ ssphy_0: phy@7d000 {
> >+ compatible = "qcom,ipq9574-qmp-usb3-phy";
> >+ reg = <0x7d000 0x1c4>;
> >+ #clock-cells = <1>;
> >+ #address-cells = <1>;
> >+ #size-cells = <1>;
> >+ ranges;
> >+
> >+ clocks = <&gcc GCC_USB0_AUX_CLK>,
> >+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>;
> >+ clock-names = "aux", "cfg_ahb";
> >+
> >+ resets = <&gcc GCC_USB0_PHY_BCR>,
> >+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
> >+ reset-names = "phy","common";
> >+ status = "disabled";
> >+
> >+ usb0_ssphy: phy@7d200 {
> >+ reg = <0x0007d200 0x130>, /* tx */
> >+ <0x0007d400 0x200>, /* rx */
> >+ <0x0007d800 0x1f8>, /* pcs */
> >+ <0x0007d600 0x044>; /* pcs misc */
> >+ #phy-cells = <0>;
> >+ clocks = <&gcc GCC_USB0_PIPE_CLK>;
> >+ clock-names = "pipe0";
> >+ clock-output-names = "usb0_pipe_clk";
> >+ };
> >+ };
> >+
> >+ usb3: usb3@8a00000 {
> >+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> >+ reg = <0x8af8800 0x400>;
> >+ #address-cells = <1>;
> >+ #size-cells = <1>;
> >+ ranges;
> >+
> >+ clocks = <&gcc GCC_SNOC_USB_CLK>,
> >+ <&gcc GCC_ANOC_USB_AXI_CLK>,
> >+ <&gcc GCC_USB0_MASTER_CLK>,
> >+ <&gcc GCC_USB0_SLEEP_CLK>,
> >+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >+
> >+ clock-names = "sys_noc_axi",
> >+ "anoc_axi",
> >+ "master",
> >+ "sleep",
> >+ "mock_utmi";
> >+
> >+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> >+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >+ assigned-clock-rates = <200000000>,
> >+ <24000000>;
> >+
> >+ resets = <&gcc GCC_USB_BCR>;
> >+ status = "disabled";
> >+
> >+ dwc_0: usb@8a00000 {
> >+ compatible = "snps,dwc3";
> >+ reg = <0x8a00000 0xcd00>;
> >+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> >+ clock-names = "ref";
> >+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> >+ phys = <&qusb_phy_0>, <&usb0_ssphy>;
> >+ phy-names = "usb2-phy", "usb3-phy";
> >+ tx-fifo-resize;
> >+ snps,is-utmi-l1-suspend;
> >+ snps,hird-threshold = /bits/ 8 <0x0>;
> >+ snps,dis_u2_susphy_quirk;
> >+ snps,dis_u3_susphy_quirk;
> >+ dr_mode = "host";
> >+ };
> >+ };
> > };
> >
> > rpm-glink {
>
> --
> With best wishes
> Dmitry
On Tue, Mar 21, 2023 at 01:07:02PM +0100, Konrad Dybcio wrote:
>
>
> On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> > Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> > Reused clock and reset list from existing targets.
> >
> > Signed-off-by: Praveenkumar I <[email protected]>
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> >
> > ---
> > Changes in v2:
> > - Removed unused phy register offsets
> > - Moved the clock entries to the correct place
> > - Maintain sorted order
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 ++++++++++++++++++++++++++++++++
> > 1 file changed, 119 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > index a49711c..51894b9 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > @@ -94,6 +94,7 @@ enum qphy_reg_layout {
> > QPHY_PCS_STATUS,
> > QPHY_PCS_AUTONOMOUS_MODE_CTRL,
> > QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
> > + QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
> > QPHY_PCS_POWER_DOWN_CONTROL,
> > /* Keep last to ensure regs_layout arrays are properly initialized */
> > QPHY_LAYOUT_SIZE
> > @@ -139,6 +140,97 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> > [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> > };
> >
> > +static const unsigned int usb3phy_regs_layout[] = {
> > + [QPHY_SW_RESET] = 0x00,
> > + [QPHY_START_CTRL] = 0x08,
> > + [QPHY_PCS_STATUS] = 0x17c,
> > + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
> > + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8,
> > + [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> > + /* PLL and Loop filter settings */
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xAB),
> Please be consistent with hex captitalization.
>
> Konrad
Will fix this.
Thanks
Varada
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xAA),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xA0),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xAA),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> > + /* SSC settings */
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7D),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0A),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> > + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> > + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> > +};
> > +
> > static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > @@ -1510,6 +1602,10 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
> > }
> >
> > /* list of clocks required by phy */
> > +static const char * const ipq9574_phy_clk_l[] = {
> > + "aux", "cfg_ahb",
> > +};
> > +
> > static const char * const msm8996_phy_clk_l[] = {
> > "aux", "cfg_ahb", "ref",
> > };
> > @@ -1586,6 +1682,26 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> > .regs = qmp_v3_usb3phy_regs_layout,
> > };
> >
> > +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> > + .lanes = 1,
> > +
> > + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> > + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> > + .tx_tbl = ipq9574_usb3_tx_tbl,
> > + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> > + .rx_tbl = ipq9574_usb3_rx_tbl,
> > + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> > + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> > + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> > + .clk_list = ipq9574_phy_clk_l,
> > + .num_clks = ARRAY_SIZE(ipq9574_phy_clk_l),
> > + .reset_list = msm8996_usb3phy_reset_l,
> > + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
> > + .vreg_list = qmp_phy_vreg_l,
> > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > + .regs = usb3phy_regs_layout,
> > +};
> > +
> > static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> > .lanes = 1,
> >
> > @@ -2589,6 +2705,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> > .compatible = "qcom,ipq8074-qmp-usb3-phy",
> > .data = &ipq8074_usb3phy_cfg,
> > }, {
> > + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> > + .data = &ipq9574_usb3phy_cfg,
> > + }, {
> > .compatible = "qcom,msm8996-qmp-usb3-phy",
> > .data = &msm8996_usb3phy_cfg,
> > }, {
On Tue, Mar 21, 2023 at 12:53:41PM +0100, Konrad Dybcio wrote:
>
>
> On 21.03.2023 09:54, Varadarajan Narayanan wrote:
> > This patch series adds the relevant phy and controller
> > configurations for enabling USB on IPQ9754
> I got this as a reply to the v1 thread. Please don't do that
> and send it as a new mail thread the next time around.
>
> Konrad
Sorry. Will take care next time.
Thanks
Varada
> >
> > Depends on:
> > https://lore.kernel.org/all/[email protected]/
> >
> > [v2]:
> > - Incorporated review comments regarding coding styler,
> > maintaining sorted order of entries and unused phy register
> > offsets
> > - Removed NOC clock entries from DT node (will be implemented
> > later with interconnect support)
> > - Fixed 'make dtbs_check' errors/warnings
> >
> > [v1]:
> > https://lore.kernel.org/linux-arm-msm/[email protected]/T/
> >
> > Varadarajan Narayanan (8):
> > dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
> > dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
> > dt-bindings: usb: dwc3: Add IPQ9574 compatible
> > clk: qcom: gcc-ipq9574: Add USB related clocks
> > phy: qcom-qusb2: add QUSB2 support for IPQ9574
> > phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
> > arm64: dts: qcom: ipq9574: Add USB related nodes
> > arm64: dts: qcom: ipq9574: Enable USB
> >
> > .../bindings/phy/qcom,msm8996-qmp-usb3-phy.yaml | 22 ++++
> > .../devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 +-
> > .../devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
> > arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 12 +++
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 86 +++++++++++++++
> > drivers/clk/qcom/gcc-ipq9574.c | 37 +++++++
> > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 119 +++++++++++++++++++++
> > drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +
> > include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 +
> > 9 files changed, 284 insertions(+), 1 deletion(-)
> >
On Tue, Mar 21, 2023 at 02:24:22PM +0530, Varadarajan Narayanan wrote:
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
[..]
> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> index c89e96d..96b7c0b 100644
> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
> @@ -214,4 +214,6 @@
> #define GCC_SNOC_PCIE1_1LANE_S_CLK 205
> #define GCC_SNOC_PCIE2_2LANE_S_CLK 206
> #define GCC_SNOC_PCIE3_2LANE_S_CLK 207
> +#define GCC_USB0_PIPE_CLK 208
> +#define GCC_USB0_SLEEP_CLK 209
Please split out the dt binding/include change in a separate patch, to
better facilitate picking both the clock and dts patch for the same
kernel version.
Thanks,
Bjorn
On 06/04/2023 20:45, Bjorn Andersson wrote:
> On Tue, Mar 21, 2023 at 02:24:22PM +0530, Varadarajan Narayanan wrote:
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> [..]
>> diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> index c89e96d..96b7c0b 100644
>> --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
>> @@ -214,4 +214,6 @@
>> #define GCC_SNOC_PCIE1_1LANE_S_CLK 205
>> #define GCC_SNOC_PCIE2_2LANE_S_CLK 206
>> #define GCC_SNOC_PCIE3_2LANE_S_CLK 207
>> +#define GCC_USB0_PIPE_CLK 208
>> +#define GCC_USB0_SLEEP_CLK 209
>
> Please split out the dt binding/include change in a separate patch, to
> better facilitate picking both the clock and dts patch for the same
> kernel version.
Uh, bindings must be split to their own patch as they are exported from
kernel repo.
Best regards,
Krzysztof