This patch set is based on Jisheng Zhang's <[email protected]>
patch set to support implementing .remove() hook in host controller
drivers of Designware based implementations.
Jisheng's patches: https://patchwork.kernel.org/project/linux-pci/list/?series=98559
This patch set moves config space APIs which are inlined in headers to
source files and exports them along with the other required APIs to
support building host controller drivers as modules.
Vidya Sagar (2):
PCI: dwc: Add API support to de-initialize host
PCI: dwc: Export APIs to support .remove() implementation
drivers/pci/controller/dwc/pcie-designware-host.c | 11 +++++++
drivers/pci/controller/dwc/pcie-designware.c | 38 +++++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.h | 40 +++++++----------------
3 files changed, 60 insertions(+), 29 deletions(-)
--
2.7.4
Add an API to group all the tasks to be done to de-initialize host which
can then be called by any Designware core based driver implementations
while adding .remove() support in their respective drivers.
Signed-off-by: Vidya Sagar <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 7 +++++++
drivers/pci/controller/dwc/pcie-designware.h | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 3e4169e738a5..d7881490282d 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -516,6 +516,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
return ret;
}
+void dw_pcie_host_deinit(struct pcie_port *pp)
+{
+ pci_stop_root_bus(pp->root_bus);
+ pci_remove_root_bus(pp->root_bus);
+ dw_pcie_free_msi(pp);
+}
+
static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val,
bool write)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index adff0c713665..ea8d1caf11c5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -343,6 +343,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
void dw_pcie_free_msi(struct pcie_port *pp);
void dw_pcie_setup_rc(struct pcie_port *pp);
int dw_pcie_host_init(struct pcie_port *pp);
+void dw_pcie_host_deinit(struct pcie_port *pp);
int dw_pcie_allocate_domains(struct pcie_port *pp);
#else
static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
@@ -367,6 +368,10 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
return 0;
}
+static inline void dw_pcie_host_deinit(struct pcie_port *pp)
+{
+}
+
static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
{
return 0;
--
2.7.4
Export all configuration space access APIs and also other APIs to
support host controller drivers of Designware core based
implementations while adding support for .remove() hook to build their
respective drivers as modules
Signed-off-by: Vidya Sagar <[email protected]>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 4 +++
drivers/pci/controller/dwc/pcie-designware.c | 38 +++++++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.h | 35 ++++-----------------
3 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d7881490282d..2a5332e5ccfa 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -333,6 +333,7 @@ void dw_pcie_msi_init(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
upper_32_bits(msi_target));
}
+EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
int dw_pcie_host_init(struct pcie_port *pp)
{
@@ -515,6 +516,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
dw_pcie_free_msi(pp);
return ret;
}
+EXPORT_SYMBOL_GPL(dw_pcie_host_init);
void dw_pcie_host_deinit(struct pcie_port *pp)
{
@@ -522,6 +524,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp)
pci_remove_root_bus(pp->root_bus);
dw_pcie_free_msi(pp);
}
+EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 devfn, int where, int size, u32 *val,
@@ -731,3 +734,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
val |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
}
+EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 31f6331ca46f..f98e2f284ae1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -40,6 +40,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val)
return PCIBIOS_SUCCESSFUL;
}
+EXPORT_SYMBOL_GPL(dw_pcie_read);
int dw_pcie_write(void __iomem *addr, int size, u32 val)
{
@@ -57,6 +58,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
return PCIBIOS_SUCCESSFUL;
}
+EXPORT_SYMBOL_GPL(dw_pcie_write);
u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
size_t size)
@@ -89,6 +91,42 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
dev_err(pci->dev, "Write DBI address failed\n");
}
+void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
+{
+ __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_writel_dbi);
+
+u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
+{
+ return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_readl_dbi);
+
+void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
+{
+ __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_writew_dbi);
+
+u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
+{
+ return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_readw_dbi);
+
+void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
+{
+ __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_writeb_dbi);
+
+u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
+{
+ return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_readb_dbi);
+
static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
{
u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ea8d1caf11c5..86df36701a37 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -265,35 +265,12 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
enum dw_pcie_region_type type);
void dw_pcie_setup(struct dw_pcie *pci);
-static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
-{
- __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
-}
-
-static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
-{
- return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
-}
-
-static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
-{
- __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
-}
-
-static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
-{
- return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
-}
-
-static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
-{
- __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
-}
-
-static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
-{
- return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
-}
+void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
+u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
+void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val);
+u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg);
+void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val);
+u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg);
static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
{
--
2.7.4
Anyone for the review of this patch series (total 2 patches)?
On Thu, Apr 4, 2019 at 5:50 PM Vidya Sagar <[email protected]> wrote:
>
> Add an API to group all the tasks to be done to de-initialize host which
> can then be called by any Designware core based driver implementations
> while adding .remove() support in their respective drivers.
>
> Signed-off-by: Vidya Sagar <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 7 +++++++
> drivers/pci/controller/dwc/pcie-designware.h | 5 +++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 3e4169e738a5..d7881490282d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -516,6 +516,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
> return ret;
> }
>
> +void dw_pcie_host_deinit(struct pcie_port *pp)
> +{
> + pci_stop_root_bus(pp->root_bus);
> + pci_remove_root_bus(pp->root_bus);
> + dw_pcie_free_msi(pp);
> +}
> +
> static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> u32 devfn, int where, int size, u32 *val,
> bool write)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index adff0c713665..ea8d1caf11c5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -343,6 +343,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
> void dw_pcie_free_msi(struct pcie_port *pp);
> void dw_pcie_setup_rc(struct pcie_port *pp);
> int dw_pcie_host_init(struct pcie_port *pp);
> +void dw_pcie_host_deinit(struct pcie_port *pp);
> int dw_pcie_allocate_domains(struct pcie_port *pp);
> #else
> static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> @@ -367,6 +368,10 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
> return 0;
> }
>
> +static inline void dw_pcie_host_deinit(struct pcie_port *pp)
> +{
> +}
> +
> static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
> {
> return 0;
> --
> 2.7.4
>
On Thu, Apr 4, 2019 at 13:20:23, Vidya Sagar <[email protected]> wrote:
> Add an API to group all the tasks to be done to de-initialize host which
> can then be called by any Designware core based driver implementations
s/Designware/DesignWare
> while adding .remove() support in their respective drivers.
>
> Signed-off-by: Vidya Sagar <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 7 +++++++
> drivers/pci/controller/dwc/pcie-designware.h | 5 +++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 3e4169e738a5..d7881490282d 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -516,6 +516,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
> return ret;
> }
>
> +void dw_pcie_host_deinit(struct pcie_port *pp)
> +{
> + pci_stop_root_bus(pp->root_bus);
> + pci_remove_root_bus(pp->root_bus);
> + dw_pcie_free_msi(pp);
> +}
> +
> static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> u32 devfn, int where, int size, u32 *val,
> bool write)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index adff0c713665..ea8d1caf11c5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -343,6 +343,7 @@ void dw_pcie_msi_init(struct pcie_port *pp);
> void dw_pcie_free_msi(struct pcie_port *pp);
> void dw_pcie_setup_rc(struct pcie_port *pp);
> int dw_pcie_host_init(struct pcie_port *pp);
> +void dw_pcie_host_deinit(struct pcie_port *pp);
> int dw_pcie_allocate_domains(struct pcie_port *pp);
> #else
> static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> @@ -367,6 +368,10 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
> return 0;
> }
>
> +static inline void dw_pcie_host_deinit(struct pcie_port *pp)
> +{
> +}
> +
> static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
> {
> return 0;
> --
> 2.7.4
On Thu, Apr 4, 2019 at 13:20:24, Vidya Sagar <[email protected]> wrote:
> Export all configuration space access APIs and also other APIs to
> support host controller drivers of Designware core based
s/Designware/DesignWare
> implementations while adding support for .remove() hook to build their
> respective drivers as modules
>
> Signed-off-by: Vidya Sagar <[email protected]>
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 4 +++
> drivers/pci/controller/dwc/pcie-designware.c | 38 +++++++++++++++++++++++
> drivers/pci/controller/dwc/pcie-designware.h | 35 ++++-----------------
> 3 files changed, 48 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index d7881490282d..2a5332e5ccfa 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -333,6 +333,7 @@ void dw_pcie_msi_init(struct pcie_port *pp)
> dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
> upper_32_bits(msi_target));
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
>
> int dw_pcie_host_init(struct pcie_port *pp)
> {
> @@ -515,6 +516,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
> dw_pcie_free_msi(pp);
> return ret;
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_host_init);
>
> void dw_pcie_host_deinit(struct pcie_port *pp)
> {
> @@ -522,6 +524,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp)
> pci_remove_root_bus(pp->root_bus);
> dw_pcie_free_msi(pp);
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
>
> static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> u32 devfn, int where, int size, u32 *val,
> @@ -731,3 +734,4 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
> val |= PORT_LOGIC_SPEED_CHANGE;
> dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 31f6331ca46f..f98e2f284ae1 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -40,6 +40,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val)
>
> return PCIBIOS_SUCCESSFUL;
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_read);
>
> int dw_pcie_write(void __iomem *addr, int size, u32 val)
> {
> @@ -57,6 +58,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val)
>
> return PCIBIOS_SUCCESSFUL;
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_write);
>
> u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> size_t size)
> @@ -89,6 +91,42 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg,
> dev_err(pci->dev, "Write DBI address failed\n");
> }
>
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> +{
> + __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_writel_dbi);
> +
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
> +{
> + return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_readl_dbi);
> +
> +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
> +{
> + __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_writew_dbi);
> +
> +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
> +{
> + return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_readw_dbi);
> +
> +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
> +{
> + __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_writeb_dbi);
> +
> +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
> +{
> + return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
> +}
> +EXPORT_SYMBOL_GPL(dw_pcie_readb_dbi);
> +
> static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
> {
> u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index ea8d1caf11c5..86df36701a37 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -265,35 +265,12 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
> enum dw_pcie_region_type type);
> void dw_pcie_setup(struct dw_pcie *pci);
>
> -static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
> -{
> - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, val);
> -}
> -
> -static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
> -{
> - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x4);
> -}
> -
> -static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
> -{
> - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x2, val);
> -}
> -
> -static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
> -{
> - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x2);
> -}
> -
> -static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
> -{
> - __dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x1, val);
> -}
> -
> -static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
> -{
> - return __dw_pcie_read_dbi(pci, pci->dbi_base, reg, 0x1);
> -}
> +void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val);
> +u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg);
> +void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val);
> +u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg);
> +void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val);
> +u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg);
>
> static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
> {
> --
> 2.7.4
Seems harmless. After word replacement, ack for the whole patch:
Acked-by: Gustavo Pimentel
<[email protected]>
Thanks
Gustavo
Pimentel