Andi,
I tried 2.6.12-rc3 with dual way dual cpus.
It seems right mapping should be
CPU 0(2) -> Node 0 -> Core 0
CPU 1(2) -> Node 0 -> Core 1
CPU 2(2) -> Node 1 -> Core 0
CPU 3(2) -> Node 1 -> Core 1
instead of
CPU 0(2) -> Node 0 -> Core 0
CPU 1(2) -> Node 0 -> Core 0
CPU 2(2) -> Node 1 -> Core 1
CPU 3(2) -> Node 1 -> Core 1
YH
CPU 0(2) -> Node 0 -> Core 0
Using local APIC NMI watchdog using perfctr0
enabled ExtINT on CPU#0
ENABLING IO-APIC IRQs
Using IO-APIC 4
...changing IO-APIC physical APIC ID to 4 ... ok.
Using IO-APIC 5
...changing IO-APIC physical APIC ID to 5 ... ok.
Using IO-APIC 6
...changing IO-APIC physical APIC ID to 6 ... ok.
Using IO-APIC 7
...changing IO-APIC physical APIC ID to 7 ... ok.
Synchronizing Arb IDs.
..TIMER: vector=0x31 pin1=0 pin2=2
testing the IO APIC.......................
.................................... done.
Using local APIC timer interrupts.
Detected 12.564 MHz APIC timer.
Booting processor 1/1 rip 6000 rsp ffff81007ff99f58
Initializing CPU#1
masked ExtINT on CPU#1
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 1(2) -> Node 0 -> Core 0
stepping 00
Synced TSC of CPU 1 difference 30064769976
Booting processor 2/2 rip 6000 rsp ffff81013ffa3f58
Initializing CPU#2
masked ExtINT on CPU#2
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 2(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 2 difference 30064770021
Booting processor 3/3 rip 6000 rsp ffff81007ff49f58
Initializing CPU#3
masked ExtINT on CPU#3
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 3(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 3 difference 30064770021
Brought up 4 CPUs
Andi,
accoring to the code in arch/x86_64/setup.c
/* When an ACPI SRAT table is available use the mappings from SRAT
instead. */
if (acpi_numa <= 0) {
node = cpu_core_id[cpu];
if (!node_online(node))
node = first_node(node_online_map);
cpu_to_node[cpu] = node;
} else {
node = cpu_to_node[cpu];
}
cpu_to_node[cpu] == cpu_core_id[cpu]
So you mean core id is node id?
YH
> -----Original Message-----
> From: YhLu
> Sent: Thursday, April 21, 2005 7:19 PM
> To: 'Andi Kleen'
> Cc: [email protected]
> Subject: x86-64 dual core mapping
>
> Andi,
>
> I tried 2.6.12-rc3 with dual way dual cpus.
>
> It seems right mapping should be
> CPU 0(2) -> Node 0 -> Core 0
> CPU 1(2) -> Node 0 -> Core 1
> CPU 2(2) -> Node 1 -> Core 0
> CPU 3(2) -> Node 1 -> Core 1
>
> instead of
>
> CPU 0(2) -> Node 0 -> Core 0
> CPU 1(2) -> Node 0 -> Core 0
> CPU 2(2) -> Node 1 -> Core 1
> CPU 3(2) -> Node 1 -> Core 1
>
> YH
>
>
>
>
> CPU 0(2) -> Node 0 -> Core 0
> Using local APIC NMI watchdog using perfctr0 enabled ExtINT
> on CPU#0 ENABLING IO-APIC IRQs Using IO-APIC 4 ...changing
> IO-APIC physical APIC ID to 4 ... ok.
> Using IO-APIC 5
> ...changing IO-APIC physical APIC ID to 5 ... ok.
> Using IO-APIC 6
> ...changing IO-APIC physical APIC ID to 6 ... ok.
> Using IO-APIC 7
> ...changing IO-APIC physical APIC ID to 7 ... ok.
> Synchronizing Arb IDs.
> ..TIMER: vector=0x31 pin1=0 pin2=2
> testing the IO APIC.......................
>
>
>
>
> .................................... done.
> Using local APIC timer interrupts.
> Detected 12.564 MHz APIC timer.
> Booting processor 1/1 rip 6000 rsp ffff81007ff99f58
> Initializing CPU#1 masked ExtINT on CPU#1
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 1(2) -> Node 0 -> Core 0
> stepping 00
> Synced TSC of CPU 1 difference 30064769976 Booting processor
> 2/2 rip 6000 rsp ffff81013ffa3f58 Initializing CPU#2 masked
> ExtINT on CPU#2
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 2(2) -> Node 1 -> Core 1
> stepping 00
> Synced TSC of CPU 2 difference 30064770021 Booting processor
> 3/3 rip 6000 rsp ffff81007ff49f58 Initializing CPU#3 masked
> ExtINT on CPU#3
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 3(2) -> Node 1 -> Core 1
> stepping 00
> Synced TSC of CPU 3 difference 30064770021 Brought up 4 CPUs
Please refer to my patch about that.
YH
before patch
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 0(2) -> Node 0 -> Core 0
Booting processor 1/1 rip 6000 rsp ffff81007ff99f58
Initializing CPU#1
masked ExtINT on CPU#1
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 1(2) -> Node 0 -> Core 0
stepping 00
Synced TSC of CPU 1 difference 21474835384
Booting processor 2/2 rip 6000 rsp ffff81013ffa3f58
Initializing CPU#2
masked ExtINT on CPU#2
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 2(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 2 difference 21474835425
Booting processor 3/3 rip 6000 rsp ffff81007ff49f58
Initializing CPU#3
masked ExtINT on CPU#3
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 3(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 3 difference 21474835425
Brought up 4 CPUs
~ # cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 3956.73
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 2
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 3
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
~ #
after patch
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 0(2) -> Node 0 -> Core 0
Booting processor 1/1 rip 6000 rsp ffff81007ff99f58
Initializing CPU#1
masked ExtINT on CPU#1
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 1(2) -> Node 0 -> Core 1
stepping 00
Synced TSC of CPU 1 difference 21474835384
Booting processor 2/2 rip 6000 rsp ffff81013ffa3f58
Initializing CPU#2
masked ExtINT on CPU#2
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 2(2) -> Node 1 -> Core 0
stepping 00
Synced TSC of CPU 2 difference 21474835425
Booting processor 3/3 rip 6000 rsp ffff81007ff49f58
Initializing CPU#3
masked ExtINT on CPU#3
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 3(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 3 difference 21474835425
Brought up 4 CPUs
~ # cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 3956.73
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 2
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 1
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 3
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 1
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
~ #
amd_dual_core_id.diff
--- setup.o.c 2005-04-28 12:41:12.823456408 -0700
+++ setup.c 2005-04-28 13:11:04.187127736 -0700
@@ -731,19 +731,20 @@
int node = 0;
if (c->x86_num_cores == 1)
return;
- cpu_core_id[cpu] = cpu >> hweight32(c->x86_num_cores - 1);
+ cpu_core_id[cpu] = cpu%c->x86_num_cores;
#ifdef CONFIG_NUMA
/* When an ACPI SRAT table is available use the mappings from SRAT
instead. */
if (acpi_numa <= 0) {
- node = cpu_core_id[cpu];
+ node = cpu >> hweight32(c->x86_num_cores - 1);
if (!node_online(node))
node = first_node(node_online_map);
cpu_to_node[cpu] = node;
} else {
node = cpu_to_node[cpu];
}
+ phys_proc_id[cpu] = node;
#endif
printk(KERN_INFO "CPU %d(%d) -> Node %d -> Core %d\n",
cpu, c->x86_num_cores, node, cpu_core_id[cpu]);
--- smpboot.o.c 2005-04-28 13:00:03.611550488 -0700
+++ smpboot.c 2005-04-28 12:59:27.151093320 -0700
@@ -652,7 +652,7 @@
int i;
if (smp_num_siblings > 1) {
for_each_online_cpu (i) {
- if (cpu_core_id[cpu] == cpu_core_id[i]) {
+ if (cpu_to_node[cpu] == cpu_to_node[i]) {
siblings++;
cpu_set(i, cpu_sibling_map[cpu]);
}
On Thu, Apr 28, 2005 at 12:49:42PM -0700, YhLu wrote:
> Please refer to my patch about that.
>
> --- smpboot.o.c 2005-04-28 13:00:03.611550488 -0700
> +++ smpboot.c 2005-04-28 12:59:27.151093320 -0700
> @@ -652,7 +652,7 @@
> int i;
> if (smp_num_siblings > 1) {
> for_each_online_cpu (i) {
> - if (cpu_core_id[cpu] == cpu_core_id[i]) {
> + if (cpu_to_node[cpu] == cpu_to_node[i]) {
> siblings++;
> cpu_set(i, cpu_sibling_map[cpu]);
> }
This patch is wrong. It will break Intel systems and I think it is also not
the correct fix for the systems you are trying to fix.
Please don't do this.
thanks,
suresh
On Thu, Apr 21, 2005 at 07:38:07PM -0700, YhLu wrote:
> Andi,
>
> I tried 2.6.12-rc3 with dual way dual cpus.
>
> It seems right mapping should be
> CPU 0(2) -> Node 0 -> Core 0
> CPU 1(2) -> Node 0 -> Core 1
> CPU 2(2) -> Node 1 -> Core 0
> CPU 3(2) -> Node 1 -> Core 1
>
> instead of
>
> CPU 0(2) -> Node 0 -> Core 0
> CPU 1(2) -> Node 0 -> Core 0
> CPU 2(2) -> Node 1 -> Core 1
> CPU 3(2) -> Node 1 -> Core 1
Hmm, yes, something seems wrong. The last time I tested
it worked this way, but maybe the latest merge has broken
it again. I will check it later.
Are you sure you dont have a broken SRAT table? The SRAT
table will overwrite the mappings, so if it is wrong
the one Linux reports will be too.
-Andi
>
> YH
>
>
>
>
> CPU 0(2) -> Node 0 -> Core 0
> Using local APIC NMI watchdog using perfctr0
> enabled ExtINT on CPU#0
> ENABLING IO-APIC IRQs
> Using IO-APIC 4
> ...changing IO-APIC physical APIC ID to 4 ... ok.
> Using IO-APIC 5
> ...changing IO-APIC physical APIC ID to 5 ... ok.
> Using IO-APIC 6
> ...changing IO-APIC physical APIC ID to 6 ... ok.
> Using IO-APIC 7
> ...changing IO-APIC physical APIC ID to 7 ... ok.
> Synchronizing Arb IDs.
> ..TIMER: vector=0x31 pin1=0 pin2=2
> testing the IO APIC.......................
>
>
>
>
> .................................... done.
> Using local APIC timer interrupts.
> Detected 12.564 MHz APIC timer.
> Booting processor 1/1 rip 6000 rsp ffff81007ff99f58
> Initializing CPU#1
> masked ExtINT on CPU#1
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 1(2) -> Node 0 -> Core 0
> stepping 00
> Synced TSC of CPU 1 difference 30064769976
> Booting processor 2/2 rip 6000 rsp ffff81013ffa3f58
> Initializing CPU#2
> masked ExtINT on CPU#2
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 2(2) -> Node 1 -> Core 1
> stepping 00
> Synced TSC of CPU 2 difference 30064770021
> Booting processor 3/3 rip 6000 rsp ffff81007ff49f58
> Initializing CPU#3
> masked ExtINT on CPU#3
> CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> CPU: L2 Cache: 1024K (64 bytes/line)
> CPU 3(2) -> Node 1 -> Core 1
> stepping 00
> Synced TSC of CPU 3 difference 30064770021
> Brought up 4 CPUs
I'm using LinuxBIOS and there is no acpi in that. Also I have tried Normal
BIOS, it also produce that.
Did you check my patch? It fixed that.
regards
YH
> -----Original Message-----
> From: Andi Kleen [mailto:[email protected]]
> Sent: Monday, May 02, 2005 10:02 AM
> To: YhLu
> Cc: Andi Kleen; [email protected]
> Subject: Re: x86-64 dual core mapping
>
> On Thu, Apr 21, 2005 at 07:38:07PM -0700, YhLu wrote:
> > Andi,
> >
> > I tried 2.6.12-rc3 with dual way dual cpus.
> >
> > It seems right mapping should be
> > CPU 0(2) -> Node 0 -> Core 0
> > CPU 1(2) -> Node 0 -> Core 1
> > CPU 2(2) -> Node 1 -> Core 0
> > CPU 3(2) -> Node 1 -> Core 1
> >
> > instead of
> >
> > CPU 0(2) -> Node 0 -> Core 0
> > CPU 1(2) -> Node 0 -> Core 0
> > CPU 2(2) -> Node 1 -> Core 1
> > CPU 3(2) -> Node 1 -> Core 1
>
> Hmm, yes, something seems wrong. The last time I tested it
> worked this way, but maybe the latest merge has broken it
> again. I will check it later.
>
> Are you sure you dont have a broken SRAT table? The SRAT
> table will overwrite the mappings, so if it is wrong the one
> Linux reports will be too.
>
> -Andi
> >
> > YH
> >
> >
> >
> >
> > CPU 0(2) -> Node 0 -> Core 0
> > Using local APIC NMI watchdog using perfctr0 enabled ExtINT
> on CPU#0
> > ENABLING IO-APIC IRQs Using IO-APIC 4 ...changing IO-APIC physical
> > APIC ID to 4 ... ok.
> > Using IO-APIC 5
> > ...changing IO-APIC physical APIC ID to 5 ... ok.
> > Using IO-APIC 6
> > ...changing IO-APIC physical APIC ID to 6 ... ok.
> > Using IO-APIC 7
> > ...changing IO-APIC physical APIC ID to 7 ... ok.
> > Synchronizing Arb IDs.
> > ..TIMER: vector=0x31 pin1=0 pin2=2
> > testing the IO APIC.......................
> >
> >
> >
> >
> > .................................... done.
> > Using local APIC timer interrupts.
> > Detected 12.564 MHz APIC timer.
> > Booting processor 1/1 rip 6000 rsp ffff81007ff99f58
> Initializing CPU#1
> > masked ExtINT on CPU#1
> > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> > CPU: L2 Cache: 1024K (64 bytes/line)
> > CPU 1(2) -> Node 0 -> Core 0
> > stepping 00
> > Synced TSC of CPU 1 difference 30064769976 Booting
> processor 2/2 rip
> > 6000 rsp ffff81013ffa3f58 Initializing CPU#2 masked ExtINT on CPU#2
> > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> > CPU: L2 Cache: 1024K (64 bytes/line)
> > CPU 2(2) -> Node 1 -> Core 1
> > stepping 00
> > Synced TSC of CPU 2 difference 30064770021 Booting
> processor 3/3 rip
> > 6000 rsp ffff81007ff49f58 Initializing CPU#3 masked ExtINT on CPU#3
> > CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
> > CPU: L2 Cache: 1024K (64 bytes/line)
> > CPU 3(2) -> Node 1 -> Core 1
> > stepping 00
> > Synced TSC of CPU 3 difference 30064770021 Brought up 4 CPUs
>
On Mon, May 02, 2005 at 12:41:31PM -0700, YhLu wrote:
> I'm using LinuxBIOS and there is no acpi in that. Also I have tried Normal
> BIOS, it also produce that.
>
> Did you check my patch? It fixed that.
I dont think it is a correct, and Suresh is right that it
will break Intel setups.
I will investigate this evening and see if I can reproduce it
on Simnow.
-Andi
Andi,
resent. FYI
YH
before patch
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 0(2) -> Node 0 -> Core 0
Booting processor 1/1 rip 6000 rsp ffff81007ff99f58 Initializing CPU#1
masked ExtINT on CPU#1
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 1(2) -> Node 0 -> Core 0
stepping 00
Synced TSC of CPU 1 difference 21474835384 Booting processor 2/2 rip 6000
rsp ffff81013ffa3f58 Initializing CPU#2 masked ExtINT on CPU#2
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 2(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 2 difference 21474835425 Booting processor 3/3 rip 6000
rsp ffff81007ff49f58 Initializing CPU#3 masked ExtINT on CPU#3
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 3(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 3 difference 21474835425 Brought up 4 CPUs
~ # cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 3956.73
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 2
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 3
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 255
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
~ #
after patch
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 0(2) -> Node 0 -> Core 0
Booting processor 1/1 rip 6000 rsp ffff81007ff99f58 Initializing CPU#1
masked ExtINT on CPU#1
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 1(2) -> Node 0 -> Core 1
stepping 00
Synced TSC of CPU 1 difference 21474835384 Booting processor 2/2 rip 6000
rsp ffff81013ffa3f58 Initializing CPU#2 masked ExtINT on CPU#2
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 2(2) -> Node 1 -> Core 0
stepping 00
Synced TSC of CPU 2 difference 21474835425 Booting processor 3/3 rip 6000
rsp ffff81007ff49f58 Initializing CPU#3 masked ExtINT on CPU#3
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
CPU 3(2) -> Node 1 -> Core 1
stepping 00
Synced TSC of CPU 3 difference 21474835425 Brought up 4 CPUs
~ # cat /proc/cpuinfo
processor : 0
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 3956.73
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 1
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 2
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 1
siblings : 2
core id : 0
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
processor : 3
vendor_id : AuthenticAMD
cpu family : 15
model : 33
model name : unknown
stepping : 0
cpu MHz : 2010.342
cache size : 1024 KB
physical id : 1
siblings : 2
core id : 1
cpu cores : 2
fpu : yes
fpu_exception : yes
cpuid level : 1
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush mmx fxsr sse sse2 ht pni syscall y
bogomips : 4014.08
TLB size : 1024 4K pages
clflush size : 64
cache_alignment : 64
address sizes : 40 bits physical, 48 bits virtual
power management: ts fid vid ttp
~ #
> -----Original Message-----
> From: Andi Kleen [mailto:[email protected]]
> Sent: Monday, May 02, 2005 1:19 PM
> To: YhLu
> Cc: Andi Kleen; [email protected]
> Subject: Re: x86-64 dual core mapping
>
> On Mon, May 02, 2005 at 12:41:31PM -0700, YhLu wrote:
> > I'm using LinuxBIOS and there is no acpi in that. Also I have tried
> > Normal BIOS, it also produce that.
> >
> > Did you check my patch? It fixed that.
>
> I dont think it is a correct, and Suresh is right that it
> will break Intel setups.
>
> I will investigate this evening and see if I can reproduce it
> on Simnow.
>
> -Andi
>
On Mon, May 02, 2005 at 02:01:00PM -0700, YhLu wrote:
> Andi,
>
> resent. FYI
I retested with my tree and everything works for me as expected.
Well actually there is a problem with the core mappings,
but not on dual core, but on single core (more cosmetic than real)
It is possible that some patch is missing again in mainline.
I will sync up my patchkit next week and double check then
that mainline is in the same state as mine.
-Andi
Thanks.
For dual core cpu, if the BIOS or LinuxBIOS disable the dual core, the
kernel will treat core0 of node 1 as core 1 of node 0.....
YH
> -----Original Message-----
> From: Andi Kleen [mailto:[email protected]]
> Sent: Tuesday, May 03, 2005 7:25 AM
> To: YhLu
> Cc: Andi Kleen; [email protected]
> Subject: Re: x86-64 dual core mapping
>
> On Mon, May 02, 2005 at 02:01:00PM -0700, YhLu wrote:
> > Andi,
> >
> > resent. FYI
>
> I retested with my tree and everything works for me as expected.
> Well actually there is a problem with the core mappings, but
> not on dual core, but on single core (more cosmetic than real)
>
> It is possible that some patch is missing again in mainline.
> I will sync up my patchkit next week and double check then
> that mainline is in the same state as mine.
>
> -Andi
>
Andi,
Did you try "acpi=off" on you test?
YH
> -----Original Message-----
> From: Andi Kleen [mailto:[email protected]]
> Sent: Tuesday, May 03, 2005 7:25 AM
> To: YhLu
> Cc: Andi Kleen; [email protected]
> Subject: Re: x86-64 dual core mapping
>
> On Mon, May 02, 2005 at 02:01:00PM -0700, YhLu wrote:
> > Andi,
> >
> > resent. FYI
>
> I retested with my tree and everything works for me as expected.
> Well actually there is a problem with the core mappings, but
> not on dual core, but on single core (more cosmetic than real)
>
> It is possible that some patch is missing again in mainline.
> I will sync up my patchkit next week and double check then
> that mainline is in the same state as mine.
>
> -Andi
>
On Tue, May 03, 2005 at 05:18:15PM -0700, YhLu wrote:
> Andi,
>
> Did you try "acpi=off" on you test?
numa=noacpi yes which is equivalent.
Please wait until after the tree resync with this.
-Andi
Andi,
the dual core mapping in 2.6.12-rc4 is not right yet. you may need to try
"acpi=off"
YH