Changes since v9:
- Change description of "MIPI_DSI_HS_PKT_END_ALIGNED".
- Use mode_flags directly instead of another variable on patch [2/3].
- Add explanation of implementation in mtk_dsi.c on commit message of [2/3].
Changes since v8:
- Use mode_flags to control this limitation instead of "hs_packet_end_aligned".
- Add new bit definition "MIPI_DSI_HS_PKT_END_ALIGNED" for mode_flags.
Changes since v7:
- Rebase to kernel 5.16
- Add tags of reviewed-by and acked-by.
- Add detailed commit message for flag "hs_packet_end_aligned" in DSI common driver.
Changes since v6:
- Add "bool hs_packet_end_aligned" in "struct mipi_dsi_device" to control the dsi aligned.
- Config the "hs_packet_end_aligned" in ANX7725 .attach().
Changes since v5:
- Search the anx7625 compatible as flag to control dsi output aligned.
Changes since v4:
- Move "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null" before
"drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid".
- Retitle "dt-bindings: drm/bridge: anx7625: add force_dsi_end_without_null".
Rex-BC Chen (3):
drm/dsi: transfer DSI HS packets ending at the same time
drm/mediatek: implement the DSI HS packets aligned
drm/bridge: anx7625: config hs packets end aligned to avoid screen shift
drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
include/drm/drm_mipi_dsi.h | 2 ++
3 files changed, 16 insertions(+), 1 deletion(-)
--
2.18.0
This device requires the packets on lanes aligned at the end to fix
screen shift or scroll.
Signed-off-by: Jitao Shi <[email protected]>
Signed-off-by: Rex-BC Chen <[email protected]>
Acked-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Xin Ji <[email protected]>
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
index 2346dbcc505f..fe32ab0878ae 100644
--- a/drivers/gpu/drm/bridge/analogix/anx7625.c
+++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
@@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
- MIPI_DSI_MODE_VIDEO_HSE;
+ MIPI_DSI_MODE_VIDEO_HSE |
+ MIPI_DSI_HS_PKT_END_ALIGNED;
ret = devm_mipi_dsi_attach(dev, dsi);
if (ret) {
--
2.18.0
Some DSI RX devices (for example, anx7625) require last alignment of
packets on all lanes after each row of data is sent.
Otherwise, there will be some issues of shift or scroll for screen.
Take horizontal_sync_active_byte for a example,
we roundup the HSA packet data to lane number, and the subtraction of 2
is the packet data value added by the roundup operation, making the
long packets are integer multiples of lane number.
This value (2) varies with the lane number, and that is the reason we
do this operation when the lane number is 4.
In the previous operation of function "mtk_dsi_config_vdo_timing",
the length of HSA and HFP data packets has been adjusted to an
integration multiple of lane number.
Since the number of RGB data packets cannot be guaranteed to be an
integer multiple of lane number, we modify the data packet length of
HBP so that the number of HBP + RGB is equal to the lane number.
So after sending a line of data (HSA + HBP + RGB + HFP), the data
lanes are aligned.
Signed-off-by: Jitao Shi <[email protected]>
Signed-off-by: Rex-BC Chen <[email protected]>
Signed-off-by: Xinlei Lee <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5d90d2eb0019..e91b3fff4342 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
}
+ if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
+ (dsi->lanes == 4)) {
+ horizontal_sync_active_byte =
+ roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
+ horizontal_frontporch_byte =
+ roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
+ horizontal_backporch_byte =
+ roundup(horizontal_backporch_byte, dsi->lanes) - 2;
+ horizontal_backporch_byte -=
+ (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
+ }
+
writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
--
2.18.0
On 19.01.2022 03:25, Rex-BC Chen wrote:
> This device requires the packets on lanes aligned at the end to fix
> screen shift or scroll.
>
> Signed-off-by: Jitao Shi <[email protected]>
> Signed-off-by: Rex-BC Chen <[email protected]>
> Acked-by: AngeloGioacchino Del Regno <[email protected]>
> Reviewed-by: Xin Ji <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
Regards
Andrzej
> ---
> drivers/gpu/drm/bridge/analogix/anx7625.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c
> index 2346dbcc505f..fe32ab0878ae 100644
> --- a/drivers/gpu/drm/bridge/analogix/anx7625.c
> +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c
> @@ -1673,7 +1673,8 @@ static int anx7625_attach_dsi(struct anx7625_data *ctx)
> dsi->format = MIPI_DSI_FMT_RGB888;
> dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
> MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> - MIPI_DSI_MODE_VIDEO_HSE;
> + MIPI_DSI_MODE_VIDEO_HSE |
> + MIPI_DSI_HS_PKT_END_ALIGNED;
>
> ret = devm_mipi_dsi_attach(dev, dsi);
> if (ret) {
Il 19/01/22 09:35, Andrzej Hajda ha scritto:
>
> On 19.01.2022 03:25, Rex-BC Chen wrote:
>> Some DSI RX devices (for example, anx7625) require last alignment of
>> packets on all lanes after each row of data is sent.
>> Otherwise, there will be some issues of shift or scroll for screen.
>>
>> Take horizontal_sync_active_byte for a example,
>> we roundup the HSA packet data to lane number, and the subtraction of 2
>> is the packet data value added by the roundup operation, making the
>> long packets are integer multiples of lane number.
>> This value (2) varies with the lane number, and that is the reason we
>> do this operation when the lane number is 4.
>>
>> In the previous operation of function "mtk_dsi_config_vdo_timing",
>> the length of HSA and HFP data packets has been adjusted to an
>> integration multiple of lane number.
>> Since the number of RGB data packets cannot be guaranteed to be an
>> integer multiple of lane number, we modify the data packet length of
>> HBP so that the number of HBP + RGB is equal to the lane number.
>> So after sending a line of data (HSA + HBP + RGB + HFP), the data
>> lanes are aligned.
>>
>> Signed-off-by: Jitao Shi <[email protected]>
>> Signed-off-by: Rex-BC Chen <[email protected]>
>> Signed-off-by: Xinlei Lee <[email protected]>
>
> Reviewed-by: Andrzej Hajda <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
>
> Regards
>
> Andrzej
>
>> ---
>> drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
>> index 5d90d2eb0019..e91b3fff4342 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
>> @@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
>> DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
>> }
>> + if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
>> + (dsi->lanes == 4)) {
>> + horizontal_sync_active_byte =
>> + roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
>> + horizontal_frontporch_byte =
>> + roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
>> + horizontal_backporch_byte =
>> + roundup(horizontal_backporch_byte, dsi->lanes) - 2;
>> + horizontal_backporch_byte -=
>> + (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
>> + }
>> +
>> writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
>> writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
>> writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
On 19.01.2022 03:25, Rex-BC Chen wrote:
> Some DSI RX devices (for example, anx7625) require last alignment of
> packets on all lanes after each row of data is sent.
> Otherwise, there will be some issues of shift or scroll for screen.
>
> Take horizontal_sync_active_byte for a example,
> we roundup the HSA packet data to lane number, and the subtraction of 2
> is the packet data value added by the roundup operation, making the
> long packets are integer multiples of lane number.
> This value (2) varies with the lane number, and that is the reason we
> do this operation when the lane number is 4.
>
> In the previous operation of function "mtk_dsi_config_vdo_timing",
> the length of HSA and HFP data packets has been adjusted to an
> integration multiple of lane number.
> Since the number of RGB data packets cannot be guaranteed to be an
> integer multiple of lane number, we modify the data packet length of
> HBP so that the number of HBP + RGB is equal to the lane number.
> So after sending a line of data (HSA + HBP + RGB + HFP), the data
> lanes are aligned.
>
> Signed-off-by: Jitao Shi <[email protected]>
> Signed-off-by: Rex-BC Chen <[email protected]>
> Signed-off-by: Xinlei Lee <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
Regards
Andrzej
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 5d90d2eb0019..e91b3fff4342 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
> }
>
> + if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
> + (dsi->lanes == 4)) {
> + horizontal_sync_active_byte =
> + roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> + horizontal_frontporch_byte =
> + roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> + horizontal_backporch_byte =
> + roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> + horizontal_backporch_byte -=
> + (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
> + }
> +
> writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
Hi, Rex:
Rex-BC Chen <[email protected]> 於 2022年1月19日 週三 上午10:26寫道：
>
> Some DSI RX devices (for example, anx7625) require last alignment of
> packets on all lanes after each row of data is sent.
> Otherwise, there will be some issues of shift or scroll for screen.
>
> Take horizontal_sync_active_byte for a example,
> we roundup the HSA packet data to lane number, and the subtraction of 2
> is the packet data value added by the roundup operation, making the
> long packets are integer multiples of lane number.
> This value (2) varies with the lane number, and that is the reason we
> do this operation when the lane number is 4.
>
> In the previous operation of function "mtk_dsi_config_vdo_timing",
> the length of HSA and HFP data packets has been adjusted to an
> integration multiple of lane number.
> Since the number of RGB data packets cannot be guaranteed to be an
> integer multiple of lane number, we modify the data packet length of
> HBP so that the number of HBP + RGB is equal to the lane number.
> So after sending a line of data (HSA + HBP + RGB + HFP), the data
> lanes are aligned.
Acked-by: Chun-Kuang Hu <[email protected]>
>
> Signed-off-by: Jitao Shi <[email protected]>
> Signed-off-by: Rex-BC Chen <[email protected]>
> Signed-off-by: Xinlei Lee <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 5d90d2eb0019..e91b3fff4342 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -500,6 +500,18 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
> DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n");
> }
>
> + if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
> + (dsi->lanes == 4)) {
> + horizontal_sync_active_byte =
> + roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
> + horizontal_frontporch_byte =
> + roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
> + horizontal_backporch_byte =
> + roundup(horizontal_backporch_byte, dsi->lanes) - 2;
> + horizontal_backporch_byte -=
> + (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
> + }
> +
> writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
> writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
> writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
> --
> 2.18.0
>