This series adds initial support for latest new SoC, J7200, from Texas Instruments.
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded products.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Testing:
- Boot log: https://pastebin.ubuntu.com/p/FvpzWjf7tw/
- ./scripts/checkpatch --strict
- Few warningns about Line length exceeding 100 columns.
But these are corresponding to comments
- v8make dtbs_check
- DT_SCHEMA_FLAGS="-u"
DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml"
v8make dtbs_check
- DT_SCHEMA_FLAGS="-u"
DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml"
v8make dt_binding_check
Lokesh Vutla (4):
dt-bindings: arm: ti: Add bindings for J7200 SoC
dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
arm64: dts: ti: Add support for J7200 SoC
arm64: dts: ti: Add support for J7200 Common Processor Board
.../devicetree/bindings/arm/ti/k3.txt | 26 ---
.../devicetree/bindings/arm/ti/k3.yaml | 28 +++
MAINTAINERS | 2 +-
arch/arm64/boot/dts/ti/Makefile | 3 +-
.../dts/ti/k3-j7200-common-proc-board.dts | 64 ++++++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
9 files changed, 572 insertions(+), 28 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
--
2.27.0
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Signed-off-by: Lokesh Vutla <[email protected]>
---
Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
index 333e7256126a..33419cce0afa 100644
--- a/Documentation/devicetree/bindings/arm/ti/k3.txt
+++ b/Documentation/devicetree/bindings/arm/ti/k3.txt
@@ -16,6 +16,9 @@ architecture it uses, using one of the following compatible values:
- J721E
compatible = "ti,j721e";
+- J7200
+ compatible = "ti,j7200";
+
Boards
------
--
2.27.0
Convert TI K3 Board/SoC bindings to DT schema format.
Signed-off-by: Lokesh Vutla <[email protected]>
---
.../devicetree/bindings/arm/ti/k3.txt | 29 -------------------
.../devicetree/bindings/arm/ti/k3.yaml | 28 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 29 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
deleted file mode 100644
index 33419cce0afa..000000000000
--- a/Documentation/devicetree/bindings/arm/ti/k3.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Texas Instruments K3 Multicore SoC architecture device tree bindings
---------------------------------------------------------------------
-
-Platforms based on Texas Instruments K3 Multicore SoC architecture
-shall follow the following scheme:
-
-SoCs
-----
-
-Each device tree root node must specify which exact SoC in K3 Multicore SoC
-architecture it uses, using one of the following compatible values:
-
-- AM654
- compatible = "ti,am654";
-
-- J721E
- compatible = "ti,j721e";
-
-- J7200
- compatible = "ti,j7200";
-
-Boards
-------
-
-In addition, each device tree root node must specify which one or more
-of the following board-specific compatible values:
-
-- AM654 EVM
- compatible = "ti,am654-evm", "ti,am654";
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml
new file mode 100644
index 000000000000..b8ecb430429f
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/ti/k3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments K3 Multicore SoC architecture device tree bindings
+
+maintainers:
+ - Nishanth Menon <[email protected]>
+
+description: |
+ Platforms based on Texas Instruments K3 Multicore SoC architecture
+ shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ti,am654-evm
+ - const: ti,am654
+ - items:
+ - const: ti,j721e
+ - items:
+ - const: ti,j7200
diff --git a/MAINTAINERS b/MAINTAINERS
index d53db30d1365..4f2092e5282d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2597,7 +2597,7 @@ M: Tero Kristo <[email protected]>
M: Nishanth Menon <[email protected]>
L: [email protected] (moderated for non-subscribers)
S: Supported
-F: Documentation/devicetree/bindings/arm/ti/k3.txt
+F: Documentation/devicetree/bindings/arm/ti/k3.yaml
F: arch/arm64/boot/dts/ti/Makefile
F: arch/arm64/boot/dts/ti/k3-*
F: include/dt-bindings/pinctrl/k3.h
--
2.27.0
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
and I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Signed-off-by: Lokesh Vutla <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
3 files changed, 448 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
new file mode 100644
index 000000000000..70c8f7e941fb
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J7200 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ msmc_ram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x70000000 0x0 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x70000000 0x100000>;
+
+ atf-sram@0 {
+ reg = <0x0 0x20000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01900000 0x00 0x100000>; /* GICR */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_navss: navss@30000000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+
+ secure_proxy_main: mailbox@32c00000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x32c00000 0x00 0x100000>,
+ <0x00 0x32400000 0x00 0x100000>,
+ <0x00 0x32800000 0x00 0x100000>;
+ interrupt-names = "rx_011";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ main_pmx0: pinmux@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x0 0x11c000 0x0 0x2b4>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 280 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 281 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 282 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 283 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart7: serial@2870000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02870000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 284 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart8: serial@2880000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02880000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 285 2>;
+ clock-names = "fclk";
+ };
+
+ main_uart9: serial@2890000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x02890000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 286 2>;
+ clock-names = "fclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
new file mode 100644
index 000000000000..670e4c7cd9fe
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu_wakeup {
+ dmsc: dmsc@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+
+ mbox-names = "rx", "tx";
+
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+
+ reg-names = "debug_messages";
+ reg = <0x00 0x44083000 0x0 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ chipid@43000014 {
+ compatible = "ti,am654-chipid";
+ reg = <0x0 0x43000014 0x0 0x4>;
+ };
+
+ wkup_pmx0: pinmux@4301c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x00 0x4301c000 0x00 0x178>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ mcu_ram: sram@41c00000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x41c00000 0x00 0x100000>;
+ ranges = <0x0 0x00 0x41c00000 0x100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ wkup_uart0: serial@42300000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x42300000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 287 2>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart0: serial@40a00000 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 2>;
+ clock-names = "fclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
new file mode 100644
index 000000000000..f7cee5a4ca1a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J7200 SoC Family
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 J7200 SoC";
+ compatible = "ti,j7200";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial1 = &mcu_uart0;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ serial9 = &main_uart7;
+ serial10 = &main_uart8;
+ serial11 = &main_uart9;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a72";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a72";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <2048>;
+ next-level-cache = <&msmc_l3>;
+ };
+
+ msmc_l3: l3-cache0 {
+ compatible = "cache";
+ cache-level = <3>;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a72_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@100000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
+ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
+
+ /* MCUSS_WKUP Range */
+ <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>;
+
+ cbass_mcu_wakeup: bus@28380000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
+ <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
+ <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
+ <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
+ <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
+ <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
+ <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
+ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
+ <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>; /* FSS OSPI0/1 data region 0 */
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-j7200-main.dtsi"
+#include "k3-j7200-mcu-wakeup.dtsi"
--
2.27.0
Add support for J7200 Common Processor Board.
The EVM architecture is very similar to J721E as follows:
+------------------------------------------------------+
| +-------------------------------------------+ |
| | | |
| | Add-on Card 1 Options | |
| | | |
| +-------------------------------------------+ |
| |
| |
| +-------------------+ |
| | | |
| | SOM | |
| +--------------+ | | |
| | | | | |
| | Add-on | +-------------------+ |
| | Card 2 | | Power Supply
| | Options | | |
| | | | |
| +--------------+ | <---
+------------------------------------------------------+
Common Processor Board
Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality.
Note:
* The minimum configuration required to boot up the board is System On
Module(SOM) + Common Processor Board.
* Since there is just a single SOM and Common Processor Board, we are
maintaining common processor board as the base dts and SOM as the dtsi
that we include. In the future as more SOM's appear, we should move
common processor board as a dtsi and include configurations as dts.
* All daughter cards beyond the basic boards shall be maintained as
overlays.
* Since J7200 is derivative of J721E re-using the CONFIG_ARCH_K3_J721E_SOC
config for building J7200 dts files.
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Peter Ujfalusi <[email protected]>
---
arch/arm64/boot/dts/ti/Makefile | 3 +-
.../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++++++++
3 files changed, 95 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index b397945fdf73..7b0b176eab1b 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -8,4 +8,5 @@
dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
-dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb \
+ k3-j7200-common-proc-board.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
new file mode 100644
index 000000000000..e27069317c4e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j7200-som-p0.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+};
+
+&wkup_uart0 {
+ /* Wakeup UART is used by System firmware */
+ status = "disabled";
+};
+
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
+&main_uart2 {
+ /* MAIN UART 2 is used by R5F firmware */
+ status = "disabled";
+};
+
+&main_uart3 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart4 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart5 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart6 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart7 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart8 {
+ /* UART not brought out */
+ status = "disabled";
+};
+
+&main_uart9 {
+ /* UART not brought out */
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
new file mode 100644
index 000000000000..22fc50bd5c4c
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j7200.dtsi"
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ /* 4G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+ <0x00000008 0x80000000 0x00000000 0x80000000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
--
2.27.0
On 7/23/20 3:46 AM, Lokesh Vutla wrote:
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded
> products.
>
> Some highlights of this SoC are:
> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
> capable dual Cortex-R5F MCUs and a Centralized Device Management and
> Security Controller (DMSC).
> * Configurable L3 Cache and IO-coherent architecture with high data
> throughput capable distributed DMA architecture under NAVSS.
> * Integrated Ethernet switch supporting up to a total of 4 external ports
> in addition to legacy Ethernet switch of up to 2 ports.
> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
> and I2C, eCAP/eQEP, eHRPWM among other peripherals.
> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
> management.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Signed-off-by: Lokesh Vutla <[email protected]>
Reviewed-by: Suman Anna <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
> 3 files changed, 448 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> new file mode 100644
> index 000000000000..70c8f7e941fb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -0,0 +1,199 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family Main Domain peripherals
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_main {
> + msmc_ram: sram@70000000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x70000000 0x0 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x70000000 0x100000>;
> +
> + atf-sram@0 {
> + reg = <0x0 0x20000>;
> + };
> + };
> +
> + gic500: interrupt-controller@1800000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
> + <0x00 0x01900000 0x00 0x100000>; /* GICR */
> +
> + /* vcpumntirq: virtual CPU interface maintenance interrupt */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gic_its: msi-controller@1820000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x00 0x01820000 0x00 0x10000>;
> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + main_navss: navss@30000000 {
> + compatible = "simple-mfd";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
> +
> + secure_proxy_main: mailbox@32c00000 {
> + compatible = "ti,am654-secure-proxy";
> + #mbox-cells = <1>;
> + reg-names = "target_data", "rt", "scfg";
> + reg = <0x00 0x32c00000 0x00 0x100000>,
> + <0x00 0x32400000 0x00 0x100000>,
> + <0x00 0x32800000 0x00 0x100000>;
> + interrupt-names = "rx_011";
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + main_pmx0: pinmux@11c000 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x0 0x11c000 0x0 0x2b4>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + main_uart0: serial@2800000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02800000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 146 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart1: serial@2810000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02810000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 278 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart2: serial@2820000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02820000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart3: serial@2830000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02830000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 280 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart4: serial@2840000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02840000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 281 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart5: serial@2850000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02850000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 282 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart6: serial@2860000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02860000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 283 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart7: serial@2870000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02870000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 284 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart8: serial@2880000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02880000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 285 2>;
> + clock-names = "fclk";
> + };
> +
> + main_uart9: serial@2890000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x02890000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 286 2>;
> + clock-names = "fclk";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> new file mode 100644
> index 000000000000..670e4c7cd9fe
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -0,0 +1,84 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_mcu_wakeup {
> + dmsc: dmsc@44083000 {
> + compatible = "ti,k2g-sci";
> + ti,host-id = <12>;
> +
> + mbox-names = "rx", "tx";
> +
> + mboxes= <&secure_proxy_main 11>,
> + <&secure_proxy_main 13>;
> +
> + reg-names = "debug_messages";
> + reg = <0x00 0x44083000 0x0 0x1000>;
> +
> + k3_pds: power-controller {
> + compatible = "ti,sci-pm-domain";
> + #power-domain-cells = <2>;
> + };
> +
> + k3_clks: clocks {
> + compatible = "ti,k2g-sci-clk";
> + #clock-cells = <2>;
> + };
> +
> + k3_reset: reset-controller {
> + compatible = "ti,sci-reset";
> + #reset-cells = <2>;
> + };
> + };
> +
> + chipid@43000014 {
> + compatible = "ti,am654-chipid";
> + reg = <0x0 0x43000014 0x0 0x4>;
> + };
> +
> + wkup_pmx0: pinmux@4301c000 {
> + compatible = "pinctrl-single";
> + /* Proxy 0 addressing */
> + reg = <0x00 0x4301c000 0x00 0x178>;
> + #pinctrl-cells = <1>;
> + pinctrl-single,register-width = <32>;
> + pinctrl-single,function-mask = <0xffffffff>;
> + };
> +
> + mcu_ram: sram@41c00000 {
> + compatible = "mmio-sram";
> + reg = <0x00 0x41c00000 0x00 0x100000>;
> + ranges = <0x0 0x00 0x41c00000 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +
> + wkup_uart0: serial@42300000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x42300000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <48000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 287 2>;
> + clock-names = "fclk";
> + };
> +
> + mcu_uart0: serial@40a00000 {
> + compatible = "ti,j721e-uart", "ti,am654-uart";
> + reg = <0x00 0x40a00000 0x00 0x100>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <96000000>;
> + current-speed = <115200>;
> + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 149 2>;
> + clock-names = "fclk";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> new file mode 100644
> index 000000000000..f7cee5a4ca1a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
> @@ -0,0 +1,165 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/k3.h>
> +#include <dt-bindings/soc/ti,sci_pm_domain.h>
> +
> +/ {
> + model = "Texas Instruments K3 J7200 SoC";
> + compatible = "ti,j7200";
> + interrupt-parent = <&gic500>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + serial0 = &wkup_uart0;
> + serial1 = &mcu_uart0;
> + serial2 = &main_uart0;
> + serial3 = &main_uart1;
> + serial4 = &main_uart2;
> + serial5 = &main_uart3;
> + serial6 = &main_uart4;
> + serial7 = &main_uart5;
> + serial8 = &main_uart6;
> + serial9 = &main_uart7;
> + serial10 = &main_uart8;
> + serial11 = &main_uart9;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu-map {
> + cluster0: cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> +
> + };
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a72";
> + reg = <0x000>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a72";
> + reg = <0x001>;
> + device_type = "cpu";
> + enable-method = "psci";
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&L2_0>;
> + };
> + };
> +
> + L2_0: l2-cache0 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + next-level-cache = <&msmc_l3>;
> + };
> +
> + msmc_l3: l3-cache0 {
> + compatible = "cache";
> + cache-level = <3>;
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> + };
> +
> + a72_timer0: timer-cl0-cpu0 {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
> + };
> +
> + pmu: pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + cbass_main: bus@100000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
> + <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
> + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
> + <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
> + <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
> + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT */
> +
> + /* MCUSS_WKUP Range */
> + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>;
> +
> + cbass_mcu_wakeup: bus@28380000 {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>; /* FSS OSPI0/1 data region 0 */
> + };
> + };
> +};
> +
> +/* Now include the peripherals for each bus segments */
> +#include "k3-j7200-main.dtsi"
> +#include "k3-j7200-mcu-wakeup.dtsi"
>
On 7/23/20 3:46 AM, Lokesh Vutla wrote:
> Add support for J7200 Common Processor Board.
> The EVM architecture is very similar to J721E as follows:
>
> +------------------------------------------------------+
> | +-------------------------------------------+ |
> | | | |
> | | Add-on Card 1 Options | |
> | | | |
> | +-------------------------------------------+ |
> | |
> | |
> | +-------------------+ |
> | | | |
> | | SOM | |
> | +--------------+ | | |
> | | | | | |
> | | Add-on | +-------------------+ |
> | | Card 2 | | Power Supply
> | | Options | | |
> | | | | |
> | +--------------+ | <---
> +------------------------------------------------------+
> Common Processor Board
>
> Common Processor board is the baseboard that has most of the actual
> connectors, power supply etc. A SOM (System on Module) is plugged on
> to the common processor board and this contains the SoC, PMIC, DDR and
> basic high speed components necessary for functionality.
>
> Note:
> * The minimum configuration required to boot up the board is System On
> Module(SOM) + Common Processor Board.
> * Since there is just a single SOM and Common Processor Board, we are
> maintaining common processor board as the base dts and SOM as the dtsi
> that we include. In the future as more SOM's appear, we should move
> common processor board as a dtsi and include configurations as dts.
> * All daughter cards beyond the basic boards shall be maintained as
> overlays.
> * Since J7200 is derivative of J721E re-using the CONFIG_ARCH_K3_J721E_SOC
> config for building J7200 dts files.
>
> Signed-off-by: Lokesh Vutla <[email protected]>
> Signed-off-by: Peter Ujfalusi <[email protected]>
Reviewed-by: Suman Anna <[email protected]>
> ---
> arch/arm64/boot/dts/ti/Makefile | 3 +-
> .../dts/ti/k3-j7200-common-proc-board.dts | 64 +++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++++++++
> 3 files changed, 95 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index b397945fdf73..7b0b176eab1b 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -8,4 +8,5 @@
>
> dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
>
> -dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb
> +dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb \
> + k3-j7200-common-proc-board.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> new file mode 100644
> index 000000000000..e27069317c4e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-j7200-som-p0.dtsi"
> +
> +/ {
> + chosen {
> + stdout-path = "serial2:115200n8";
> + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
> + };
> +};
> +
> +&wkup_uart0 {
> + /* Wakeup UART is used by System firmware */
> + status = "disabled";
> +};
> +
> +&main_uart0 {
> + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
> +};
> +
> +&main_uart2 {
> + /* MAIN UART 2 is used by R5F firmware */
> + status = "disabled";
> +};
> +
> +&main_uart3 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart4 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart5 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart6 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart7 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart8 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart9 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> new file mode 100644
> index 000000000000..22fc50bd5c4c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-j7200.dtsi"
> +
> +/ {
> + memory@80000000 {
> + device_type = "memory";
> + /* 4G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> + <0x00000008 0x80000000 0x00000000 0x80000000>;
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> + };
> +};
>
On 23/07/2020 11:46, Lokesh Vutla wrote:
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded
> products.
>
> Some highlights of this SoC are:
> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
> capable dual Cortex-R5F MCUs and a Centralized Device Management and
> Security Controller (DMSC).
> * Configurable L3 Cache and IO-coherent architecture with high data
> throughput capable distributed DMA architecture under NAVSS.
> * Integrated Ethernet switch supporting up to a total of 4 external ports
> in addition to legacy Ethernet switch of up to 2 ports.
> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
> and I2C, eCAP/eQEP, eHRPWM among other peripherals.
> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
> management.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Signed-off-by: Lokesh Vutla <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
> 3 files changed, 448 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> new file mode 100644
> index 000000000000..70c8f7e941fb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -0,0 +1,199 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for J7200 SoC Family Main Domain peripherals
> + *
> + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +&cbass_main {
> + msmc_ram: sram@70000000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x70000000 0x0 0x100000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x70000000 0x100000>;
> +
> + atf-sram@0 {
> + reg = <0x0 0x20000>;
> + };
> + };
> +
> + gic500: interrupt-controller@1800000 {
> + compatible = "arm,gic-v3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
> + <0x00 0x01900000 0x00 0x100000>; /* GICR */
> +
> + /* vcpumntirq: virtual CPU interface maintenance interrupt */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gic_its: msi-controller@1820000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x00 0x01820000 0x00 0x10000>;
> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + main_navss: navss@30000000 {
> + compatible = "simple-mfd";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
Can we return back
ti,sci-dev-id = <199>;
here? it's needed for DMA PSI-L pairing.
Option: add it as part of dma/net submission.
[...]
--
Best regards,
grygorii
On 23/07/2020 11:46, Lokesh Vutla wrote:
> This series adds initial support for latest new SoC, J7200, from Texas Instruments.
>
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded products.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Testing:
> - Boot log: https://pastebin.ubuntu.com/p/FvpzWjf7tw/
> - ./scripts/checkpatch --strict
> - Few warningns about Line length exceeding 100 columns.
> But these are corresponding to comments
> - v8make dtbs_check
> - DT_SCHEMA_FLAGS="-u"
> DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml"
> v8make dtbs_check
> - DT_SCHEMA_FLAGS="-u"
> DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml"
> v8make dt_binding_check
>
> Lokesh Vutla (4):
> dt-bindings: arm: ti: Add bindings for J7200 SoC
> dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
> arm64: dts: ti: Add support for J7200 SoC
> arm64: dts: ti: Add support for J7200 Common Processor Board
>
> .../devicetree/bindings/arm/ti/k3.txt | 26 ---
> .../devicetree/bindings/arm/ti/k3.yaml | 28 +++
> MAINTAINERS | 2 +-
> arch/arm64/boot/dts/ti/Makefile | 3 +-
> .../dts/ti/k3-j7200-common-proc-board.dts | 64 ++++++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++
> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
> 9 files changed, 572 insertions(+), 28 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
> create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
>
I have networking enabled on top of this series here.
ssh://[email protected]/~x1045550/ti-priv-linux-kernel.git ti-linux-5.4.y-for-next-pull
But DMA failed for Main domain.
0.781005] ti-udma 31150000.dma-controller: NAVSS ti,sci-dev-id read failure -22
[ 0.788684] ti-udma: probe of 31150000.dma-controller failed with error -22
http://lcpdresults.itg.ti.com/launcher/results/8013
Is there anything (except my comment for patch 3) which prevents this from been merged?
--
Best regards,
grygorii
Hi Grygorii,
On 7/28/20 2:16 PM, Grygorii Strashko wrote:
>
>
> On 23/07/2020 11:46, Lokesh Vutla wrote:
>> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
>> It is targeted for automotive gateway, vehicle compute systems,
>> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
>> The SoC aims to meet the complex processing needs of modern embedded
>> products.
>>
>> Some highlights of this SoC are:
>> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
>> capable dual Cortex-R5F MCUs and a Centralized Device Management and
>> Security Controller (DMSC).
>> * Configurable L3 Cache and IO-coherent architecture with high data
>> throughput capable distributed DMA architecture under NAVSS.
>> * Integrated Ethernet switch supporting up to a total of 4 external ports
>> in addition to legacy Ethernet switch of up to 2 ports.
>> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
>> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C
>> and I2C, eCAP/eQEP, eHRPWM among other peripherals.
>> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
>> management.
>>
>> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
>> for further details: https://www.ti.com/lit/pdf/spruiu1
>>
>> Signed-off-by: Lokesh Vutla <[email protected]>
>> ---
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
>> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
>> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
>> 3 files changed, 448 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> new file mode 100644
>> index 000000000000..70c8f7e941fb
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> @@ -0,0 +1,199 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Device Tree Source for J7200 SoC Family Main Domain peripherals
>> + *
>> + * Copyright (C) 2020 Texas Instruments Incorporated -
>> https://www.ti.com/
>> + */
>> +
>> +&cbass_main {
>> + msmc_ram: sram@70000000 {
>> + compatible = "mmio-sram";
>> + reg = <0x0 0x70000000 0x0 0x100000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x0 0x70000000 0x100000>;
>> +
>> + atf-sram@0 {
>> + reg = <0x0 0x20000>;
>> + };
>> + };
>> +
>> + gic500: interrupt-controller@1800000 {
>> + compatible = "arm,gic-v3";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
>> + <0x00 0x01900000 0x00 0x100000>; /* GICR */
>> +
>> + /* vcpumntirq: virtual CPU interface maintenance interrupt */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + gic_its: msi-controller@1820000 {
>> + compatible = "arm,gic-v3-its";
>> + reg = <0x00 0x01820000 0x00 0x10000>;
>> + socionext,synquacer-pre-its = <0x1000000 0x400000>;
>> + msi-controller;
>> + #msi-cells = <1>;
>> + };
>> + };
>> +
>> + main_navss: navss@30000000 {
>> + compatible = "simple-mfd";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
>
> Can we return back
> ti,sci-dev-id = <199>;
>
> here? it's needed for DMA PSI-L pairing.
Oh, I wasn't aware of this. Lokesh removed it based on my earlier
comments. Is this used by more than one driver? Anytime you see a
ti,sci-dev-id, you would also expect to see the ti,sci reference in
general for that driver to really leverage it.
The lack of a specific binding for this node also makes one think it is
not needed.
>
> Option: add it as part of dma/net submission.
Yeah, I think we should go with this approach on upstream if we aren't
respinning the series. Any reason, this couldn't be added to the udma
node itself?
regards
Suman
On 28/07/2020 22:19, Grygorii Strashko wrote:
>
>
> On 23/07/2020 11:46, Lokesh Vutla wrote:
>> This series adds initial support for latest new SoC, J7200, from Texas Instruments.
>>
>> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
>> It is targeted for for automotive gateway, vehicle compute systems,
>> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
>> The SoC aims to meet the complex processing needs of modern embedded products.
>>
>> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
>> for further details: https://www.ti.com/lit/pdf/spruiu1
>>
>> Testing:
>> - Boot log: https://pastebin.ubuntu.com/p/FvpzWjf7tw/
>> - ./scripts/checkpatch --strict
>> - Few warningns about Line length exceeding 100 columns.
>> But these are corresponding to comments
>> - v8make dtbs_check
>> - DT_SCHEMA_FLAGS="-u"
>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml"
>> v8make dtbs_check
>> - DT_SCHEMA_FLAGS="-u"
>> DT_SCHEMA_FILES="Documentation/devicetree/bindings/arm/ti/k3.yaml"
>> v8make dt_binding_check
>>
>> Lokesh Vutla (4):
>> dt-bindings: arm: ti: Add bindings for J7200 SoC
>> dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schema
>> arm64: dts: ti: Add support for J7200 SoC
>> arm64: dts: ti: Add support for J7200 Common Processor Board
>>
>> .../devicetree/bindings/arm/ti/k3.txt | 26 ---
>> .../devicetree/bindings/arm/ti/k3.yaml | 28 +++
>> MAINTAINERS | 2 +-
>> arch/arm64/boot/dts/ti/Makefile | 3 +-
>> .../dts/ti/k3-j7200-common-proc-board.dts | 64 ++++++
>> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 199 ++++++++++++++++++
>> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 84 ++++++++
>> arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 29 +++
>> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 165 +++++++++++++++
>> 9 files changed, 572 insertions(+), 28 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/arm/ti/k3.txt
>> create mode 100644 Documentation/devicetree/bindings/arm/ti/k3.yaml
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi
>> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200.dtsi
>>
>
> I have networking enabled on top of this series here.
>
> ssh://[email protected]/~x1045550/ti-priv-linux-kernel.git ti-linux-5.4.y-for-next-pull
>
> But DMA failed for Main domain.
> 0.781005] ti-udma 31150000.dma-controller: NAVSS ti,sci-dev-id read failure -22
> [ 0.788684] ti-udma: probe of 31150000.dma-controller failed with error -22
>
> http://lcpdresults.itg.ti.com/launcher/results/8013
>
> Is there anything (except my comment for patch 3) which prevents this from been merged?
>
Sry. Pls. ignore this mail.
--
Best regards,
grygorii
On 14:16-20200723, Lokesh Vutla wrote:
> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
> It is targeted for automotive gateway, vehicle compute systems,
> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
> The SoC aims to meet the complex processing needs of modern embedded
> products.
>
> Some highlights of this SoC are:
> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
> capable dual Cortex-R5F MCUs and a Centralized Device Management and
> Security Controller (DMSC).
> * Configurable L3 Cache and IO-coherent architecture with high data
> throughput capable distributed DMA architecture under NAVSS.
> * Integrated Ethernet switch supporting up to a total of 4 external ports
> in addition to legacy Ethernet switch of up to 2 ports.
> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
> I2C, eCAP/eQEP, eHRPWM among other peripherals.
> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
> management.
>
> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
> for further details: https://www.ti.com/lit/pdf/spruiu1
>
> Signed-off-by: Lokesh Vutla <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
> index 333e7256126a..33419cce0afa 100644
> --- a/Documentation/devicetree/bindings/arm/ti/k3.txt
> +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt
> @@ -16,6 +16,9 @@ architecture it uses, using one of the following compatible values:
> - J721E
> compatible = "ti,j721e";
>
> +- J7200
> + compatible = "ti,j7200";
> +
> Boards
> ------
Lets convert the k3.txt to k3.yaml before we do anything more here.
Looking at the full series, I see that there are pending comments from
Grygorii as well which needs to be looked at. I have'nt seen a follow up
version since this version.
[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Hi Nishanth,
On 27/08/20 5:53 am, Nishanth Menon wrote:
> On 14:16-20200723, Lokesh Vutla wrote:
>> The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
>> It is targeted for automotive gateway, vehicle compute systems,
>> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
>> The SoC aims to meet the complex processing needs of modern embedded
>> products.
>>
>> Some highlights of this SoC are:
>> * Dual Cortex-A72s in a single cluster, two clusters of lockstep
>> capable dual Cortex-R5F MCUs and a Centralized Device Management and
>> Security Controller (DMSC).
>> * Configurable L3 Cache and IO-coherent architecture with high data
>> throughput capable distributed DMA architecture under NAVSS.
>> * Integrated Ethernet switch supporting up to a total of 4 external ports
>> in addition to legacy Ethernet switch of up to 2 ports.
>> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
>> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
>> I2C, eCAP/eQEP, eHRPWM among other peripherals.
>> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
>> management.
>>
>> See J7200 Technical Reference Manual (SPRUIU1, June 2020)
>> for further details: https://www.ti.com/lit/pdf/spruiu1
>>
>> Signed-off-by: Lokesh Vutla <[email protected]>
>> ---
>> Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt
>> index 333e7256126a..33419cce0afa 100644
>> --- a/Documentation/devicetree/bindings/arm/ti/k3.txt
>> +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt
>> @@ -16,6 +16,9 @@ architecture it uses, using one of the following compatible values:
>> - J721E
>> compatible = "ti,j721e";
>>
>> +- J7200
>> + compatible = "ti,j7200";
>> +
>> Boards
>> ------
>
> Lets convert the k3.txt to k3.yaml before we do anything more here.
> Looking at the full series, I see that there are pending comments from
okay, I can switch Patch 1 and 2.
> Grygorii as well which needs to be looked at. I have'nt seen a follow up
> version since this version.
Grygorii replied to the same asking to ignore his mail[0]
[0] https://patchwork.kernel.org/cover/11680441/
Thanks and regards,
Lokesh
>
> [1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
>