This series adds platform support for the V3s/V3/S3 MIPI CSI-2 and ISP units
as well the as A83T MIPI CSI-2 unit in the respective device-trees.
Overlays for the BananaPi M3 cameras are also provided as actual users of the
camera pipeline on A83T.
The corresponding drivers and dt bindings were merged a long time ago but this
series was never actually picked up. It seems more than ready to be merged!
Changes since v6:
- Rebased on top of the latest media tree, renamed dts to dtso for overlays.
Changes since v5:
- Added BananaPi M3 camera sensor support as device-tree overlays;
- Cleaned-up OV8865 regulator definitions;
- Always declared the internal links between CSI and MIPI CSI-2 on A83T
in device-tree.
Changes since v4:
- Removed mbus bindings patch: an equivalent change was merged;
- Added collected tags;
- Rebased on latest media tree.
Changes since v3:
- Reordered v3s mbus compatible in binding;
- Added collected tag;
- Removed rejected interconnects fix.
Changes since all-in-one v2:
- Corrected mbus index used for the interconnects;
- Used extended mbus binding and exported the DRAM clock for that;
- Reworked the description of the core openfirmware change to give
more insight about the situation.
Paul Kocialkowski (7):
clk: sunxi-ng: v3s: Export MBUS and DRAM clocks to the public header
ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect
ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
ARM: dts: sun8i: v3s: Add support for the ISP
ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
ARM: dts: sun8i-a83t: Add BananaPi M3 OV5640 camera overlay
ARM: dts: sun8i-a83t: Add BananaPi M3 OV8865 camera overlay
arch/arm/boot/dts/allwinner/Makefile | 2 +
.../sun8i-a83t-bananapi-m3-camera-ov5640.dtso | 117 +++++++++++++++++
.../sun8i-a83t-bananapi-m3-camera-ov8865.dtso | 109 ++++++++++++++++
arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 43 +++++++
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 121 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 4 -
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +-
7 files changed, 394 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov5640.dtso
create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
--
2.42.1
The V3s uses the mbus interconnect to provide DRAM access for a
number of blocks. The SoC can only map 2 GiB of DRAM, which is
reflected in the dma-ranges property.
Signed-off-by: Paul Kocialkowski <[email protected]>
Reviewed-by: Samuel Holland <[email protected]>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index 3b9a282c2746..506e98f4f69d 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -579,6 +579,21 @@ int_mii_phy: ethernet-phy@1 {
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-v3s-mbus";
+ reg = <0x01c62000 0x1000>,
+ <0x01c63000 0x1000>;
+ reg-names = "mbus", "dram";
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
+ #interconnect-cells = <1>;
+ };
+
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
--
2.42.1
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
The interconnects property is used to inherit the proper DMA offset.
Signed-off-by: Paul Kocialkowski <[email protected]>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 71 ++++++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index 506e98f4f69d..d57612023aa4 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -621,6 +621,77 @@ gic: interrupt-controller@1c81000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ csi0: camera@1cb0000 {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <&dphy>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint = <&csi0_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CSI>;
+ allwinner,direction = "rx";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
--
2.42.1
Add an overlay supporting the OV8865 from the BananaPi Camera v3
peripheral board. The board has two sensors (OV5640 and OV8865)
which cannot be supported in parallel as they share the same reset
pin and the kernel currently has no support for this case.
Signed-off-by: Paul Kocialkowski <[email protected]>
---
arch/arm/boot/dts/allwinner/Makefile | 1 +
.../sun8i-a83t-bananapi-m3-camera-ov8865.dtso | 109 ++++++++++++++++++
2 files changed, 110 insertions(+)
create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
index a0a9aa6595e4..980ac88634e3 100644
--- a/arch/arm/boot/dts/allwinner/Makefile
+++ b/arch/arm/boot/dts/allwinner/Makefile
@@ -278,6 +278,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-bananapi-m3.dtb \
sun8i-a83t-bananapi-m3-camera-ov5640.dtbo \
+ sun8i-a83t-bananapi-m3-camera-ov8865.dtbo \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-a83t-tbs-a711.dtb \
sun8i-h2-plus-bananapi-m2-zero.dtb \
diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
new file mode 100644
index 000000000000..0656ee8d4bfe
--- /dev/null
+++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/*
+ * Copyright 2022 Bootlin
+ * Author: Kévin L'hôpital <[email protected]>
+ * Author: Paul Kocialkowski <[email protected]>
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/sun8i-a83t-ccu.h>
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+ /*
+ * These regulators actually have DLDO4 tied to their EN pin, which is
+ * described as input supply here for lack of a better representation.
+ * Their actual supply is PS, which is always-on.
+ */
+
+ ov8865_avdd: ov8865-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "ov8865-avdd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <®_dldo4>;
+ };
+
+ ov8865_dovdd: ov8865-dovdd {
+ compatible = "regulator-fixed";
+ regulator-name = "ov8865-dovdd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <®_dldo4>;
+ };
+
+ ov8865_dvdd: ov8865-dvdd {
+ compatible = "regulator-fixed";
+ regulator-name = "ov8865-dvdd";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <®_dldo4>;
+ };
+};
+
+&ccu {
+ assigned-clocks = <&ccu CLK_CSI_MCLK>;
+ assigned-clock-parents = <&osc24M>;
+ assigned-clock-rates = <24000000>;
+};
+
+&csi {
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pe_pins>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov8865: camera@36 {
+ compatible = "ovti,ov8865";
+ reg = <0x36>;
+
+ clocks = <&ccu CLK_CSI_MCLK>;
+ assigned-clocks = <&ccu CLK_CSI_MCLK>;
+ assigned-clock-parents = <&osc24M>;
+ assigned-clock-rates = <24000000>;
+
+ avdd-supply = <&ov8865_avdd>;
+ dovdd-supply = <&ov8865_dovdd>;
+ dvdd-supply = <&ov8865_dvdd>;
+
+ powerdown-gpios = <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
+
+ port {
+ ov8865_out_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_in_ov8865>;
+ link-frequencies = /bits/ 64 <360000000>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+ };
+};
+
+&mipi_csi2 {
+ status = "okay";
+};
+
+&mipi_csi2_in {
+ mipi_csi2_in_ov8865: endpoint {
+ remote-endpoint = <&ov8865_out_mipi_csi2>;
+ data-lanes = <1 2 3 4>;
+ };
+};
+
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi_mclk_pin>;
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
--
2.42.1
Hi Paul!
Sorry for late reply.
On Wednesday, November 22, 2023 3:14:21 PM CET Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
> controller. The controller uses a separate D-PHY, which is the same
> that is otherwise used for MIPI DSI, but used in Rx mode.
>
> On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
> not have access to any parallel interface pins.
>
> Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
> support the MIPI CSI-2 interface.
>
> Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
> even when no sensor is connected. This will result in a probe failure
> for the controller as long as no sensor is connected but this is fine
> since no other interface is available.
>
> The interconnects property is used to inherit the proper DMA offset.
>
> Signed-off-by: Paul Kocialkowski <[email protected]>
> ---
> arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 71 ++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> index 506e98f4f69d..d57612023aa4 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
> @@ -621,6 +621,77 @@ gic: interrupt-controller@1c81000 {
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + csi0: camera@1cb0000 {
> + compatible = "allwinner,sun8i-v3s-csi";
> + reg = <0x01cb0000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI1_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> + interconnects = <&mbus 5>;
> + interconnect-names = "dma-mem";
As far as I can see, interconnects are not documented in
allwinner,sun6i-a31-csi.yaml. Please run make dtbs_check on this.
Best regards,
Jernej
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + csi0_in_mipi_csi2: endpoint {
> + remote-endpoint = <&mipi_csi2_out_csi0>;
> + };
> + };
> + };
> + };
> +
> + mipi_csi2: csi@1cb1000 {
> + compatible = "allwinner,sun8i-v3s-mipi-csi2",
> + "allwinner,sun6i-a31-mipi-csi2";
> + reg = <0x01cb1000 0x1000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI1_SCLK>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_CSI>;
> + status = "disabled";
> +
> + phys = <&dphy>;
> + phy-names = "dphy";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mipi_csi2_in: port@0 {
> + reg = <0>;
> + };
> +
> + mipi_csi2_out: port@1 {
> + reg = <1>;
> +
> + mipi_csi2_out_csi0: endpoint {
> + remote-endpoint = <&csi0_in_mipi_csi2>;
> + };
> + };
> + };
> + };
> +
> + dphy: d-phy@1cb2000 {
> + compatible = "allwinner,sun6i-a31-mipi-dphy";
> + reg = <0x01cb2000 0x1000>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_MIPI_CSI>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_CSI>;
> + allwinner,direction = "rx";
> + status = "disabled";
> + #phy-cells = <0>;
> + };
> +
> csi1: camera@1cb4000 {
> compatible = "allwinner,sun8i-v3s-csi";
> reg = <0x01cb4000 0x3000>;
>
Hi Paul,
same comments as for patch 6.
Best regards,
Jernej
On Wednesday, November 22, 2023 3:14:25 PM CET Paul Kocialkowski wrote:
> Add an overlay supporting the OV8865 from the BananaPi Camera v3
> peripheral board. The board has two sensors (OV5640 and OV8865)
> which cannot be supported in parallel as they share the same reset
> pin and the kernel currently has no support for this case.
>
> Signed-off-by: Paul Kocialkowski <[email protected]>
> ---
> arch/arm/boot/dts/allwinner/Makefile | 1 +
> .../sun8i-a83t-bananapi-m3-camera-ov8865.dtso | 109 ++++++++++++++++++
> 2 files changed, 110 insertions(+)
> create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
>
> diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
> index a0a9aa6595e4..980ac88634e3 100644
> --- a/arch/arm/boot/dts/allwinner/Makefile
> +++ b/arch/arm/boot/dts/allwinner/Makefile
> @@ -278,6 +278,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-bananapi-m3.dtb \
> sun8i-a83t-bananapi-m3-camera-ov5640.dtbo \
> + sun8i-a83t-bananapi-m3-camera-ov8865.dtbo \
> sun8i-a83t-cubietruck-plus.dtb \
> sun8i-a83t-tbs-a711.dtb \
> sun8i-h2-plus-bananapi-m2-zero.dtb \
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
> new file mode 100644
> index 000000000000..0656ee8d4bfe
> --- /dev/null
> +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dtso
> @@ -0,0 +1,109 @@
> +// SPDX-License-Identifier: GPL-2.0 OR X11
> +/*
> + * Copyright 2022 Bootlin
> + * Author: K?vin L'h?pital <[email protected]>
> + * Author: Paul Kocialkowski <[email protected]>
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/sun8i-a83t-ccu.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&{/} {
> + /*
> + * These regulators actually have DLDO4 tied to their EN pin, which is
> + * described as input supply here for lack of a better representation.
> + * Their actual supply is PS, which is always-on.
> + */
> +
> + ov8865_avdd: ov8865-avdd {
> + compatible = "regulator-fixed";
> + regulator-name = "ov8865-avdd";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + vin-supply = <®_dldo4>;
> + };
> +
> + ov8865_dovdd: ov8865-dovdd {
> + compatible = "regulator-fixed";
> + regulator-name = "ov8865-dovdd";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + vin-supply = <®_dldo4>;
> + };
> +
> + ov8865_dvdd: ov8865-dvdd {
> + compatible = "regulator-fixed";
> + regulator-name = "ov8865-dvdd";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + vin-supply = <®_dldo4>;
> + };
> +};
> +
> +&ccu {
> + assigned-clocks = <&ccu CLK_CSI_MCLK>;
> + assigned-clock-parents = <&osc24M>;
> + assigned-clock-rates = <24000000>;
> +};
> +
> +&csi {
> + status = "okay";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pe_pins>;
> + status = "okay";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ov8865: camera@36 {
> + compatible = "ovti,ov8865";
> + reg = <0x36>;
> +
> + clocks = <&ccu CLK_CSI_MCLK>;
> + assigned-clocks = <&ccu CLK_CSI_MCLK>;
> + assigned-clock-parents = <&osc24M>;
> + assigned-clock-rates = <24000000>;
> +
> + avdd-supply = <&ov8865_avdd>;
> + dovdd-supply = <&ov8865_dovdd>;
> + dvdd-supply = <&ov8865_dvdd>;
> +
> + powerdown-gpios = <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */
> + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
> +
> + port {
> + ov8865_out_mipi_csi2: endpoint {
> + remote-endpoint = <&mipi_csi2_in_ov8865>;
> + link-frequencies = /bits/ 64 <360000000>;
> + data-lanes = <1 2 3 4>;
> + };
> + };
> + };
> +};
> +
> +&mipi_csi2 {
> + status = "okay";
> +};
> +
> +&mipi_csi2_in {
> + mipi_csi2_in_ov8865: endpoint {
> + remote-endpoint = <&ov8865_out_mipi_csi2>;
> + data-lanes = <1 2 3 4>;
> + };
> +};
> +
> +&pio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&csi_mclk_pin>;
> +};
> +
> +®_dldo4 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> +};
>