The pinmux settings for RK3328 is incomplete, correct the pin bank
settings and recalced mux data according to RK3328 TRM[1].
There was a patch[2] in rockchip-linux kernel repo that cover part of
missing mux settings, unfortunatly it never got into upstream kernel
source.
The last patch fixes an issue in rockchip_pmx_set which is general for
all rockchip platforms that might cause unexpected pinmux to be set to
0.
[1]: https://opensource.rock-chips.com/images/9/97/Rockchip_RK3328TRM_V1.1-Part1-20170321.pdf
[2]: https://github.com/rockchip-linux/kernel/commit/d69af8ab6534bb28c1556076f08d2a5ab4935d95
v2:
- split commits for GPIO2-B pins and GPIO3-B pins each
- add a missing Fixes as suggested by Heiko
- add Reviewed-by to last 2 patches
Huang-Huang Bao (4):
pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins
pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins
pinctrl: rockchip: use dedicated pinctrl type for RK3328
pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set
drivers/pinctrl/pinctrl-rockchip.c | 68 ++++++++++++++++++++++++++----
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 60 insertions(+), 9 deletions(-)
base-commit: 2df0193e62cf887f373995fb8a91068562784adc
--
2.45.2
The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
specified in RK3328 TRM, however we can get hint from pad name and its
correspinding IOMUX setting for pins in interface descriptions. The
correspinding IOMIX settings for these pins can be found in the same
row next to occurrences of following pad names in RK3328 TRM.
GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
Add pinmux data to rk3328_mux_recalced_data as mux register offset for
these pins does not follow rockchip convention.
Signed-off-by: Huang-Huang Bao <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 78dcf4daccde..23531ea0d088 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -634,17 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
+ /* gpio2_b7_sel */
.num = 2,
.pin = 15,
.reg = 0x28,
.bit = 0,
.mask = 0x7
}, {
+ /* gpio2_c7_sel */
.num = 2,
.pin = 23,
.reg = 0x30,
.bit = 14,
.mask = 0x3
+ }, {
+ /* gpio3_b1_sel */
+ .num = 3,
+ .pin = 9,
+ .reg = 0x44,
+ .bit = 2,
+ .mask = 0x3
+ }, {
+ /* gpio3_b2_sel */
+ .num = 3,
+ .pin = 10,
+ .reg = 0x44,
+ .bit = 4,
+ .mask = 0x3
+ }, {
+ /* gpio3_b3_sel */
+ .num = 3,
+ .pin = 11,
+ .reg = 0x44,
+ .bit = 6,
+ .mask = 0x3
+ }, {
+ /* gpio3_b4_sel */
+ .num = 3,
+ .pin = 12,
+ .reg = 0x44,
+ .bit = 8,
+ .mask = 0x3
+ }, {
+ /* gpio3_b5_sel */
+ .num = 3,
+ .pin = 13,
+ .reg = 0x44,
+ .bit = 10,
+ .mask = 0x3
+ }, {
+ /* gpio3_b6_sel */
+ .num = 3,
+ .pin = 14,
+ .reg = 0x44,
+ .bit = 12,
+ .mask = 0x3
+ }, {
+ /* gpio3_b7_sel */
+ .num = 3,
+ .pin = 15,
+ .reg = 0x44,
+ .bit = 14,
+ .mask = 0x3
},
};
--
2.45.2
rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error,
add missing bank data retrieval in that code to avoid setting mux on
unexpected pins.
Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux")
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Huang-Huang Bao <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 24ee88863ce3..3f56991f5b89 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2751,8 +2751,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
if (ret) {
/* revert the already done pin settings */
- for (cnt--; cnt >= 0; cnt--)
+ for (cnt--; cnt >= 0; cnt--) {
+ bank = pin_to_bank(info, pins[cnt]);
rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
+ }
return ret;
}
--
2.45.2
The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
recalculated so it remain unchanged.
The pinmux bits for those pins are not explicitly specified in RK3328
TRM, however we can get hint from pad name and its correspinding IOMUX
setting for pins in interface descriptions. The correspinding IOMIX
settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to
occurrences of following pad names in RK3328 TRM.
GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5
GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5
GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5
GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5
GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5
GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5
GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5
This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
between GPIO2-B7 with GPIO2-B5.
Signed-off-by: Huang-Huang Bao <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3bedf36a0019..78dcf4daccde 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -634,12 +634,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
- .num = 2,
- .pin = 12,
- .reg = 0x24,
- .bit = 8,
- .mask = 0x3
- }, {
.num = 2,
.pin = 15,
.reg = 0x28,
@@ -3763,7 +3757,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
- IOMUX_WIDTH_3BIT,
+ 0,
IOMUX_WIDTH_3BIT,
0),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
--
2.45.2
rk3328_pin_ctrl uses type of RK3288 which has a hack in
rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6
at assume, the hack is not applicable to RK3328 as GPIO6 is not even
exist in it. So use a dedicated pinctrl type to skip this hack.
Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")
Reviewed-by: Heiko Stuebner <[email protected]>
Signed-off-by: Huang-Huang Bao <[email protected]>
---
drivers/pinctrl/pinctrl-rockchip.c | 5 ++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 23531ea0d088..24ee88863ce3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2478,6 +2478,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3188:
case RK3288:
case RK3308:
+ case RK3328:
case RK3368:
case RK3399:
case RK3568:
@@ -2536,6 +2537,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3188:
case RK3288:
case RK3308:
+ case RK3328:
case RK3368:
case RK3399:
case RK3568:
@@ -2798,6 +2800,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3188:
case RK3288:
case RK3308:
+ case RK3328:
case RK3368:
case RK3399:
case RK3568:
@@ -3822,7 +3825,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.label = "RK3328-GPIO",
- .type = RK3288,
+ .type = RK3328,
.grf_mux_offset = 0x0,
.iomux_recalced = rk3328_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index 4759f336941e..849266f8b191 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -193,6 +193,7 @@ enum rockchip_pinctrl_type {
RK3188,
RK3288,
RK3308,
+ RK3328,
RK3368,
RK3399,
RK3568,
--
2.45.2
Am Donnerstag, 6. Juni 2024, 14:57:52 CEST schrieb Huang-Huang Bao:
> The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width,
> correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is
> recalculated so it remain unchanged.
>
> The pinmux bits for those pins are not explicitly specified in RK3328
> TRM, however we can get hint from pad name and its correspinding IOMUX
> setting for pins in interface descriptions. The correspinding IOMIX
> settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to
> occurrences of following pad names in RK3328 TRM.
>
> GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5
> GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5
> GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5
> GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5
> GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5
> GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5
> GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5
>
> This fix has been tested on NanoPi R2S for fixing confliting pinmux bits
> between GPIO2-B7 with GPIO2-B5.
>
> Signed-off-by: Huang-Huang Bao <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")
The TRM also supports those findings, as gpio2-b4 actually is documented
there as 2-bit wide with the functions you found in the pad descriptions.
Am Donnerstag, 6. Juni 2024, 14:57:53 CEST schrieb Huang-Huang Bao:
> The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
> specified in RK3328 TRM, however we can get hint from pad name and its
> correspinding IOMUX setting for pins in interface descriptions. The
> correspinding IOMIX settings for these pins can be found in the same
> row next to occurrences of following pad names in RK3328 TRM.
>
> GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
> GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
> GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
> GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
> GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
> GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
>
> Add pinmux data to rk3328_mux_recalced_data as mux register offset for
> these pins does not follow rockchip convention.
>
> Signed-off-by: Huang-Huang Bao <[email protected]>
This matches the information that I found in my TRM, thanks to your
detailed explanation.
Though I of course can't say if the TRM is just wrong or the hardware
changed after the pads-description was written.
Did you test the usage of these pins on your board?
Heiko
> ---
> drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
> index 78dcf4daccde..23531ea0d088 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -634,17 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>
> static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
> {
> + /* gpio2_b7_sel */
> .num = 2,
> .pin = 15,
> .reg = 0x28,
> .bit = 0,
> .mask = 0x7
> }, {
> + /* gpio2_c7_sel */
> .num = 2,
> .pin = 23,
> .reg = 0x30,
> .bit = 14,
> .mask = 0x3
> + }, {
> + /* gpio3_b1_sel */
> + .num = 3,
> + .pin = 9,
> + .reg = 0x44,
> + .bit = 2,
> + .mask = 0x3
> + }, {
> + /* gpio3_b2_sel */
> + .num = 3,
> + .pin = 10,
> + .reg = 0x44,
> + .bit = 4,
> + .mask = 0x3
> + }, {
> + /* gpio3_b3_sel */
> + .num = 3,
> + .pin = 11,
> + .reg = 0x44,
> + .bit = 6,
> + .mask = 0x3
> + }, {
> + /* gpio3_b4_sel */
> + .num = 3,
> + .pin = 12,
> + .reg = 0x44,
> + .bit = 8,
> + .mask = 0x3
> + }, {
> + /* gpio3_b5_sel */
> + .num = 3,
> + .pin = 13,
> + .reg = 0x44,
> + .bit = 10,
> + .mask = 0x3
> + }, {
> + /* gpio3_b6_sel */
> + .num = 3,
> + .pin = 14,
> + .reg = 0x44,
> + .bit = 12,
> + .mask = 0x3
> + }, {
> + /* gpio3_b7_sel */
> + .num = 3,
> + .pin = 15,
> + .reg = 0x44,
> + .bit = 14,
> + .mask = 0x3
> },
> };
>
>
On 6/7/24 20:32, Heiko Stuebner wrote:
> Am Donnerstag, 6. Juni 2024, 14:57:53 CEST schrieb Huang-Huang Bao:
>> The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
>> specified in RK3328 TRM, however we can get hint from pad name and its
>> correspinding IOMUX setting for pins in interface descriptions. The
>> correspinding IOMIX settings for these pins can be found in the same
>> row next to occurrences of following pad names in RK3328 TRM.
>>
>> GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
>> GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
>> GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
>> GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
>> GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
>> GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
>>
>> Add pinmux data to rk3328_mux_recalced_data as mux register offset for
>> these pins does not follow rockchip convention.
>>
>> Signed-off-by: Huang-Huang Bao <[email protected]>
>
> This matches the information that I found in my TRM, thanks to your
> detailed explanation.
>
> Though I of course can't say if the TRM is just wrong or the hardware
> changed after the pads-description was written.
>
> Did you test the usage of these pins on your board?
>
My board(NanoPi R2S) is kinda integrated and does not have GPIO3 pins so
I can't test these pins directly.
From DTS for RK3328(arch/arm64/boot/dts/rockchip/rk3328*.dts*), there is
pinctrl/cif-0/dvp_d2d9_m0 referencing part of GPIO3-B1+ pins(GPIO3-B1 to
GPIO3-B4) that indeed matches "Table 15-1 TSP interface description"
which contains hint pad names. And this DTS node exists from
initial commit to add RK3328 dtsi
(52e02d377a72 "arm64: dts: rockchip: add core dtsi file for RK3328 SoCs").
Though this node is not actually used in any RK3328 DTSs. So I can't
test indirectly either.
Huang-Huang
>
> Heiko
>
>
>
>> ---
>> drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>>
>> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
>> index 78dcf4daccde..23531ea0d088 100644
>> --- a/drivers/pinctrl/pinctrl-rockchip.c
>> +++ b/drivers/pinctrl/pinctrl-rockchip.c
>> @@ -634,17 +634,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
>>
>> static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
>> {
>> + /* gpio2_b7_sel */
>> .num = 2,
>> .pin = 15,
>> .reg = 0x28,
>> .bit = 0,
>> .mask = 0x7
>> }, {
>> + /* gpio2_c7_sel */
>> .num = 2,
>> .pin = 23,
>> .reg = 0x30,
>> .bit = 14,
>> .mask = 0x3
>> + }, {
>> + /* gpio3_b1_sel */
>> + .num = 3,
>> + .pin = 9,
>> + .reg = 0x44,
>> + .bit = 2,
>> + .mask = 0x3
>> + }, {
>> + /* gpio3_b2_sel */
>> + .num = 3,
>> + .pin = 10,
>> + .reg = 0x44,
>> + .bit = 4,
>> + .mask = 0x3
>> + }, {
>> + /* gpio3_b3_sel */
>> + .num = 3,
>> + .pin = 11,
>> + .reg = 0x44,
>> + .bit = 6,
>> + .mask = 0x3
>> + }, {
>> + /* gpio3_b4_sel */
>> + .num = 3,
>> + .pin = 12,
>> + .reg = 0x44,
>> + .bit = 8,
>> + .mask = 0x3
>> + }, {
>> + /* gpio3_b5_sel */
>> + .num = 3,
>> + .pin = 13,
>> + .reg = 0x44,
>> + .bit = 10,
>> + .mask = 0x3
>> + }, {
>> + /* gpio3_b6_sel */
>> + .num = 3,
>> + .pin = 14,
>> + .reg = 0x44,
>> + .bit = 12,
>> + .mask = 0x3
>> + }, {
>> + /* gpio3_b7_sel */
>> + .num = 3,
>> + .pin = 15,
>> + .reg = 0x44,
>> + .bit = 14,
>> + .mask = 0x3
>> },
>> };
>>
>>
>
>
>
>
Am Donnerstag, 6. Juni 2024, 14:57:53 CEST schrieb Huang-Huang Bao:
> The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
> specified in RK3328 TRM, however we can get hint from pad name and its
> correspinding IOMUX setting for pins in interface descriptions. The
> correspinding IOMIX settings for these pins can be found in the same
> row next to occurrences of following pad names in RK3328 TRM.
>
> GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
> GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
> GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
> GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
> GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
> GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
>
> Add pinmux data to rk3328_mux_recalced_data as mux register offset for
> these pins does not follow rockchip convention.
>
> Signed-off-by: Huang-Huang Bao <[email protected]>
with my question about sourcing those information resolved.
Reviewed-by: Heiko Stuebner <[email protected]>
Am Freitag, 7. Juni 2024, 16:46:19 CEST schrieb Huang-Huang Bao:
>
> On 6/7/24 20:32, Heiko Stuebner wrote:
> > Am Donnerstag, 6. Juni 2024, 14:57:53 CEST schrieb Huang-Huang Bao:
> >> The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
> >> specified in RK3328 TRM, however we can get hint from pad name and its
> >> correspinding IOMUX setting for pins in interface descriptions. The
> >> correspinding IOMIX settings for these pins can be found in the same
> >> row next to occurrences of following pad names in RK3328 TRM.
> >>
> >> GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
> >> GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
> >> GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
> >> GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
> >> GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
> >> GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
> >>
> >> Add pinmux data to rk3328_mux_recalced_data as mux register offset for
> >> these pins does not follow rockchip convention.
> >>
> >> Signed-off-by: Huang-Huang Bao <[email protected]>
> >
> > This matches the information that I found in my TRM, thanks to your
> > detailed explanation.
> >
> > Though I of course can't say if the TRM is just wrong or the hardware
> > changed after the pads-description was written.
> >
> > Did you test the usage of these pins on your board?
> >
>
> My board(NanoPi R2S) is kinda integrated and does not have GPIO3 pins so
> I can't test these pins directly.
>
> From DTS for RK3328(arch/arm64/boot/dts/rockchip/rk3328*.dts*), there is
> pinctrl/cif-0/dvp_d2d9_m0 referencing part of GPIO3-B1+ pins(GPIO3-B1 to
> GPIO3-B4) that indeed matches "Table 15-1 TSP interface description"
> which contains hint pad names. And this DTS node exists from
> initial commit to add RK3328 dtsi
> (52e02d377a72 "arm64: dts: rockchip: add core dtsi file for RK3328 SoCs").
thanks for digging up this information, that makes sense and stuff looks
pretty much correct with everything combined.
Heiko
On 6/6/24 20:57, Huang-Huang Bao wrote:
> The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
> specified in RK3328 TRM, however we can get hint from pad name and its
> correspinding IOMUX setting for pins in interface descriptions. The
> correspinding IOMIX settings for these pins can be found in the same
> row next to occurrences of following pad names in RK3328 TRM.
>
> GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
> GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
> GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
> GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
> GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
> GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
>
> Add pinmux data to rk3328_mux_recalced_data as mux register offset for
> these pins does not follow rockchip convention.
>
> Signed-off-by: Huang-Huang Bao <[email protected]>
This is also
Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support")