2008-03-26 21:10:28

by Stefan Richter

Subject: memory-barriers.txt: cache coherency vs mmio

The subject section in memory-barriers.txt says:

"[...] MMIO accesses may, in effect, overtake accesses to cached memory
that were emitted earlier. A memory barrier isn't sufficient in such a
case, but rather the cache must be flushed between the cached memory
write and the MMIO access if the two are in any way dependent."

And the lowly driver programmer immediately asks:
How do I flush the cache?

In particular, do I have to do anyhing between

coherent_dma_buffer->datum = something;

writel(YOU_CAN_START_DMA_NOW, register);

Thanks,
--
Stefan Richter
-=====-==--- --== ==-=-
http://arcgraph.de/sr/

2008-03-27 05:13:37

by Robert Hancock

Subject: Re: memory-barriers.txt: cache coherency vs mmio

Stefan Richter wrote:
> The subject section in memory-barriers.txt says:
>
> "[...] MMIO accesses may, in effect, overtake accesses to cached memory
> that were emitted earlier. A memory barrier isn't sufficient in such a
> case, but rather the cache must be flushed between the cached memory
> write and the MMIO access if the two are in any way dependent."
>
> And the lowly driver programmer immediately asks:
> How do I flush the cache?
>
> In particular, do I have to do anyhing between
>
> coherent_dma_buffer->datum = something;
>
> writel(YOU_CAN_START_DMA_NOW, register);
>
> Thanks,

That part of the document seems kind of bogus to me. Or rather, if it's
true and there are architectures where ordering between normal memory
writes and MMIO is not ensured even with wmb(), that's the bogus part.
Driver authors should not have to deal with that sort of thing.