LinuxLists.cc - [Qualcomm PM8921 MFD v2 0/6] pmic 8921 core and subdevices

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Subject: [Qualcomm PM8921 MFD v2 5/6] MAINTAINERS: Add patterns for pmic 8921 files to MSM subsystem

From: Abhijeet Dharmapurikar <[email protected]>

Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
MAINTAINERS | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 696cb18..8d8c87b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -905,6 +905,9 @@ F: drivers/mmc/host/msm_sdcc.h
F: drivers/tty/serial/msm_serial.h
F: drivers/tty/serial/msm_serial.c
F: drivers/platform/msm/
+F: drivers/*/pm8???-*
+F: include/linux/mfd/pm8???.h
+F: include/linux/mfd/pm8xxx/
T: git git://codeaurora.org/quic/kernel/davidb/linux-msm.git
S: Maintained

--
1.7.1

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-08 06:11:37

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Subject: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

From: Abhijeet Dharmapurikar <[email protected]>

Add support for the irq controller in Qualcomm 8xxx pmic. The 8xxx
interrupt controller provides control for gpio and mpp configured as
interrupts in addition to other subdevice interrupts. The interrupt
controller also provides a way to read the real time status of an
interrupt. This real time status is the only way one can get the
input values of gpio and mpp lines.

Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
drivers/mfd/Kconfig | 10 +
drivers/mfd/Makefile | 1 +
drivers/mfd/pm8921-core.c | 85 ++++++
drivers/mfd/pm8xxx-irq.c | 551 +++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pm8921.h | 4 +
include/linux/mfd/pm8xxx/core.h | 9 +
include/linux/mfd/pm8xxx/irq.h | 81 ++++++
7 files changed, 741 insertions(+), 0 deletions(-)
create mode 100644 drivers/mfd/pm8xxx-irq.c
create mode 100644 include/linux/mfd/pm8xxx/irq.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 46f0d2f..318e42a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -642,6 +642,16 @@ config MFD_PM8921_CORE
Say M here if you want to include support for PM8921 chip as a module.
This will build a module called "pm8921-core.ko".

+config MFD_PM8XXX_IRQ
+ bool "Support for Qualcomm PM8xxx IRQ features"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This is the IRQ driver for Qualcomm PM 8xxx PMIC chips.
+
+ This is required to use certain other PM 8xxx features, such as GPIO
+ and MPP.
+
endif # MFD_SUPPORT

menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index ec158da..5fc9315 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -84,3 +84,4 @@ obj-$(CONFIG_MFD_VX855) += vx855.o
obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
+obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index 06c39e1..d554551 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -15,6 +15,7 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <linux/err.h>
#include <linux/msm_ssbi.h>
#include <linux/mfd/core.h>
#include <linux/mfd/pm8921.h>
@@ -25,6 +26,7 @@

struct pm8921 {
struct device *dev;
+ void *irq_data;
};

static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
@@ -61,11 +63,74 @@ static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
return msm_ssbi_write(pmic->dev->parent, addr, buf, cnt);
}

+static int pm8921_read_irq_stat(const struct device *dev, int irq)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return pm8xxx_get_irq_stat(pmic->irq_data, irq);
+}
+
static struct pm8xxx_drvdata pm8921_drvdata = {
.pmic_readb = pm8921_readb,
.pmic_writeb = pm8921_writeb,
.pmic_read_buf = pm8921_read_buf,
.pmic_write_buf = pm8921_write_buf,
+ .pmic_read_irq_stat = pm8921_read_irq_stat,
+};
+
+static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
+ *pdata,
+ struct pm8921 *pmic,
+ u32 rev)
+{
+ int ret = 0;
+ int irq_base = 0;
+ void *irq_data;
+
+ if (pdata->irq_pdata) {
+ pdata->irq_pdata->irq_cdata.nirqs = PM8921_NR_IRQS;
+ pdata->irq_pdata->irq_cdata.rev = rev;
+ irq_base = pdata->irq_pdata->irq_base;
+ irq_data = pm8xxx_irq_init(pmic->dev, pdata->irq_pdata);
+
+ if (IS_ERR(irq_data)) {
+ pr_err("Failed to init interrupts ret=%ld\n",
+ PTR_ERR(irq_data));
+ ret = PTR_ERR(irq_data);
+ goto bail;
+ } else
+ pmic->irq_data = irq_data;
+ }
+
+bail:
+ return ret;
+}
+
+#ifdef CONFIG_PM
+static int pm8921_suspend(const struct device *dev)
+{
+ const struct pm8xxx_drvdata *drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = drvdata->pm_chip_data;
+
+ pm8xxx_suspend_irq(pmic->irq_data);
+}
+
+static int pm8921_resume(const struct device *dev)
+{
+ const struct pm8xxx_drvdata *drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = drvdata->pm_chip_data;
+
+ pm8xxx_resume_irq(pmic->irq_data);
+}
+#else
+#define pm8921_suspend NULL
+#define pm8921_resume NULL
+#endif
+
+static const struct dev_pm_ops pm8921_pm = {
+ .suspend = pm8921_suspend,
+ .resume = pm8921_resume,
};

static int __devinit pm8921_probe(struct platform_device *pdev)
@@ -74,6 +139,7 @@ static int __devinit pm8921_probe(struct platform_device *pdev)
struct pm8921 *pmic;
int rc;
u8 val;
+ u32 rev;

if (!pdata) {
pr_err("missing platform data\n");
@@ -93,6 +159,7 @@ static int __devinit pm8921_probe(struct platform_device *pdev)
goto err_read_rev;
}
pr_info("PMIC revision 1: %02X\n", val);
+ rev = val;

/* Read PMIC chip revision 2 */
rc = msm_ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
@@ -102,13 +169,26 @@ static int __devinit pm8921_probe(struct platform_device *pdev)
goto err_read_rev;
}
pr_info("PMIC revision 2: %02X\n", val);
+ rev |= val << BITS_PER_BYTE;

pmic->dev = &pdev->dev;
pm8921_drvdata.pm_chip_data = pmic;
platform_set_drvdata(pdev, &pm8921_drvdata);

+ rc = pm8921_add_subdevices(pdata, pmic, rev);
+ if (rc) {
+ pr_err("Cannot add subdevices rc=%d\n", rc);
+ goto err;
+ }
+
+ /* gpio might not work if no irq device is found */
+ WARN_ON(pmic->irq_data == NULL);
+
return 0;

+err:
+ mfd_remove_devices(pmic->dev);
+ platform_set_drvdata(pdev, NULL);
err_read_rev:
kfree(pmic);
return rc;
@@ -124,6 +204,10 @@ static int __devexit pm8921_remove(struct platform_device *pdev)
pmic = drvdata->pm_chip_data;
if (pmic)
mfd_remove_devices(pmic->dev);
+ if (pmic->irq_data) {
+ pm8xxx_irq_exit(pmic->irq_data);
+ pmic->irq_data = NULL;
+ }
platform_set_drvdata(pdev, NULL);
kfree(pmic);

@@ -136,6 +220,7 @@ static struct platform_driver pm8921_driver = {
.driver = {
.name = "pm8921-core",
.owner = THIS_MODULE,
+ .pm = &pm8921_pm,
},
};

diff --git a/drivers/mfd/pm8xxx-irq.c b/drivers/mfd/pm8xxx-irq.c
new file mode 100644
index 0000000..0bf15d4
--- /dev/null
+++ b/drivers/mfd/pm8xxx-irq.c
@@ -0,0 +1,551 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/irq.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+
+/* PMIC8xxx IRQ */
+
+#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
+
+#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
+#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
+#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
+#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
+#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
+#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
+#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
+#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
+#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
+
+#define PM_IRQF_LVL_SEL 0x01 /* level select */
+#define PM_IRQF_MASK_FE 0x02 /* mask falling edge */
+#define PM_IRQF_MASK_RE 0x04 /* mask rising edge */
+#define PM_IRQF_CLR 0x08 /* clear interrupt */
+#define PM_IRQF_BITS_MASK 0x70
+#define PM_IRQF_BITS_SHIFT 4
+#define PM_IRQF_WRITE 0x80
+
+#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
+ PM_IRQF_MASK_RE)
+#define PM_IRQF_W_C_M (PM_IRQF_WRITE | \
+ PM_IRQF_CLR | \
+ PM_IRQF_MASK_ALL)
+
+struct pm_irq_chip {
+ struct list_head link;
+ struct device *dev;
+ spinlock_t pm_irq_lock;
+ u8 *irqs_allowed;
+ u16 *irqs_to_handle;
+ u8 *config;
+ unsigned long *wake_enable;
+ unsigned int devirq;
+ unsigned int count_wakeable;
+ unsigned int irq_base;
+ unsigned int num_irqs;
+ unsigned int num_blocks;
+ unsigned int num_masters;
+};
+
+static LIST_HEAD(pm_irq_chips);
+
+/* Helper Functions */
+static DEFINE_RATELIMIT_STATE(pm8xxx_irq_ratelimit, 60 * HZ, 10);
+
+static inline int pm8xxx_can_print(void)
+{
+ return __ratelimit(&pm8xxx_irq_ratelimit);
+}
+
+static int
+pm8xxx_read_root_irq(const struct pm_irq_chip *chip, u8 *rp)
+{
+ return pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_ROOT, rp);
+}
+
+static int
+pm8xxx_read_master_irq(const struct pm_irq_chip *chip, u8 m, u8 *bp)
+{
+ return pm8xxx_readb(chip->dev,
+ SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
+}
+
+static int
+pm8xxx_read_block_irq(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
+{
+ int rc;
+
+ rc = pm8xxx_writeb(chip->dev,
+ SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
+ if (rc) {
+ pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
+ goto bail_out;
+ }
+
+ rc = pm8xxx_readb(chip->dev,
+ SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
+ if (rc)
+ pr_err("Failed Reading Status rc=%d\n", rc);
+bail_out:
+ return rc;
+}
+
+static int
+pm8xxx_config_irq(const struct pm_irq_chip *chip, u8 bp, u8 cp)
+{
+ int rc;
+
+ rc = pm8xxx_writeb(chip->dev,
+ SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
+ if (rc) {
+ pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
+ goto bail_out;
+ }
+
+ rc = pm8xxx_writeb(chip->dev,
+ SSBI_REG_ADDR_IRQ_CONFIG, cp);
+ if (rc)
+ pr_err("Failed Configuring IRQ rc=%d\n", rc);
+bail_out:
+ return rc;
+}
+
+static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip,
+ int block, int *handled)
+{
+ int ret = 0;
+ u8 bits;
+ int pmirq, irq, k;
+
+ spin_lock(&chip->pm_irq_lock);
+ ret = pm8xxx_read_block_irq(chip, block, &bits);
+ if (ret) {
+ if (pm8xxx_can_print())
+ pr_err("Failed reading %d block ret=%d",
+ block, ret);
+ goto out;
+ }
+ if (!bits) {
+ if (pm8xxx_can_print())
+ pr_err("block bit set in master but no irqs: %d",
+ block);
+ goto out;
+ }
+
+ /* Check IRQ bits */
+ for (k = 0; k < 8; k++) {
+ if (bits & (1 << k)) {
+ pmirq = block * 8 + k;
+ irq = pmirq + chip->irq_base;
+ chip->irqs_to_handle[*handled] = irq;
+ (*handled)++;
+ }
+ }
+out:
+ spin_unlock(&chip->pm_irq_lock);
+ return ret;
+}
+
+static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip,
+ int master, int *handled)
+{
+ int ret = 0;
+ u8 blockbits;
+ int block_number, j;
+
+ ret = pm8xxx_read_master_irq(chip, master, &blockbits);
+ if (ret) {
+ pr_err("Failed to read master %d ret=%d\n", master, ret);
+ return ret;
+ }
+ if (!blockbits) {
+ if (pm8xxx_can_print())
+ pr_err("master bit set in root but no blocks: %d",
+ master);
+ return 0;
+ }
+
+ for (j = 0; j < 8; j++)
+ if (blockbits & (1 << j)) {
+ block_number = master * 8 + j; /* block # */
+ ret |= pm8xxx_irq_block_handler(chip, block_number,
+ handled);
+ }
+ return ret;
+}
+
+static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+ struct pm_irq_chip *chip = get_irq_data(irq);
+ int i, ret;
+ u8 root;
+ int masters = 0, handled = 0;
+
+ ret = pm8xxx_read_root_irq(chip, &root);
+ if (ret) {
+ pr_err("Can't read root status ret=%d\n", ret);
+ return;
+ }
+
+ /* on pm8xxx series masters start from bit 1 of the root */
+ masters = root >> 1;
+
+ /* Read allowed masters for blocks. */
+ for (i = 0; i < chip->num_masters; i++)
+ if (masters & (1 << i))
+ pm8xxx_irq_master_handler(chip, i, &handled);
+
+ for (i = 0; i < handled; i++)
+ generic_handle_irq(chip->irqs_to_handle[i]);
+
+ desc->chip->ack(irq);
+}
+
+static void pm8xxx_irq_ack(struct irq_data *d)
+{
+ const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+ unsigned int pmirq = d->irq - chip->irq_base;
+ u8 block, config;
+
+ block = pmirq / 8;
+
+ config = PM_IRQF_WRITE | chip->config[pmirq] | PM_IRQF_CLR;
+ /* Keep the mask */
+ if (!(chip->irqs_allowed[block] & (1 << (pmirq % 8))))
+ config |= PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
+ pm8xxx_config_irq(chip, block, config);
+}
+
+static void pm8xxx_irq_mask(struct irq_data *d)
+{
+ const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+ unsigned int pmirq = d->irq - chip->irq_base;
+ int master, irq_bit;
+ u8 block, config;
+
+ block = pmirq / 8;
+ master = block / 8;
+ irq_bit = pmirq % 8;
+
+ chip->irqs_allowed[block] &= ~(1 << irq_bit);
+
+ config = PM_IRQF_WRITE | chip->config[pmirq] |
+ PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
+ pm8xxx_config_irq(chip, block, config);
+}
+
+static void pm8xxx_irq_unmask(struct irq_data *d)
+{
+ const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+ unsigned int pmirq = d->irq - chip->irq_base;
+ int master, irq_bit;
+ u8 block, config, old_irqs_allowed;
+
+ block = pmirq / 8;
+ master = block / 8;
+ irq_bit = pmirq % 8;
+
+ old_irqs_allowed = chip->irqs_allowed[block];
+ chip->irqs_allowed[block] |= 1 << irq_bit;
+
+ config = PM_IRQF_WRITE | chip->config[pmirq];
+ pm8xxx_config_irq(chip, block, config);
+}
+
+static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+ const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+ unsigned int pmirq = d->irq - chip->irq_base;
+ int master, irq_bit;
+ u8 block, config;
+
+ block = pmirq / 8;
+ master = block / 8;
+ irq_bit = pmirq % 8;
+
+ chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT) |
+ PM_IRQF_MASK_RE | PM_IRQF_MASK_FE;
+ if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
+ if (flow_type & IRQF_TRIGGER_RISING)
+ chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
+ if (flow_type & IRQF_TRIGGER_FALLING)
+ chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
+ } else {
+ chip->config[pmirq] |= PM_IRQF_LVL_SEL;
+
+ if (flow_type & IRQF_TRIGGER_HIGH)
+ chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
+ else
+ chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
+ }
+
+ config = PM_IRQF_WRITE
+ | chip->config[pmirq] | PM_IRQF_CLR;
+ return pm8xxx_config_irq(chip, block, config);
+}
+
+static int pm8xxx_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
+ unsigned int pmirq = d->irq - chip->irq_base;
+
+ if (on) {
+ set_bit(pmirq, chip->wake_enable);
+ chip->count_wakeable++;
+ } else {
+ clear_bit(pmirq, chip->wake_enable);
+ chip->count_wakeable--;
+ }
+
+ return 0;
+}
+
+static struct irq_chip pm8xxx_irq_chip = {
+ .name = "pm8xxx",
+ .irq_ack = pm8xxx_irq_ack,
+ .irq_mask = pm8xxx_irq_mask,
+ .irq_unmask = pm8xxx_irq_unmask,
+ .irq_set_type = pm8xxx_irq_set_type,
+ .irq_set_wake = pm8xxx_irq_set_wake,
+};
+
+int pm8xxx_get_irq_stat(void *data, int irq)
+{
+ struct pm_irq_chip *chip = data;
+ int pmirq;
+ int rc;
+ u8 block, bits, bit;
+ unsigned long flags;
+
+ if (chip == NULL || irq < chip->irq_base ||
+ irq >= chip->irq_base + chip->num_irqs)
+ return -EINVAL;
+
+ pmirq = irq - chip->irq_base;
+
+ block = pmirq / 8;
+ bit = pmirq % 8;
+
+ spin_lock_irqsave(&chip->pm_irq_lock, flags);
+
+ rc = pm8xxx_writeb(chip->dev,
+ SSBI_REG_ADDR_IRQ_BLK_SEL, block);
+ if (rc) {
+ pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
+ irq, pmirq, block, rc);
+ goto bail_out;
+ }
+
+ rc = pm8xxx_readb(chip->dev,
+ SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
+ if (rc) {
+ pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
+ irq, pmirq, block, rc);
+ goto bail_out;
+ }
+
+ rc = (bits & (1 << bit)) ? 1 : 0;
+
+bail_out:
+ spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_get_irq_stat);
+
+#ifdef CONFIG_PM
+int pm8xxx_suspend_irq(const void *data)
+{
+ const struct pm_irq_chip *chip = data;
+ int pmirq;
+
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
+ if (!((chip->config[i] & PM_IRQF_MASK_ALL)
+ == PM_IRQF_MASK_ALL)) {
+ irq = i + chip->irq_base;
+ pm8xxx_irq_mask(get_irq_data(irq));
+ }
+ }
+ }
+
+ if (!chip->count_wakeable)
+ disable_irq(chip->dev->irq);
+
+ return 0;
+}
+
+void pm8xxx_show_resume_irq(void)
+{
+ struct pm_irq_chip *chip;
+ u8 block, bits;
+ int pmirq;
+
+ list_for_each_entry(chip, &pm_irq_chips, link) {
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ if (test_bit(pmirq, chip->wake_enable)) {
+ block = pmirq / 8;
+ if (!pm8xxx_read_block_irq(chip,
+ &block, &bits)) {
+ if (bits & (1 << (pmirq & 0x7)))
+ pr_warning("%d triggered\n",
+ pmirq + chip->pdata.irq_base);
+ }
+ }
+ }
+ }
+}
+
+int pm8xxx_resume_irq(const void *data)
+{
+ const struct pm_irq_chip *chip = data;
+ int pmirq;
+
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
+ if (!((chip->config[i] & PM_IRQF_MASK_ALL)
+ == PM_IRQF_MASK_ALL)) {
+ irq = i + chip->irq_base;
+ pm8xxx_irq_unmask(get_irq_data(irq));
+ }
+ }
+ }
+
+ if (!chip->count_wakeable)
+ enable_irq(chip->dev->irq);
+
+ return 0;
+}
+#else
+#define pm8xxx_suspend NULL
+#define pm8xxx_resume NULL
+#endif
+
+void * __devinit pm8xxx_irq_init(struct device *dev,
+ const struct pm8xxx_irq_platform_data *pdata)
+{
+ struct pm_irq_chip *chip;
+ int devirq;
+ int rc;
+ unsigned int pmirq;
+
+ if (!pdata) {
+ pr_err("No platform data\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ devirq = pdata->devirq;
+ if (devirq < 0) {
+ pr_err("missing devirq\n");
+ rc = devirq;
+ goto out;
+ }
+
+ chip = kzalloc(sizeof(struct pm_irq_chip), GFP_KERNEL);
+ if (!chip) {
+ pr_err("Cannot alloc pm_irq_chip struct\n");
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ chip->dev = dev;
+ chip->devirq = devirq;
+ chip->irq_base = pdata->irq_base;
+ chip->num_irqs = pdata->irq_cdata.nirqs;
+ chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
+ chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
+ spin_lock_init(&chip->pm_irq_lock);
+
+ chip->irqs_allowed = kzalloc(sizeof(u8) * chip->num_blocks, GFP_KERNEL);
+ if (!chip->irqs_allowed) {
+ pr_err("Cannot alloc irqs_allowed array\n");
+ rc = -ENOMEM;
+ goto free_pm_irq_chip;
+ }
+
+ chip->irqs_to_handle = kzalloc(sizeof(u16) * chip->num_irqs,
+ GFP_KERNEL);
+ if (!chip->irqs_to_handle) {
+ pr_err("Cannot alloc irqs_to_handle array\n");
+ rc = -ENOMEM;
+ goto free_irqs_allowed;
+ }
+ chip->config = kzalloc(sizeof(u8) * chip->num_irqs, GFP_KERNEL);
+ if (!chip->config) {
+ pr_err("Cannot alloc config array\n");
+ rc = -ENOMEM;
+ goto free_irqs_to_handle;
+ }
+ chip->wake_enable = kzalloc(sizeof(unsigned long)
+ * DIV_ROUND_UP(chip->num_irqs, BITS_PER_LONG),
+ GFP_KERNEL);
+ if (!chip->wake_enable) {
+ pr_err("Cannot alloc wake_enable array\n");
+ rc = -ENOMEM;
+ goto free_config;
+ }
+
+ list_add(&chip->link, &pm_irq_chips);
+
+ for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
+ set_irq_chip(chip->irq_base + pmirq, &pm8xxx_irq_chip);
+ set_irq_chip_data(chip->irq_base + pmirq, chip);
+ set_irq_handler(chip->irq_base + pmirq, handle_level_irq);
+#ifdef CONFIG_ARM
+ set_irq_flags(chip->irq_base + pmirq, IRQF_VALID);
+#else
+ set_irq_noprobe(chip->irq_base + pmirq);
+#endif
+ }
+
+ set_irq_type(devirq, pdata->irq_trigger_flag);
+ set_irq_data(devirq, chip);
+ set_irq_chained_handler(devirq, pm8xxx_irq_handler);
+ set_irq_wake(devirq, 1);
+
+ return chip;
+
+free_config:
+ kfree(chip->config);
+free_irqs_to_handle:
+ kfree(chip->irqs_to_handle);
+free_irqs_allowed:
+ kfree(chip->irqs_allowed);
+free_pm_irq_chip:
+ kfree(chip);
+out:
+ return ERR_PTR(rc);
+}
+
+int __devexit pm8xxx_irq_exit(void *data)
+{
+ struct pm_irq_chip *chip = data;
+
+ list_del(&chip->link);
+ set_irq_chained_handler(chip->devirq, NULL);
+ kfree(chip->wake_enable);
+ kfree(chip->config);
+ kfree(chip->irqs_to_handle);
+ kfree(chip->irqs_allowed);
+ kfree(chip);
+ return 0;
+}
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
index 6bed710..d2806ff 100644
--- a/include/linux/mfd/pm8921.h
+++ b/include/linux/mfd/pm8921.h
@@ -18,9 +18,13 @@
#define __MFD_PM8921_H

#include <linux/device.h>
+#include <linux/mfd/pm8xxx/irq.h>
+
+#define PM8921_NR_IRQS 256

struct pm8921_platform_data {
int irq_base;
+ struct pm8xxx_irq_platform_data *irq_pdata;
};

#endif
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
index 61f1c01..e5aeecf 100644
--- a/include/linux/mfd/pm8xxx/core.h
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -26,6 +26,7 @@ struct pm8xxx_drvdata {
int n);
int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
int n);
+ int (*pmic_read_irq_stat) (const struct device *dev, int irq);
void *pm_chip_data;
};

@@ -63,4 +64,12 @@ static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
return dd->pmic_write_buf(dev, addr, buf, n);
}

+static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_read_irq_stat(dev, irq);
+}
+
#endif
diff --git a/include/linux/mfd/pm8xxx/irq.h b/include/linux/mfd/pm8xxx/irq.h
new file mode 100644
index 0000000..298d4ff
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/irq.h
@@ -0,0 +1,81 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC irq 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_IRQ_H
+#define __MFD_PM8XXX_IRQ_H
+
+#include <linux/errno.h>
+#include <linux/err.h>
+
+struct pm8xxx_irq_core_data {
+ u32 rev;
+ int nirqs;
+};
+
+struct pm8xxx_irq_platform_data {
+ int irq_base;
+ struct pm8xxx_irq_core_data irq_cdata;
+ int devirq;
+ int irq_trigger_flag;
+};
+
+#ifdef CONFIG_MFD_PM8XXX_IRQ
+/**
+ * pm8xxx_get_irq_stat - get the status of the irq line
+ * @dev: the interrupt device
+ * @irq: the irq number
+ *
+ * The pm8xxx gpio and mpp rely on the interrupt block to read
+ * the values on their pins. This function is to facilitate reading
+ * the status of a gpio or an mpp line. The caller has to convert the
+ * gpio number to irq number.
+ *
+ * RETURNS:
+ * an int indicating the value read on that line
+ */
+int pm8xxx_get_irq_stat(void *data, int irq);
+void pm8xxx_show_resume_irq(void);
+void * __devinit pm8xxx_irq_init(struct device *dev,
+ const struct pm8xxx_irq_platform_data *pdata);
+int __devexit pm8xxx_irq_exit(void *data);
+
+void pm8xxx_suspend_irq(const void *data);
+void pm8xxx_resume_irq(const void *data);
+#else
+static inline int pm8xxx_get_irq_stat(void *data, int irq)
+{
+ return -ENXIO;
+}
+static inline void pm8xxx_show_resume_irq(void)
+{
+}
+static inline void * __devinit pm8xxx_irq_init(const struct device *dev,
+ const struct pm8xxx_irq_platform_data *pdata);
+{
+ return ERR_PTR(-ENXIO);
+}
+static inline int __devexit pm8xxx_irq_exit(void *data);
+{
+ return ERR_PTR(-ENXIO);
+}
+static inline void pm8xxx_suspend_irq(const void *data)
+{
+}
+static inline void pm8xxx_resume_irq(const void *data)
+{
+}
+#endif /* CONFIG_MFD_PM8XXX_IRQ */
+#endif /* __MFD_PM8XXX_IRQ_H */
--
1.7.1

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-08 06:11:34

[permalink] [raw]

Subject: [Qualcomm PM8921 MFD v2 3/6] gpio: pm8xxx-gpio: Add pm8xxx gpio driver

From: Abhijeet Dharmapurikar <[email protected]>

Add support for GPIO on Qualcomm PM8xxx PMIC chips.

Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
drivers/gpio/Kconfig | 10 +
drivers/gpio/Makefile | 1 +
drivers/gpio/pm8xxx-gpio.c | 451 +++++++++++++++++++++++++++++++++++++++
drivers/mfd/pm8921-core.c | 34 +++
include/linux/mfd/pm8921.h | 11 +
include/linux/mfd/pm8xxx/gpio.h | 132 ++++++++++++
6 files changed, 639 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/pm8xxx-gpio.c
create mode 100644 include/linux/mfd/pm8xxx/gpio.h

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 664660e..c5e6f51 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -411,4 +411,14 @@ config GPIO_JANZ_TTL
This driver provides support for driving the pins in output
mode only. Input mode is not supported.

+comment "SSBI GPIO expanders:"
+
+config GPIO_PM8XXX
+ tristate "Qualcomm PM8xxx GPIO support"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This option enables support for on-chip GPIO found on Qualcomm PM8xxx
+ PMICs.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3351cf8..10efe6c 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -42,3 +42,4 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
obj-$(CONFIG_GPIO_SX150X) += sx150x.o
obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o
obj-$(CONFIG_GPIO_ML_IOH) += ml_ioh_gpio.o
+obj-$(CONFIG_GPIO_PM8XXX) += pm8xxx-gpio.o
diff --git a/drivers/gpio/pm8xxx-gpio.c b/drivers/gpio/pm8xxx-gpio.c
new file mode 100644
index 0000000..d9c246b
--- /dev/null
+++ b/drivers/gpio/pm8xxx-gpio.c
@@ -0,0 +1,451 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC8XXX GPIO driver
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/gpio.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+
+/* GPIO registers */
+#define SSBI_REG_ADDR_GPIO_BASE 0x150
+#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
+
+/* GPIO */
+#define PM_GPIO_BANK_MASK 0x70
+#define PM_GPIO_BANK_SHIFT 4
+#define PM_GPIO_WRITE 0x80
+
+/* Bank 0 */
+#define PM_GPIO_VIN_MASK 0x0E
+#define PM_GPIO_VIN_SHIFT 1
+#define PM_GPIO_MODE_ENABLE 0x01
+
+/* Bank 1 */
+#define PM_GPIO_MODE_MASK 0x0C
+#define PM_GPIO_MODE_SHIFT 2
+#define PM_GPIO_OUT_BUFFER 0x02
+#define PM_GPIO_OUT_INVERT 0x01
+
+#define PM_GPIO_MODE_OFF 3
+#define PM_GPIO_MODE_OUTPUT 2
+#define PM_GPIO_MODE_INPUT 0
+#define PM_GPIO_MODE_BOTH 1
+
+/* Bank 2 */
+#define PM_GPIO_PULL_MASK 0x0E
+#define PM_GPIO_PULL_SHIFT 1
+
+/* Bank 3 */
+#define PM_GPIO_OUT_STRENGTH_MASK 0x0C
+#define PM_GPIO_OUT_STRENGTH_SHIFT 2
+
+/* Bank 4 */
+#define PM_GPIO_FUNC_MASK 0x0E
+#define PM_GPIO_FUNC_SHIFT 1
+
+/* Bank 5 */
+#define PM_GPIO_NON_INT_POL_INV 0x08
+#define PM_GPIO_BANKS 6
+
+struct pm_gpio_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+ struct mutex pm_lock;
+ u8 *bank1;
+ int irq_base;
+};
+
+static LIST_HEAD(pm_gpio_chips);
+
+static int pm_gpio_get(struct pm_gpio_chip *pm_gpio_chip, unsigned gpio)
+{
+ int mode;
+
+ if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ /* Get gpio value from config bank 1 if output gpio.
+ Get gpio value from IRQ RT status register for all other gpio modes.
+ */
+ mode = (pm_gpio_chip->bank1[gpio] & PM_GPIO_MODE_MASK) >>
+ PM_GPIO_MODE_SHIFT;
+ if (mode == PM_GPIO_MODE_OUTPUT)
+ return pm_gpio_chip->bank1[gpio] & PM_GPIO_OUT_INVERT;
+ else
+ return pm8xxx_read_irq_stat(pm_gpio_chip->gpio_chip.dev->parent,
+ pm_gpio_chip->irq_base + gpio);
+}
+
+static int pm_gpio_set(struct pm_gpio_chip *pm_gpio_chip,
+ unsigned gpio, int value)
+{
+ int rc;
+ u8 bank1;
+
+ if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ mutex_lock(&pm_gpio_chip->pm_lock);
+ bank1 = PM_GPIO_WRITE
+ | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_OUT_INVERT);
+
+ if (value)
+ bank1 |= PM_GPIO_OUT_INVERT;
+
+ pm_gpio_chip->bank1[gpio] = bank1;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(gpio), bank1);
+ mutex_unlock(&pm_gpio_chip->pm_lock);
+
+ if (rc)
+ pr_err("FAIL pm8xxx_writeb(): rc=%d. "
+ "(gpio=%d, value=%d)\n",
+ rc, gpio, value);
+
+ return rc;
+}
+
+static int dir_map[] = {
+ PM_GPIO_MODE_OFF,
+ PM_GPIO_MODE_OUTPUT,
+ PM_GPIO_MODE_INPUT,
+ PM_GPIO_MODE_BOTH,
+};
+
+static int pm_gpio_set_direction(struct pm_gpio_chip *pm_gpio_chip,
+ unsigned gpio, int direction)
+{
+ int rc;
+ u8 bank1;
+
+ if (!direction || pm_gpio_chip == NULL)
+ return -EINVAL;
+
+ mutex_lock(&pm_gpio_chip->pm_lock);
+ bank1 = PM_GPIO_WRITE
+ | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_MODE_MASK);
+
+ bank1 |= ((dir_map[direction] << PM_GPIO_MODE_SHIFT)
+ & PM_GPIO_MODE_MASK);
+
+ pm_gpio_chip->bank1[gpio] = bank1;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(gpio), bank1);
+ mutex_unlock(&pm_gpio_chip->pm_lock);
+
+ if (rc)
+ pr_err("Failed on pm8xxx_writeb(): rc=%d (GPIO config)\n",
+ rc);
+
+ return rc;
+}
+
+static int pm_gpio_init_bank1(struct pm_gpio_chip *pm_gpio_chip)
+{
+ int i, rc;
+ u8 bank;
+
+ for (i = 0; i < pm_gpio_chip->gpio_chip.ngpio; i++) {
+ bank = 1 << PM_GPIO_BANK_SHIFT;
+ rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ bank);
+ if (rc) {
+ pr_err("error setting bank rc=%d\n", rc);
+ return rc;
+ }
+
+ rc = pm8xxx_readb(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ &pm_gpio_chip->bank1[i]);
+ if (rc) {
+ pr_err("error reading bank 1 rc=%d\n", rc);
+ return rc;
+ }
+ }
+ return 0;
+}
+
+static int pm_gpio_to_irq(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_chip->irq_base + offset;
+}
+
+static int pm_gpio_read(struct gpio_chip *gpio_chip, unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_get(pm_gpio_chip, offset);
+}
+
+static void pm_gpio_write(struct gpio_chip *gpio_chip,
+ unsigned offset, int val)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ pm_gpio_set(pm_gpio_chip, offset, val);
+}
+
+static int pm_gpio_direction_input(struct gpio_chip *gpio_chip,
+ unsigned offset)
+{
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ return pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_IN);
+}
+
+static int pm_gpio_direction_output(struct gpio_chip *gpio_chip,
+ unsigned offset,
+ int val)
+{
+ int ret;
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+
+ ret = pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_OUT);
+ if (!ret)
+ ret = pm_gpio_set(pm_gpio_chip, offset, val);
+
+ return ret;
+}
+
+static void pm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gpio_chip)
+{
+ static const char * const cmode[] = { "in", "in/out", "out", "off" };
+ struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
+ u8 mode, state, bank;
+ const char *label;
+ int i, j;
+
+ for (i = 0; i < gpio_chip->ngpio; i++) {
+ label = gpiochip_is_requested(gpio_chip, i);
+ mode = (pm_gpio_chip->bank1[i] & PM_GPIO_MODE_MASK) >>
+ PM_GPIO_MODE_SHIFT;
+ state = pm_gpio_get(pm_gpio_chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s",
+ gpio_chip->base + i,
+ label ? label : "--",
+ cmode[mode],
+ state ? "hi" : "lo");
+ for (j = 0; j < PM_GPIO_BANKS; j++) {
+ bank = j << PM_GPIO_BANK_SHIFT;
+ pm8xxx_writeb(gpio_chip->dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ bank);
+ pm8xxx_readb(gpio_chip->dev->parent,
+ SSBI_REG_ADDR_GPIO(i),
+ &bank);
+ seq_printf(s, " 0x%02x", bank);
+ }
+ seq_printf(s, "\n");
+ }
+}
+
+static int __devinit pm_gpio_probe(struct platform_device *pdev)
+{
+ int ret;
+ const struct pm8xxx_gpio_platform_data *pdata = pdev->dev.platform_data;
+ struct pm_gpio_chip *pm_gpio_chip;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ pm_gpio_chip = kzalloc(sizeof(struct pm_gpio_chip), GFP_KERNEL);
+ if (!pm_gpio_chip) {
+ pr_err("Cannot allocate pm_gpio_chip\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ pm_gpio_chip->bank1 = kzalloc(sizeof(u8) * pdata->gpio_cdata.ngpios,
+ GFP_KERNEL);
+ if (!pm_gpio_chip->bank1) {
+ pr_err("Cannot allocate pm_gpio_chip->bank1\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ mutex_init(&pm_gpio_chip->pm_lock);
+ pm_gpio_chip->gpio_chip.label = "pm-gpio";
+ pm_gpio_chip->gpio_chip.direction_input = pm_gpio_direction_input;
+ pm_gpio_chip->gpio_chip.direction_output = pm_gpio_direction_output;
+ pm_gpio_chip->gpio_chip.to_irq = pm_gpio_to_irq;
+ pm_gpio_chip->gpio_chip.get = pm_gpio_read;
+ pm_gpio_chip->gpio_chip.set = pm_gpio_write;
+ pm_gpio_chip->gpio_chip.dbg_show = pm_gpio_dbg_show;
+ pm_gpio_chip->gpio_chip.ngpio = pdata->gpio_cdata.ngpios;
+ pm_gpio_chip->gpio_chip.can_sleep = 1;
+ pm_gpio_chip->gpio_chip.dev = &pdev->dev;
+ pm_gpio_chip->gpio_chip.base = pdata->gpio_base;
+ pm_gpio_chip->irq_base = platform_get_irq(pdev, 0);
+ list_add(&pm_gpio_chip->link, &pm_gpio_chips);
+ platform_set_drvdata(pdev, pm_gpio_chip);
+
+ ret = gpiochip_add(&pm_gpio_chip->gpio_chip);
+ if (ret) {
+ pr_err("gpiochip_add failed ret = %d\n", ret);
+ goto reset_drvdata;
+ }
+
+ ret = pm_gpio_init_bank1(pm_gpio_chip);
+ if (ret) {
+ pr_err("gpio init bank failed ret = %d\n", ret);
+ goto remove_chip;
+ }
+
+ return 0;
+
+remove_chip:
+ if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+reset_drvdata:
+ platform_set_drvdata(pdev, NULL);
+ mutex_destroy(&pm_gpio_chip->pm_lock);
+ kfree(pm_gpio_chip);
+out:
+ return ret;
+}
+
+static int __devexit pm_gpio_remove(struct platform_device *pdev)
+{
+ struct pm_gpio_chip *pm_gpio_chip
+ = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ mutex_destroy(&pm_gpio_chip->pm_lock);
+ kfree(pm_gpio_chip->bank1);
+ kfree(pm_gpio_chip);
+ return 0;
+}
+
+int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
+{
+ int rc;
+ u8 bank[8];
+ struct pm_gpio_chip *pm_gpio_chip;
+ struct gpio_chip *gpio_chip;
+ int pm_gpio;
+ int found = 0;
+
+ if (param == NULL)
+ return -EINVAL;
+ list_for_each_entry(pm_gpio_chip, &pm_gpio_chips, link) {
+ gpio_chip = &pm_gpio_chip->gpio_chip;
+ if (gpio >= gpio_chip->base
+ && gpio < gpio_chip->base + gpio_chip->ngpio) {
+ found = 1;
+ pm_gpio = gpio - gpio_chip->base;
+ break;
+ }
+ }
+ if (!found) {
+ pr_err("called on gpio %d not handled by any pmic\n", gpio);
+ return -EINVAL;
+ }
+
+ /* Select banks and configure the gpio */
+ bank[0] = PM_GPIO_WRITE |
+ ((param->vin_sel << PM_GPIO_VIN_SHIFT) &
+ PM_GPIO_VIN_MASK) |
+ PM_GPIO_MODE_ENABLE;
+ bank[1] = PM_GPIO_WRITE |
+ ((1 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((dir_map[param->direction] <<
+ PM_GPIO_MODE_SHIFT) &
+ PM_GPIO_MODE_MASK) |
+ ((param->direction & PM_GPIO_DIR_OUT) ?
+ ((param->output_buffer & 1) ?
+ PM_GPIO_OUT_BUFFER : 0) : 0) |
+ ((param->direction & PM_GPIO_DIR_OUT) ?
+ param->output_value & 0x01 : 0);
+ bank[2] = PM_GPIO_WRITE |
+ ((2 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->pull << PM_GPIO_PULL_SHIFT) &
+ PM_GPIO_PULL_MASK);
+ bank[3] = PM_GPIO_WRITE |
+ ((3 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->out_strength <<
+ PM_GPIO_OUT_STRENGTH_SHIFT) &
+ PM_GPIO_OUT_STRENGTH_MASK);
+ bank[4] = PM_GPIO_WRITE |
+ ((4 << PM_GPIO_BANK_SHIFT) &
+ PM_GPIO_BANK_MASK) |
+ ((param->function << PM_GPIO_FUNC_SHIFT) &
+ PM_GPIO_FUNC_MASK);
+ bank[5] = PM_GPIO_WRITE |
+ ((5 << PM_GPIO_BANK_SHIFT) & PM_GPIO_BANK_MASK) |
+ (param->inv_int_pol ? 0 : PM_GPIO_NON_INT_POL_INV);
+
+ mutex_lock(&pm_gpio_chip->pm_lock);
+ /* Remember bank1 for later use */
+ pm_gpio_chip->bank1[pm_gpio] = bank[1];
+ rc = pm8xxx_write_buf(pm_gpio_chip->gpio_chip.dev->parent,
+ SSBI_REG_ADDR_GPIO(pm_gpio), bank, 6);
+ mutex_unlock(&pm_gpio_chip->pm_lock);
+
+ if (rc)
+ pr_err("Failed on pm8xxx_write_buf() rc=%d (GPIO config)\n",
+ rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_gpio_config);
+
+static struct platform_driver pm_gpio_driver = {
+ .probe = pm_gpio_probe,
+ .remove = __devexit_p(pm_gpio_remove),
+ .driver = {
+ .name = PM8XXX_GPIO_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm_gpio_init(void)
+{
+ int rc = platform_driver_register(&pm_gpio_driver);
+
+ return rc;
+}
+subsys_initcall(pm_gpio_init);
+
+static void __exit pm_gpio_exit(void)
+{
+ platform_driver_unregister(&pm_gpio_driver);
+}
+module_exit(pm_gpio_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC GPIO driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_GPIO_DEV_NAME);
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index d554551..c887ac6 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -79,6 +79,22 @@ static struct pm8xxx_drvdata pm8921_drvdata = {
.pmic_read_irq_stat = pm8921_read_irq_stat,
};

+static const struct resource gpio_cell_resources[] __devinitconst = {
+ [0] = {
+ .start = PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, 0),
+ .end = PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, 0)
+ + PM8921_NR_GPIOS - 1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mfd_cell gpio_cell __devinitdata = {
+ .name = PM8XXX_GPIO_DEV_NAME,
+ .id = -1,
+ .resources = gpio_cell_resources,
+ .num_resources = ARRAY_SIZE(gpio_cell_resources),
+};
+
static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
*pdata,
struct pm8921 *pmic,
@@ -103,7 +119,25 @@ static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
pmic->irq_data = irq_data;
}

+ if (pdata->gpio_pdata) {
+ pdata->gpio_pdata->gpio_cdata.ngpios = PM8921_NR_GPIOS;
+ pdata->gpio_pdata->gpio_cdata.rev = rev;
+ gpio_cell.platform_data = pdata->gpio_pdata;
+ gpio_cell.data_size = sizeof(struct pm8xxx_gpio_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &gpio_cell, 1,
+ NULL, irq_base);
+ if (ret) {
+ pr_err("Failed to add gpio subdevice ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
+ return 0;
bail:
+ if (pmic->irq_data) {
+ pm8xxx_irq_exit(pmic->irq_data);
+ pmic->irq_data = NULL;
+ }
return ret;
}

diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
index d2806ff..74d47c7 100644
--- a/include/linux/mfd/pm8921.h
+++ b/include/linux/mfd/pm8921.h
@@ -19,12 +19,23 @@

#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
+#include <linux/mfd/pm8xxx/gpio.h>

#define PM8921_NR_IRQS 256

+#define PM8921_NR_GPIOS 44
+
+#define PM8921_GPIO_BLOCK_START 24
+#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
+
+/* GPIOs [1,N] */
+#define PM8921_GPIO_IRQ(base, gpio) ((base) + \
+ PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, (gpio)-1))
+
struct pm8921_platform_data {
int irq_base;
struct pm8xxx_irq_platform_data *irq_pdata;
+ struct pm8xxx_gpio_platform_data *gpio_pdata;
};

#endif
diff --git a/include/linux/mfd/pm8xxx/gpio.h b/include/linux/mfd/pm8xxx/gpio.h
new file mode 100644
index 0000000..3ab08e0
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/gpio.h
@@ -0,0 +1,132 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Qualcomm PMIC8XXX gpio driver header file
+ *
+ */
+
+#ifndef __PM8XXX_GPIO_H
+#define __PM8XXX_GPIO_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_GPIO_DEV_NAME "pm8xxx-gpio"
+
+struct pm8xxx_gpio_core_data {
+ u32 rev;
+ int ngpios;
+};
+
+struct pm8xxx_gpio_platform_data {
+ struct pm8xxx_gpio_core_data gpio_cdata;
+ int gpio_base;
+};
+
+/* GPIO parameters */
+/* direction */
+#define PM_GPIO_DIR_OUT 0x01
+#define PM_GPIO_DIR_IN 0x02
+#define PM_GPIO_DIR_BOTH (PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
+
+/* output_buffer */
+#define PM_GPIO_OUT_BUF_OPEN_DRAIN 1
+#define PM_GPIO_OUT_BUF_CMOS 0
+
+/* pull */
+#define PM_GPIO_PULL_UP_30 0
+#define PM_GPIO_PULL_UP_1P5 1
+#define PM_GPIO_PULL_UP_31P5 2
+#define PM_GPIO_PULL_UP_1P5_30 3
+#define PM_GPIO_PULL_DN 4
+#define PM_GPIO_PULL_NO 5
+
+/* vin_sel: Voltage Input Select */
+#define PM_GPIO_VIN_VPH 0
+#define PM_GPIO_VIN_BB 1
+#define PM_GPIO_VIN_S3 2
+#define PM_GPIO_VIN_L3 3
+#define PM_GPIO_VIN_L7 4
+#define PM_GPIO_VIN_L6 5
+#define PM_GPIO_VIN_L5 6
+#define PM_GPIO_VIN_L2 7
+
+/* out_strength */
+#define PM_GPIO_STRENGTH_NO 0
+#define PM_GPIO_STRENGTH_HIGH 1
+#define PM_GPIO_STRENGTH_MED 2
+#define PM_GPIO_STRENGTH_LOW 3
+
+/* function */
+#define PM_GPIO_FUNC_NORMAL 0
+#define PM_GPIO_FUNC_PAIRED 1
+#define PM_GPIO_FUNC_1 2
+#define PM_GPIO_FUNC_2 3
+#define PM_GPIO_DTEST1 4
+#define PM_GPIO_DTEST2 5
+#define PM_GPIO_DTEST3 6
+#define PM_GPIO_DTEST4 7
+
+/**
+ * struct pm_gpio - structure to specify gpio configurtion values
+ * @direction: indicates whether the gpio should be input, output, or
+ * both. Should be of the type PM_GPIO_DIR_*
+ * @output_buffer: indicates gpio should be configured as CMOS or open
+ * drain. Should be of the type PM_GPIO_OUT_BUF_*
+ * @output_value: The gpio output value of the gpio line - 0 or 1
+ * @pull: Indicates whether a pull up or pull down should be
+ * applied. If a pullup is required the current strength
+ * needs to be specified. Current values of 30uA, 1.5uA,
+ * 31.5uA, 1.5uA with 30uA boost are supported. This value
+ * should be one of the PM_GPIO_PULL_*
+ * @vin_sel: specifies the voltage level when the output is set to 1.
+ * For an input gpio specifies the voltage level at which
+ * the input is interpreted as a logical 1.
+ * @out_strength: the amount of current supplied for an output gpio,
+ * should be of the type PM_GPIO_STRENGTH_*
+ * @function: choose alternate function for the gpio. Certain gpios
+ * can be paired (shorted) with each other. Some gpio pin
+ * can act as alternate functions. This parameter should
+ * be of type PM_GPIO_FUNC_*
+ * @inv_int_pol: Invert polarity before feeding the line to the interrupt
+ * module in pmic. This feature will almost be never used
+ * since the pm8xxx interrupt block can detect both edges
+ * and both levels.
+ */
+struct pm_gpio {
+ int direction;
+ int output_buffer;
+ int output_value;
+ int pull;
+ int vin_sel;
+ int out_strength;
+ int function;
+ int inv_int_pol;
+};
+
+#if defined(CONFIG_GPIO_PM8XXX) || defined(CONFIG_GPIO_PM8XXX_MODULE)
+/**
+ * pm8xxx_gpio_config - configure a gpio controlled by a pm8xxx chip
+ * @gpio: gpio number to configure
+ * @param: configuration values
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ */
+int pm8xxx_gpio_config(int gpio, struct pm_gpio *param);
+#else
+static inline int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
+{
+ return -ENXIO;
+}
+#endif
+
+#endif
--
1.7.1

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-08 06:12:22

[permalink] [raw]

Subject: [Qualcomm PM8921 MFD v2 1/6] mfd: pm8921: Add PMIC 8921 core driver

From: Abhijeet Dharmapurikar <[email protected]>

Add support for the Qualcomm PM8921 PMIC chip. The core driver
will communicate with the PMIC chip via the MSM SSBI bus.

Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
---
drivers/mfd/Kconfig | 18 +++++
drivers/mfd/Makefile | 1 +
drivers/mfd/pm8921-core.c | 157 +++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pm8921.h | 26 +++++++
include/linux/mfd/pm8xxx/core.h | 66 ++++++++++++++++
5 files changed, 268 insertions(+), 0 deletions(-)
create mode 100644 drivers/mfd/pm8921-core.c
create mode 100644 include/linux/mfd/pm8921.h
create mode 100644 include/linux/mfd/pm8xxx/core.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index fd01836..46f0d2f 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -624,6 +624,24 @@ config MFD_WL1273_CORE
driver connects the radio-wl1273 V4L2 module and the wl1273
audio codec.

+config MFD_PM8XXX
+ tristate
+
+config MFD_PM8921_CORE
+ tristate "Qualcomm PM8921 PMIC chip"
+ depends on MSM_SSBI
+ select MFD_CORE
+ select MFD_PM8XXX
+ help
+ If you say yes to this option, support will be included for the
+ built-in PM8921 PMIC chip
+
+ This is required if your board has a PM8921 and uses its features,
+ such as: MPPs, GPIOs, regulators, interrupts, and PWM.
+
+ Say M here if you want to include support for PM8921 chip as a module.
+ This will build a module called "pm8921-core.ko".
+
endif # MFD_SUPPORT

menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index a54e2c7..ec158da 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -83,3 +83,4 @@ obj-$(CONFIG_MFD_TPS6586X) += tps6586x.o
obj-$(CONFIG_MFD_VX855) += vx855.o
obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
+obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
new file mode 100644
index 0000000..06c39e1
--- /dev/null
+++ b/drivers/mfd/pm8921-core.c
@@ -0,0 +1,157 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/msm_ssbi.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/pm8921.h>
+#include <linux/mfd/pm8xxx/core.h>
+
+#define REG_HWREV 0x002 /* PMIC4 revision */
+#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */
+
+struct pm8921 {
+ struct device *dev;
+};
+
+static int pm8921_readb(const struct device *dev, u16 addr, u8 *val)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_read(pmic->dev->parent, addr, val, 1);
+}
+
+static int pm8921_writeb(const struct device *dev, u16 addr, u8 val)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_write(pmic->dev->parent, addr, &val, 1);
+}
+
+static int pm8921_read_buf(const struct device *dev, u16 addr, u8 *buf,
+ int cnt)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_read(pmic->dev->parent, addr, buf, cnt);
+}
+
+static int pm8921_write_buf(const struct device *dev, u16 addr, u8 *buf,
+ int cnt)
+{
+ const struct pm8xxx_drvdata *pm8921_drvdata = dev_get_drvdata(dev);
+ const struct pm8921 *pmic = pm8921_drvdata->pm_chip_data;
+
+ return msm_ssbi_write(pmic->dev->parent, addr, buf, cnt);
+}
+
+static struct pm8xxx_drvdata pm8921_drvdata = {
+ .pmic_readb = pm8921_readb,
+ .pmic_writeb = pm8921_writeb,
+ .pmic_read_buf = pm8921_read_buf,
+ .pmic_write_buf = pm8921_write_buf,
+};
+
+static int __devinit pm8921_probe(struct platform_device *pdev)
+{
+ const struct pm8921_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8921 *pmic;
+ int rc;
+ u8 val;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ return -EINVAL;
+ }
+
+ pmic = kzalloc(sizeof(struct pm8921), GFP_KERNEL);
+ if (!pmic) {
+ pr_err("Cannot alloc pm8921 struct\n");
+ return -ENOMEM;
+ }
+
+ /* Read PMIC chip revision */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_HWREV, &val, sizeof(val));
+ if (rc) {
+ pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
+ goto err_read_rev;
+ }
+ pr_info("PMIC revision 1: %02X\n", val);
+
+ /* Read PMIC chip revision 2 */
+ rc = msm_ssbi_read(pdev->dev.parent, REG_HWREV_2, &val, sizeof(val));
+ if (rc) {
+ pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
+ REG_HWREV_2, rc);
+ goto err_read_rev;
+ }
+ pr_info("PMIC revision 2: %02X\n", val);
+
+ pmic->dev = &pdev->dev;
+ pm8921_drvdata.pm_chip_data = pmic;
+ platform_set_drvdata(pdev, &pm8921_drvdata);
+
+ return 0;
+
+err_read_rev:
+ kfree(pmic);
+ return rc;
+}
+
+static int __devexit pm8921_remove(struct platform_device *pdev)
+{
+ struct pm8xxx_drvdata *drvdata;
+ struct pm8921 *pmic = NULL;
+
+ drvdata = platform_get_drvdata(pdev);
+ if (drvdata)
+ pmic = drvdata->pm_chip_data;
+ if (pmic)
+ mfd_remove_devices(pmic->dev);
+ platform_set_drvdata(pdev, NULL);
+ kfree(pmic);
+
+ return 0;
+}
+
+static struct platform_driver pm8921_driver = {
+ .probe = pm8921_probe,
+ .remove = __devexit_p(pm8921_remove),
+ .driver = {
+ .name = "pm8921-core",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8921_init(void)
+{
+ return platform_driver_register(&pm8921_driver);
+}
+subsys_initcall(pm8921_init);
+
+static void __exit pm8921_exit(void)
+{
+ platform_driver_unregister(&pm8921_driver);
+}
+module_exit(pm8921_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PMIC 8921 core driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:pm8921-core");
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
new file mode 100644
index 0000000..6bed710
--- /dev/null
+++ b/include/linux/mfd/pm8921.h
@@ -0,0 +1,26 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8921 driver header file
+ *
+ */
+
+#ifndef __MFD_PM8921_H
+#define __MFD_PM8921_H
+
+#include <linux/device.h>
+
+struct pm8921_platform_data {
+ int irq_base;
+};
+
+#endif
diff --git a/include/linux/mfd/pm8xxx/core.h b/include/linux/mfd/pm8xxx/core.h
new file mode 100644
index 0000000..61f1c01
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/core.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PMIC 8xxx driver header file
+ *
+ */
+
+#ifndef __MFD_PM8XXX_CORE_H
+#define __MFD_PM8XXX_CORE_H
+
+#include <linux/mfd/core.h>
+
+struct pm8xxx_drvdata {
+ int (*pmic_readb) (const struct device *dev, u16 addr, u8 *val);
+ int (*pmic_writeb) (const struct device *dev, u16 addr, u8 val);
+ int (*pmic_read_buf) (const struct device *dev, u16 addr, u8 *buf,
+ int n);
+ int (*pmic_write_buf) (const struct device *dev, u16 addr, u8 *buf,
+ int n);
+ void *pm_chip_data;
+};
+
+static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_readb(dev, addr, val);
+}
+
+static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_writeb(dev, addr, val);
+}
+
+static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
+ int n)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_read_buf(dev, addr, buf, n);
+}
+
+static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
+ int n)
+{
+ struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
+
+ BUG_ON(!dd);
+ return dd->pmic_write_buf(dev, addr, buf, n);
+}
+
+#endif
--
1.7.1

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-08 06:12:25

[permalink] [raw]

Subject: [Qualcomm PM8921 MFD v2 4/6] mfd: pm8xxx-mpp: Add pm8xxx MPP driver

From: David Collins <[email protected]>

Add support for multi-purpose pins (MPPs) on Qualcomm PM8xxx
PMIC chips.

PM8xxx MPPs can be configured as digital or analog inputs or
outputs, current sinks, or buffers.

Signed-off-by: David Collins <[email protected]>
---
drivers/mfd/Kconfig | 8 +
drivers/mfd/Makefile | 1 +
drivers/mfd/pm8921-core.c | 31 ++++
drivers/mfd/pm8xxx-mpp.c | 320 ++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pm8921.h | 9 +-
include/linux/mfd/pm8xxx/mpp.h | 233 +++++++++++++++++++++++++++++
6 files changed, 601 insertions(+), 1 deletions(-)
create mode 100644 drivers/mfd/pm8xxx-mpp.c
create mode 100644 include/linux/mfd/pm8xxx/mpp.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 318e42a..0000dac 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -652,6 +652,14 @@ config MFD_PM8XXX_IRQ
This is required to use certain other PM 8xxx features, such as GPIO
and MPP.

+config MFD_PM8XXX_MPP
+ tristate "Support for Qualcomm PM8xxx MPP features"
+ depends on MFD_PM8XXX
+ default y if MFD_PM8XXX
+ help
+ This is the multi-purpose pin (MPP) driver for Qualcomm PM 8xxx PMIC
+ chips.
+
endif # MFD_SUPPORT

menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 5fc9315..8891177 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -85,3 +85,4 @@ obj-$(CONFIG_MFD_WL1273_CORE) += wl1273-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
+obj-$(CONFIG_MFD_PM8XXX_MPP) += pm8xxx-mpp.o
diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
index c887ac6..e9411fc 100644
--- a/drivers/mfd/pm8921-core.c
+++ b/drivers/mfd/pm8921-core.c
@@ -24,6 +24,8 @@
#define REG_HWREV 0x002 /* PMIC4 revision */
#define REG_HWREV_2 0x0E8 /* PMIC4 revision 2 */

+#define REG_MPP_BASE 0x050
+
struct pm8921 {
struct device *dev;
void *irq_data;
@@ -95,6 +97,22 @@ static struct mfd_cell gpio_cell __devinitdata = {
.num_resources = ARRAY_SIZE(gpio_cell_resources),
};

+static const struct resource mpp_cell_resources[] __devinitconst = {
+ {
+ .start = PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, 0),
+ .end = PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, 0)
+ + PM8921_NR_MPPS - 1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mfd_cell mpp_cell __devinitdata = {
+ .name = PM8XXX_MPP_DEV_NAME,
+ .id = -1,
+ .resources = mpp_cell_resources,
+ .num_resources = ARRAY_SIZE(mpp_cell_resources),
+};
+
static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
*pdata,
struct pm8921 *pmic,
@@ -132,6 +150,19 @@ static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
}
}

+ if (pdata->mpp_pdata) {
+ pdata->mpp_pdata->core_data.nmpps = PM8921_NR_MPPS;
+ pdata->mpp_pdata->core_data.base_addr = REG_MPP_BASE;
+ mpp_cell.platform_data = pdata->mpp_pdata;
+ mpp_cell.data_size = sizeof(struct pm8xxx_mpp_platform_data);
+ ret = mfd_add_devices(pmic->dev, 0, &mpp_cell, 1, NULL,
+ irq_base);
+ if (ret) {
+ pr_err("Failed to add mpp subdevice ret=%d\n", ret);
+ goto bail;
+ }
+ }
+
return 0;
bail:
if (pmic->irq_data) {
diff --git a/drivers/mfd/pm8xxx-mpp.c b/drivers/mfd/pm8xxx-mpp.c
new file mode 100644
index 0000000..174294a
--- /dev/null
+++ b/drivers/mfd/pm8xxx-mpp.c
@@ -0,0 +1,320 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Qualcomm PM8XXX Multi-Purpose Pin (MPP) driver
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/seq_file.h>
+#include <linux/slab.h>
+#include <linux/mfd/pm8xxx/core.h>
+#include <linux/mfd/pm8xxx/mpp.h>
+
+/* MPP Type */
+#define PM8XXX_MPP_TYPE_MASK 0xE0
+#define PM8XXX_MPP_TYPE_SHIFT 5
+
+/* MPP Config Level */
+#define PM8XXX_MPP_CONFIG_LVL_MASK 0x1C
+#define PM8XXX_MPP_CONFIG_LVL_SHIFT 2
+
+/* MPP Config Control */
+#define PM8XXX_MPP_CONFIG_CTRL_MASK 0x03
+#define PM8XXX_MPP_CONFIG_CTRL_SHIFT 0
+
+struct pm8xxx_mpp_chip {
+ struct list_head link;
+ struct gpio_chip gpio_chip;
+ struct mutex pm_lock;
+ u8 *ctrl_reg;
+ int mpp_base;
+ int irq_base;
+ int nmpps;
+ u16 base_addr;
+};
+
+static LIST_HEAD(pm8xxx_mpp_chips);
+
+static int pm8xxx_mpp_write(struct pm8xxx_mpp_chip *mpp_chip, u16 offset,
+ u8 val, u8 mask)
+{
+ u8 reg;
+ int rc;
+
+ mutex_lock(&mpp_chip->pm_lock);
+
+ reg = (mpp_chip->ctrl_reg[offset] & ~mask) | (val & mask);
+ rc = pm8xxx_writeb(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->base_addr + offset, reg);
+ if (!rc)
+ mpp_chip->ctrl_reg[offset] = reg;
+
+ mutex_unlock(&mpp_chip->pm_lock);
+
+ return rc;
+}
+
+static int pm8xxx_mpp_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+
+ return mpp_chip->irq_base + offset;
+}
+
+static int pm8xxx_mpp_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc;
+
+ if ((mpp_chip->ctrl_reg[offset] & PM8XXX_MPP_TYPE_MASK) >>
+ PM8XXX_MPP_TYPE_SHIFT == PM8XXX_MPP_TYPE_D_OUTPUT)
+ rc = mpp_chip->ctrl_reg[offset] & PM8XXX_MPP_CONFIG_CTRL_MASK;
+ else
+ rc = pm8xxx_read_irq_stat(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->irq_base + offset);
+
+ return rc;
+}
+
+static void pm8xxx_mpp_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = val ? PM8XXX_MPP_DOUT_CTRL_HIGH : PM8XXX_MPP_DOUT_CTRL_LOW;
+ int rc;
+
+ rc = pm8xxx_mpp_write(mpp_chip, offset, reg,
+ PM8XXX_MPP_CONFIG_CTRL_MASK);
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+}
+
+static int pm8xxx_mpp_dir_input(struct gpio_chip *chip, unsigned offset)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ int rc = pm8xxx_mpp_write(mpp_chip, offset,
+ PM8XXX_MPP_TYPE_D_INPUT << PM8XXX_MPP_TYPE_SHIFT,
+ PM8XXX_MPP_TYPE_MASK);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+ return rc;
+}
+
+static int pm8xxx_mpp_dir_output(struct gpio_chip *chip,
+ unsigned offset, int val)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 reg = (PM8XXX_MPP_TYPE_D_OUTPUT << PM8XXX_MPP_TYPE_SHIFT) |
+ (val & PM8XXX_MPP_CONFIG_CTRL_MASK);
+ u8 mask = PM8XXX_MPP_TYPE_MASK | PM8XXX_MPP_CONFIG_CTRL_MASK;
+ int rc = pm8xxx_mpp_write(mpp_chip, offset, reg, mask);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+ return rc;
+}
+
+static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
+{
+ static const char * const ctype[] = { "d_in", "d_out", "bi_dir",
+ "a_in", "a_out", "sink",
+ "dtest_sink", "dtest_out"
+ };
+ struct pm8xxx_mpp_chip *mpp_chip = dev_get_drvdata(chip->dev);
+ u8 type, state;
+ const char *label;
+ int i;
+
+ for (i = 0; i < mpp_chip->nmpps; i++) {
+ label = gpiochip_is_requested(chip, i);
+ type = (mpp_chip->ctrl_reg[i] & PM8XXX_MPP_TYPE_MASK) >>
+ PM8XXX_MPP_TYPE_SHIFT;
+ state = pm8xxx_mpp_get(chip, i);
+ seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
+ " %s 0x%02x\n",
+ chip->base + i,
+ label ? label : "--",
+ ctype[type],
+ state ? "hi" : "lo",
+ mpp_chip->ctrl_reg[i]);
+ }
+}
+
+int pm8xxx_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control)
+{
+ struct pm8xxx_mpp_chip *mpp_chip;
+ int found = 0;
+ u8 config, mask;
+ int rc;
+
+ list_for_each_entry(mpp_chip, &pm8xxx_mpp_chips, link) {
+ if (mpp >= mpp_chip->mpp_base
+ && mpp < mpp_chip->mpp_base + mpp_chip->nmpps) {
+ found = 1;
+ break;
+ }
+ }
+ if (!found) {
+ pr_err("called on mpp %d not handled by any pmic\n", mpp);
+ return -EINVAL;
+ }
+
+ mask = PM8XXX_MPP_TYPE_MASK | PM8XXX_MPP_CONFIG_LVL_MASK |
+ PM8XXX_MPP_CONFIG_CTRL_MASK;
+ config = (type << PM8XXX_MPP_TYPE_SHIFT) & PM8XXX_MPP_TYPE_MASK;
+ config |= (level << PM8XXX_MPP_CONFIG_LVL_SHIFT) &
+ PM8XXX_MPP_CONFIG_LVL_MASK;
+ config |= control & PM8XXX_MPP_CONFIG_CTRL_MASK;
+
+ rc = pm8xxx_mpp_write(mpp_chip, mpp - mpp_chip->mpp_base, config, mask);
+
+ if (rc)
+ pr_err("pm8xxx_mpp_write(): rc=%d\n", rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(pm8xxx_mpp_config);
+
+static int __devinit pm8xxx_mpp_reg_init(struct pm8xxx_mpp_chip *mpp_chip)
+{
+ int rc, i;
+
+ for (i = 0; i < mpp_chip->nmpps; i++) {
+ rc = pm8xxx_readb(mpp_chip->gpio_chip.dev->parent,
+ mpp_chip->base_addr + i,
+ &mpp_chip->ctrl_reg[i]);
+ if (rc)
+ goto bail;
+ }
+
+bail:
+ return rc;
+}
+
+static int __devinit pm8xxx_mpp_probe(struct platform_device *pdev)
+{
+ int rc;
+ const struct pm8xxx_mpp_platform_data *pdata = pdev->dev.platform_data;
+ struct pm8xxx_mpp_chip *mpp_chip;
+
+ if (!pdata) {
+ pr_err("missing platform data\n");
+ rc = -EINVAL;
+ goto out;
+ }
+
+ mpp_chip = kzalloc(sizeof(struct pm8xxx_mpp_chip), GFP_KERNEL);
+ if (!mpp_chip) {
+ pr_err("Cannot allocate %d bytes\n",
+ sizeof(struct pm8xxx_mpp_chip));
+ rc = -ENOMEM;
+ goto out;
+ }
+
+ mpp_chip->ctrl_reg = kzalloc(pdata->core_data.nmpps, GFP_KERNEL);
+ if (!mpp_chip->ctrl_reg) {
+ pr_err("Cannot allocate %d bytes\n", pdata->core_data.nmpps);
+ rc = -ENOMEM;
+ goto free_mpp_chip;
+ }
+
+ mutex_init(&mpp_chip->pm_lock);
+
+ mpp_chip->gpio_chip.label = PM8XXX_MPP_DEV_NAME;
+ mpp_chip->gpio_chip.direction_input = pm8xxx_mpp_dir_input;
+ mpp_chip->gpio_chip.direction_output = pm8xxx_mpp_dir_output;
+ mpp_chip->gpio_chip.to_irq = pm8xxx_mpp_to_irq;
+ mpp_chip->gpio_chip.get = pm8xxx_mpp_get;
+ mpp_chip->gpio_chip.set = pm8xxx_mpp_set;
+ mpp_chip->gpio_chip.dbg_show = pm8xxx_mpp_dbg_show;
+ mpp_chip->gpio_chip.ngpio = pdata->core_data.nmpps;
+ mpp_chip->gpio_chip.can_sleep = 1;
+ mpp_chip->gpio_chip.dev = &pdev->dev;
+ mpp_chip->gpio_chip.base = pdata->mpp_base;
+ mpp_chip->irq_base = platform_get_irq(pdev, 0);
+ mpp_chip->mpp_base = pdata->mpp_base;
+ mpp_chip->base_addr = pdata->core_data.base_addr;
+ mpp_chip->nmpps = pdata->core_data.nmpps;
+
+ list_add(&mpp_chip->link, &pm8xxx_mpp_chips);
+ platform_set_drvdata(pdev, mpp_chip);
+
+ rc = gpiochip_add(&mpp_chip->gpio_chip);
+ if (rc) {
+ pr_err("gpiochip_add failed, rc=%d\n", rc);
+ goto reset_drvdata;
+ }
+
+ rc = pm8xxx_mpp_reg_init(mpp_chip);
+ if (rc) {
+ pr_err("failed to read MPP ctrl registers, rc=%d\n", rc);
+ goto remove_chip;
+ }
+
+ return 0;
+
+remove_chip:
+ if (gpiochip_remove(&mpp_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+reset_drvdata:
+ platform_set_drvdata(pdev, NULL);
+ mutex_destroy(&mpp_chip->pm_lock);
+free_mpp_chip:
+ kfree(mpp_chip);
+out:
+ return rc;
+}
+
+static int __devexit pm8xxx_mpp_remove(struct platform_device *pdev)
+{
+ struct pm8xxx_mpp_chip *mpp_chip = platform_get_drvdata(pdev);
+
+ platform_set_drvdata(pdev, NULL);
+ if (gpiochip_remove(&mpp_chip->gpio_chip))
+ pr_err("failed to remove gpio chip\n");
+ mutex_destroy(&mpp_chip->pm_lock);
+ kfree(mpp_chip->ctrl_reg);
+ kfree(mpp_chip);
+
+ return 0;
+}
+
+static struct platform_driver pm8xxx_mpp_driver = {
+ .probe = pm8xxx_mpp_probe,
+ .remove = __devexit_p(pm8xxx_mpp_remove),
+ .driver = {
+ .name = PM8XXX_MPP_DEV_NAME,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init pm8xxx_mpp_init(void)
+{
+ return platform_driver_register(&pm8xxx_mpp_driver);
+}
+subsys_initcall(pm8xxx_mpp_init);
+
+static void __exit pm8xxx_mpp_exit(void)
+{
+ platform_driver_unregister(&pm8xxx_mpp_driver);
+}
+module_exit(pm8xxx_mpp_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("PM8XXX MPP driver");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("platform:" PM8XXX_MPP_DEV_NAME);
diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
index 74d47c7..1867bdb 100644
--- a/include/linux/mfd/pm8921.h
+++ b/include/linux/mfd/pm8921.h
@@ -20,22 +20,29 @@
#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/gpio.h>
+#include <linux/mfd/pm8xxx/mpp.h>

#define PM8921_NR_IRQS 256

#define PM8921_NR_GPIOS 44

+#define PM8921_NR_MPPS 12
+
#define PM8921_GPIO_BLOCK_START 24
+#define PM8921_MPP_BLOCK_START 16
#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))

-/* GPIOs [1,N] */
+/* GPIOs and MPPs [1,N] */
#define PM8921_GPIO_IRQ(base, gpio) ((base) + \
PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, (gpio)-1))
+#define PM8921_MPP_IRQ(base, mpp) ((base) + \
+ PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, (mpp)-1))

struct pm8921_platform_data {
int irq_base;
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_gpio_platform_data *gpio_pdata;
+ struct pm8xxx_mpp_platform_data *mpp_pdata;
};

#endif
diff --git a/include/linux/mfd/pm8xxx/mpp.h b/include/linux/mfd/pm8xxx/mpp.h
new file mode 100644
index 0000000..c779760
--- /dev/null
+++ b/include/linux/mfd/pm8xxx/mpp.h
@@ -0,0 +1,233 @@
+/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PM8XXX_MPP_H
+#define __PM8XXX_MPP_H
+
+#include <linux/errno.h>
+
+#define PM8XXX_MPP_DEV_NAME "pm8xxx-mpp"
+
+struct pm8xxx_mpp_core_data {
+ int base_addr;
+ int nmpps;
+};
+
+struct pm8xxx_mpp_platform_data {
+ struct pm8xxx_mpp_core_data core_data;
+ int mpp_base;
+};
+
+/* API */
+#if defined(CONFIG_MFD_PM8XXX_MPP) || defined(CONFIG_MFD_PM8XXX_MPP_MODULE)
+
+/**
+ * pm8xxx_mpp_config() - configure control options of a multi-purpose pin (MPP)
+ * @mpp: global GPIO number corresponding to the MPP
+ * @type: MPP type which determines the overall MPP function (i.e. digital
+ * in/out/bi, analog in/out, current sink, or test). It should be
+ * set to the value of one of PM8XXX_MPP_TYPE_D_*.
+ * @level: meaning depends upon MPP type specified
+ * @control: meaning depends upon MPP type specified
+ * Context: can sleep
+ *
+ * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
+ *
+ * Usage of level argument:
+ * 1. type = PM8XXX_MPP_TYPE_D_INPUT, PM8XXX_MPP_TYPE_D_OUTPUT,
+ * PM8XXX_MPP_TYPE_D_BI_DIR, or PM8XXX_MPP_TYPE_DTEST_OUTPUT -
+ *
+ * level specifies that digital logic level to use for the MPP. It should
+ * be set to the value of one of PM8XXX_MPP_DIG_LEVEL_*. Actual regulator
+ * connections for these level choices are PMIC chip specific.
+ *
+ * 2. type = PM8XXX_MPP_TYPE_A_INPUT -
+ *
+ * level specifies where in the PMIC chip the analog input value should
+ * be routed to. It should be set to the value of one of
+ * PM8XXX_MPP_AIN_AMUX_*.
+ *
+ * 3. type = PM8XXX_MPP_TYPE_A_OUTPUT -
+ *
+ * level specifies the output analog voltage reference level. It should
+ * be set to the value of one of PM8XXX_MPP_AOUT_LVL_*.
+ *
+ * 4. type = PM8XXX_MPP_TYPE_SINK or PM8XXX_MPP_TYPE_DTEST_SINK -
+ *
+ * level specifies the output current level. It should be set to the value
+ * of one of PM8XXX_MPP_CS_OUT_*.
+ *
+ * Usage of control argument:
+ * 1. type = PM8XXX_MPP_TYPE_D_INPUT -
+ *
+ * control specifies how the digital input should be routed in the chip.
+ * It should be set to the value of one of PM8XXX_MPP_DIN_TO_*.
+ *
+ * 2. type = PM8XXX_MPP_TYPE_D_OUTPUT -
+ *
+ * control specifies the digital output value. It should be set to the
+ * value of one of PM8XXX_MPP_DOUT_CTRL_*.
+ *
+ * 3. type = PM8XXX_MPP_TYPE_D_BI_DIR -
+ *
+ * control specifies the pullup resistor value. It should be set to the
+ * value of one of PM8XXX_MPP_BI_PULLUP_*.
+ *
+ * 4. type = PM8XXX_MPP_TYPE_A_INPUT -
+ *
+ * control is unused; a value of 0 is sufficient.
+ *
+ * 5. type = PM8XXX_MPP_TYPE_A_OUTPUT -
+ *
+ * control specifies if analog output is enabled. It should be set to the
+ * value of one of PM8XXX_MPP_AOUT_CTRL_*.
+ *
+ * 6. type = PM8XXX_MPP_TYPE_SINK -
+ *
+ * control specifies if current sinking is enabled. It should be set to
+ * the value of one of PM8XXX_MPP_CS_CTRL_*.
+ *
+ * 7. type = PM8XXX_MPP_TYPE_DTEST_SINK -
+ *
+ * control specifies if current sinking is enabled. It should be set to
+ * the value of one of PM8XXX_MPP_DTEST_CS_CTRL_*.
+ *
+ * 8. type = PM8XXX_MPP_TYPE_DTEST_OUTPUT -
+ *
+ * control specifies which DTEST bus value to output. It should be set to
+ * the value of one of PM8XXX_MPP_DTEST_*.
+ */
+int pm8xxx_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control);
+
+#else
+
+static inline int pm8xxx_mpp_config(unsigned mpp, unsigned type, unsigned level,
+ unsigned control)
+{
+ return -ENXIO;
+}
+
+#endif
+
+/* MPP Type: type */
+#define PM8XXX_MPP_TYPE_D_INPUT 0
+#define PM8XXX_MPP_TYPE_D_OUTPUT 1
+#define PM8XXX_MPP_TYPE_D_BI_DIR 2
+#define PM8XXX_MPP_TYPE_A_INPUT 3
+#define PM8XXX_MPP_TYPE_A_OUTPUT 4
+#define PM8XXX_MPP_TYPE_SINK 5
+#define PM8XXX_MPP_TYPE_DTEST_SINK 6
+#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
+
+/* Digital Input/Output: level */
+#define PM8XXX_MPP_DIG_LEVEL_VIO_0 0
+#define PM8XXX_MPP_DIG_LEVEL_VIO_1 1
+#define PM8XXX_MPP_DIG_LEVEL_VIO_2 2
+#define PM8XXX_MPP_DIG_LEVEL_VIO_3 3
+#define PM8XXX_MPP_DIG_LEVEL_VIO_4 4
+#define PM8XXX_MPP_DIG_LEVEL_VIO_5 5
+#define PM8XXX_MPP_DIG_LEVEL_VIO_6 6
+#define PM8XXX_MPP_DIG_LEVEL_VIO_7 7
+
+/* Digital Input/Output: level [PM8058] */
+#define PM8058_MPP_DIG_LEVEL_VPH 0
+#define PM8058_MPP_DIG_LEVEL_S3 1
+#define PM8058_MPP_DIG_LEVEL_L2 2
+#define PM8058_MPP_DIG_LEVEL_L3 3
+
+/* Digital Input/Output: level [PM8901] */
+#define PM8901_MPP_DIG_LEVEL_MSMIO 0
+#define PM8901_MPP_DIG_LEVEL_DIG 1
+#define PM8901_MPP_DIG_LEVEL_L5 2
+#define PM8901_MPP_DIG_LEVEL_S4 3
+#define PM8901_MPP_DIG_LEVEL_VPH 4
+
+/* Digital Input/Output: level [PM8921] */
+#define PM8921_MPP_DIG_LEVEL_S4 1
+#define PM8921_MPP_DIG_LEVEL_L15 3
+#define PM8921_MPP_DIG_LEVEL_L17 4
+#define PM8921_MPP_DIG_LEVEL_VPH 7
+
+/* Digital Input: control */
+#define PM8XXX_MPP_DIN_TO_INT 0
+#define PM8XXX_MPP_DIN_TO_DBUS1 1
+#define PM8XXX_MPP_DIN_TO_DBUS2 2
+#define PM8XXX_MPP_DIN_TO_DBUS3 3
+
+/* Digital Output: control */
+#define PM8XXX_MPP_DOUT_CTRL_LOW 0
+#define PM8XXX_MPP_DOUT_CTRL_HIGH 1
+#define PM8XXX_MPP_DOUT_CTRL_MPP 2
+#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
+
+/* Bidirectional: control */
+#define PM8XXX_MPP_BI_PULLUP_1KOHM 0
+#define PM8XXX_MPP_BI_PULLUP_OPEN 1
+#define PM8XXX_MPP_BI_PULLUP_10KOHM 2
+#define PM8XXX_MPP_BI_PULLUP_30KOHM 3
+
+/* Analog Input: level */
+#define PM8XXX_MPP_AIN_AMUX_CH5 0
+#define PM8XXX_MPP_AIN_AMUX_CH6 1
+#define PM8XXX_MPP_AIN_AMUX_CH7 2
+#define PM8XXX_MPP_AIN_AMUX_CH8 3
+#define PM8XXX_MPP_AIN_AMUX_CH9 4
+#define PM8XXX_MPP_AIN_AMUX_ABUS1 5
+#define PM8XXX_MPP_AIN_AMUX_ABUS2 6
+#define PM8XXX_MPP_AIN_AMUX_ABUS3 7
+
+/* Analog Output: level */
+#define PM8XXX_MPP_AOUT_LVL_1V25 0
+#define PM8XXX_MPP_AOUT_LVL_1V25_2 1
+#define PM8XXX_MPP_AOUT_LVL_0V625 2
+#define PM8XXX_MPP_AOUT_LVL_0V3125 3
+#define PM8XXX_MPP_AOUT_LVL_MPP 4
+#define PM8XXX_MPP_AOUT_LVL_ABUS1 5
+#define PM8XXX_MPP_AOUT_LVL_ABUS2 6
+#define PM8XXX_MPP_AOUT_LVL_ABUS3 7
+
+/* Analog Output: control */
+#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
+#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
+#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
+#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
+
+/* Current Sink: level */
+#define PM8XXX_MPP_CS_OUT_5MA 0
+#define PM8XXX_MPP_CS_OUT_10MA 1
+#define PM8XXX_MPP_CS_OUT_15MA 2
+#define PM8XXX_MPP_CS_OUT_20MA 3
+#define PM8XXX_MPP_CS_OUT_25MA 4
+#define PM8XXX_MPP_CS_OUT_30MA 5
+#define PM8XXX_MPP_CS_OUT_35MA 6
+#define PM8XXX_MPP_CS_OUT_40MA 7
+
+/* Current Sink: control */
+#define PM8XXX_MPP_CS_CTRL_DISABLE 0
+#define PM8XXX_MPP_CS_CTRL_ENABLE 1
+#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
+#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
+
+/* DTEST Current Sink: control */
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
+#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
+
+/* DTEST Digital Output: control */
+#define PM8XXX_MPP_DTEST_DBUS1 0
+#define PM8XXX_MPP_DTEST_DBUS2 1
+#define PM8XXX_MPP_DTEST_DBUS3 2
+#define PM8XXX_MPP_DTEST_DBUS4 3
+
+#endif
--
1.7.1

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-08 06:12:29

[permalink] [raw]

Subject: [Qualcomm PM8921 MFD v2 6/6] msm: board-8960: Add support for pm8921

From: Abhijeet Dharmapurikar <[email protected]>

Add device structure declarations to the msm8960 board file
for PMIC 8921 chip and its subdevices.

Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
Signed-off-by: David Collins <[email protected]>
---
arch/arm/mach-msm/board-msm8960.c | 47 ++++++++++++++++++++++------
arch/arm/mach-msm/include/mach/irqs-8960.h | 9 ++---
2 files changed, 41 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index bf1a24b..8516f51 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -8,19 +8,15 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
*/
+
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/clkdev.h>
#include <linux/msm_ssbi.h>
+#include <linux/mfd/pm8921.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -28,9 +24,18 @@

#include <mach/board.h>
#include <mach/msm_iomap.h>
+#include <mach/irqs.h>

#include "devices.h"

+/* Macros assume PMIC GPIOs and MPPs start at 1 */
+#define PM8921_GPIO_BASE NR_GPIO_IRQS
+#define PM8921_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_GPIO_BASE)
+#define PM8921_MPP_BASE (PM8921_GPIO_BASE + PM8921_NR_GPIOS)
+#define PM8921_MPP_PM_TO_SYS(pm_gpio) (pm_gpio - 1 + PM8921_MPP_BASE)
+#define PM8921_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
+#define PM8921_MPP_IRQ_BASE (PM8921_IRQ_BASE + NR_GPIO_IRQS)
+
static void __init msm8960_map_io(void)
{
msm_map_msm8960_io();
@@ -65,12 +70,34 @@ static struct platform_device *sim_devices[] __initdata = {

static struct platform_device *rumi3_devices[] __initdata = {
&msm8960_device_uart_gsbi5,
+ &msm8960_device_ssbi_pm8921,
+};
+
+static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = {
+ .irq_base = PM8921_IRQ_BASE,
+ .devirq = MSM_GPIO_TO_INT(104),
+ .irq_trigger_flag = IRQF_TRIGGER_LOW,
+};
+
+static struct pm8xxx_gpio_platform_data pm8xxx_gpio_pdata __devinitdata = {
+ .gpio_base = PM8921_GPIO_PM_TO_SYS(1),
+};
+
+static struct pm8xxx_mpp_platform_data pm8xxx_mpp_pdata __devinitdata = {
+ .mpp_base = PM8921_MPP_PM_TO_SYS(1),
+};
+
+static struct pm8921_platform_data pm8921_platform_data __devinitdata = {
+ .irq_pdata = &pm8xxx_irq_pdata,
+ .gpio_pdata = &pm8xxx_gpio_pdata,
+ .mpp_pdata = &pm8xxx_mpp_pdata,
};

-static struct msm_ssbi_platform_data msm8960_ssbi_pm8921_pdata = {
- .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
- .slave = {
- .name = "pm8921-core",
+static struct msm_ssbi_platform_data msm8960_ssbi_pm8921_pdata __initdata = {
+ .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
+ .slave = {
+ .name = "pm8921-core",
+ .platform_data = &pm8921_platform_data,
},
};

diff --git a/arch/arm/mach-msm/include/mach/irqs-8960.h b/arch/arm/mach-msm/include/mach/irqs-8960.h
index 81ab2a6..0a5b9c5 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8960.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8960.h
@@ -267,11 +267,10 @@
#define PM8921_SEC_IRQ_104 (GIC_SPI_START + 225)
#define PM8018_SEC_IRQ_107 (GIC_SPI_START + 226)

-/* For now, use the maximum number of interrupts until a pending GIC issue
- * is sorted out */
-#define NR_MSM_IRQS 1020
-#define NR_BOARD_IRQS 0
-#define NR_GPIO_IRQS 0
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 150
+#define NR_PM8921_IRQS 256
+#define NR_BOARD_IRQS (NR_PM8921_IRQS)

#endif

--
1.7.1

Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-08 12:05:55

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Mon, 7 Mar 2011, [email protected] wrote:
> +static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
> + *pdata,
> + struct pm8921 *pmic,
> + u32 rev)
> +{
> + int ret = 0;
> + int irq_base = 0;
> + void *irq_data;
> +
> + if (pdata->irq_pdata) {

So if pdata->irq_pdata == NULL you return success. Is that correct ?
Also please return early on (!pdata->irq_pdata) and avoid that extra
indent level for the real code path.

> + pdata->irq_pdata->irq_cdata.nirqs = PM8921_NR_IRQS;
> + pdata->irq_pdata->irq_cdata.rev = rev;
> + irq_base = pdata->irq_pdata->irq_base;
> + irq_data = pm8xxx_irq_init(pmic->dev, pdata->irq_pdata);
> +
> + if (IS_ERR(irq_data)) {
> + pr_err("Failed to init interrupts ret=%ld\n",
> + PTR_ERR(irq_data));
> + ret = PTR_ERR(irq_data);
> + goto bail;

return PTR_ERR(irq_data);

And then you have
}
pmic->irq_data = irq_data;
return 0;

> + } else
> + pmic->irq_data = irq_data;
> + }
> +
> +bail:
> + return ret;
> +}

> +struct pm_irq_chip {
> + struct list_head link;
> + struct device *dev;
> + spinlock_t pm_irq_lock;
> + u8 *irqs_allowed;
> + u16 *irqs_to_handle;
> + u8 *config;
> + unsigned long *wake_enable;
> + unsigned int devirq;
> + unsigned int count_wakeable;
> + unsigned int irq_base;
> + unsigned int num_irqs;
> + unsigned int num_blocks;
> + unsigned int num_masters;
> +};
> +
> +static LIST_HEAD(pm_irq_chips);
> +
> +/* Helper Functions */
> +static DEFINE_RATELIMIT_STATE(pm8xxx_irq_ratelimit, 60 * HZ, 10);
> +
> +static inline int pm8xxx_can_print(void)
> +{
> + return __ratelimit(&pm8xxx_irq_ratelimit);
> +}
> +
> +static int
> +pm8xxx_read_root_irq(const struct pm_irq_chip *chip, u8 *rp)
> +{
> + return pm8xxx_readb(chip->dev, SSBI_REG_ADDR_IRQ_ROOT, rp);
> +}
> +
> +static int
> +pm8xxx_read_master_irq(const struct pm_irq_chip *chip, u8 m, u8 *bp)
> +{
> + return pm8xxx_readb(chip->dev,
> + SSBI_REG_ADDR_IRQ_M_STATUS1 + m, bp);
> +}
> +
> +static int
> +pm8xxx_read_block_irq(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
> +{
> + int rc;
> +
> + rc = pm8xxx_writeb(chip->dev,
> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
> + if (rc) {
> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
> + goto bail_out;

These goto's are silly. return rc; is fine here.

> + }
> +
> + rc = pm8xxx_readb(chip->dev,
> + SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
> + if (rc)
> + pr_err("Failed Reading Status rc=%d\n", rc);
> +bail_out:
> + return rc;
> +}
> +
> +static int
> +pm8xxx_config_irq(const struct pm_irq_chip *chip, u8 bp, u8 cp)
> +{
> + int rc;
> +
> + rc = pm8xxx_writeb(chip->dev,
> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);

And how are the callers of this function serialized against the other
functions which access SSBI_REG_ADDR_IRQ_BLK_SEL ?

> + if (rc) {
> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
> + goto bail_out;
> + }
> +
> + rc = pm8xxx_writeb(chip->dev,
> + SSBI_REG_ADDR_IRQ_CONFIG, cp);
> + if (rc)
> + pr_err("Failed Configuring IRQ rc=%d\n", rc);
> +bail_out:
> + return rc;
> +}
> +
> +static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip,
> + int block, int *handled)
> +{
> + int ret = 0;
> + u8 bits;
> + int pmirq, irq, k;

Can you please collapse all int variables into one line. Also why are
the iterators in your various functions randomly named i, j, k and
whatever? We usually use i for the first iterator and j when we have a
nested section.

> + spin_lock(&chip->pm_irq_lock);
> + ret = pm8xxx_read_block_irq(chip, block, &bits);
> + if (ret) {
> + if (pm8xxx_can_print())
> + pr_err("Failed reading %d block ret=%d",
> + block, ret);
> + goto out;
> + }

You can drop chip->pm_irq_lock here and return if (!bits)

> + if (!bits) {
> + if (pm8xxx_can_print())
> + pr_err("block bit set in master but no irqs: %d",
> + block);
> + goto out;
> + }
> +
> + /* Check IRQ bits */
> + for (k = 0; k < 8; k++) {
> + if (bits & (1 << k)) {
> + pmirq = block * 8 + k;
> + irq = pmirq + chip->irq_base;
> + chip->irqs_to_handle[*handled] = irq;
> + (*handled)++;

Why all this horrible indirection? Why don't you call
generic_handle_irq() right away?

> + }
> + }
> +out:
> + spin_unlock(&chip->pm_irq_lock);
> + return ret;
> +}
> +
> +static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip,
> + int master, int *handled)
> +{
> + int ret = 0;
> + u8 blockbits;
> + int block_number, j;
> +
> + ret = pm8xxx_read_master_irq(chip, master, &blockbits);
> + if (ret) {
> + pr_err("Failed to read master %d ret=%d\n", master, ret);
> + return ret;
> + }
> + if (!blockbits) {
> + if (pm8xxx_can_print())

What's the point of this ratelimit? This should not happen at all and
if it happens often enough that you need a rate limit then you better
figure out why and fix the real problem instead of papering over it.

> + pr_err("master bit set in root but no blocks: %d",
> + master);
> + return 0;
> + }
> +
> + for (j = 0; j < 8; j++)
> + if (blockbits & (1 << j)) {
> + block_number = master * 8 + j; /* block # */
> + ret |= pm8xxx_irq_block_handler(chip, block_number,
> + handled);
> + }
> + return ret;
> +}
> +
> +static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
> +{
> + struct pm_irq_chip *chip = get_irq_data(irq);
> + int i, ret;
> + u8 root;
> + int masters = 0, handled = 0;
> +
> + ret = pm8xxx_read_root_irq(chip, &root);
> + if (ret) {
> + pr_err("Can't read root status ret=%d\n", ret);
> + return;
> + }
> +
> + /* on pm8xxx series masters start from bit 1 of the root */
> + masters = root >> 1;
> +
> + /* Read allowed masters for blocks. */
> + for (i = 0; i < chip->num_masters; i++)
> + if (masters & (1 << i))
> + pm8xxx_irq_master_handler(chip, i, &handled);
> +
> + for (i = 0; i < handled; i++)
> + generic_handle_irq(chip->irqs_to_handle[i]);
> +
> + desc->chip->ack(irq);

chip->irq_ack()

> +}
> +
> +static void pm8xxx_irq_ack(struct irq_data *d)
> +{
> + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = d->irq - chip->irq_base;
> + u8 block, config;
> +
> + block = pmirq / 8;
> +
> + config = PM_IRQF_WRITE | chip->config[pmirq] | PM_IRQF_CLR;
> + /* Keep the mask */
> + if (!(chip->irqs_allowed[block] & (1 << (pmirq % 8))))
> + config |= PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;

What's the point of this exercise? ack is called before mask and it
should never be called when the interrupt is masked.

> + pm8xxx_config_irq(chip, block, config);
> +}
> +
> +static void pm8xxx_irq_mask(struct irq_data *d)
> +{
> + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = d->irq - chip->irq_base;
> + int master, irq_bit;
> + u8 block, config;
> +
> + block = pmirq / 8;
> + master = block / 8;
> + irq_bit = pmirq % 8;
> +
> + chip->irqs_allowed[block] &= ~(1 << irq_bit);
> +
> + config = PM_IRQF_WRITE | chip->config[pmirq] |
> + PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;

Why don't you define PM_IRQF_MASK as PM_IRQF_MASK_FE | PM_IRQF_MASK_RE
and use this instead of having those line breaks.

Also every function which calls pm8xxx_config_irq() ORs
PM_IRQF_WRITE. Why can't you do that in pm8xxx_config_irq() and only
OR the real relevant bits in the various callers ?

> + pm8xxx_config_irq(chip, block, config);
> +}
> +
> +static void pm8xxx_irq_unmask(struct irq_data *d)
> +{
> + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = d->irq - chip->irq_base;
> + int master, irq_bit;
> + u8 block, config, old_irqs_allowed;
> +
> + block = pmirq / 8;
> + master = block / 8;
> + irq_bit = pmirq % 8;
> +
> + old_irqs_allowed = chip->irqs_allowed[block];

???

> + chip->irqs_allowed[block] |= 1 << irq_bit;
> +
> + config = PM_IRQF_WRITE | chip->config[pmirq];
> + pm8xxx_config_irq(chip, block, config);
> +}
> +
> +static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
> +{
> + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = d->irq - chip->irq_base;
> + int master, irq_bit;
> + u8 block, config;
> +
> + block = pmirq / 8;
> + master = block / 8;
> + irq_bit = pmirq % 8;
> +
> + chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT) |
> + PM_IRQF_MASK_RE | PM_IRQF_MASK_FE;
> + if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
> + if (flow_type & IRQF_TRIGGER_RISING)
> + chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
> + if (flow_type & IRQF_TRIGGER_FALLING)
> + chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
> + } else {
> + chip->config[pmirq] |= PM_IRQF_LVL_SEL;
> +
> + if (flow_type & IRQF_TRIGGER_HIGH)
> + chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
> + else
> + chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
> + }
> +
> + config = PM_IRQF_WRITE
> + | chip->config[pmirq] | PM_IRQF_CLR;

Grrr. These random line breaks all over the place are horrible.

Also please make that:

cfg = chip->config[pmirq] | PM_IRQF_WRITE | PM_IRQF_CLR;

So all the bits which you OR to the stored config are together.

> + return pm8xxx_config_irq(chip, block, config);
> +}
> +
> +static int pm8xxx_irq_set_wake(struct irq_data *d, unsigned int on)
> +{
> + struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> + unsigned int pmirq = d->irq - chip->irq_base;
> +
> + if (on) {
> + set_bit(pmirq, chip->wake_enable);
> + chip->count_wakeable++;
> + } else {
> + clear_bit(pmirq, chip->wake_enable);
> + chip->count_wakeable--;
> + }
> +
> + return 0;
> +}
> +
> +static struct irq_chip pm8xxx_irq_chip = {
> + .name = "pm8xxx",
> + .irq_ack = pm8xxx_irq_ack,
> + .irq_mask = pm8xxx_irq_mask,
> + .irq_unmask = pm8xxx_irq_unmask,
> + .irq_set_type = pm8xxx_irq_set_type,
> + .irq_set_wake = pm8xxx_irq_set_wake,
> +};
> +
> +int pm8xxx_get_irq_stat(void *data, int irq)
> +{
> + struct pm_irq_chip *chip = data;
> + int pmirq;
> + int rc;
> + u8 block, bits, bit;
> + unsigned long flags;
> +
> + if (chip == NULL || irq < chip->irq_base ||
> + irq >= chip->irq_base + chip->num_irqs)
> + return -EINVAL;
> +
> + pmirq = irq - chip->irq_base;
> +
> + block = pmirq / 8;
> + bit = pmirq % 8;
> +
> + spin_lock_irqsave(&chip->pm_irq_lock, flags);
> +
> + rc = pm8xxx_writeb(chip->dev,
> + SSBI_REG_ADDR_IRQ_BLK_SEL, block);
> + if (rc) {
> + pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
> + irq, pmirq, block, rc);
> + goto bail_out;
> + }
> +
> + rc = pm8xxx_readb(chip->dev,
> + SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
> + if (rc) {
> + pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
> + irq, pmirq, block, rc);
> + goto bail_out;
> + }
> +
> + rc = (bits & (1 << bit)) ? 1 : 0;
> +
> +bail_out:
> + spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
> +
> + return rc;
> +}
> +EXPORT_SYMBOL(pm8xxx_get_irq_stat);

EXPORT_SYMBOL_GPL if at all. Why needs this to be exported?

> +
> +#ifdef CONFIG_PM
> +int pm8xxx_suspend_irq(const void *data)
> +{
> + const struct pm_irq_chip *chip = data;
> + int pmirq;
> +
> + for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
> + if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
> + if (!((chip->config[i] & PM_IRQF_MASK_ALL)
> + == PM_IRQF_MASK_ALL)) {
> + irq = i + chip->irq_base;
> + pm8xxx_irq_mask(get_irq_data(irq));
> + }
> + }
> + }
> +
> + if (!chip->count_wakeable)
> + disable_irq(chip->dev->irq);
> +
> + return 0;
> +}
> +
> +void pm8xxx_show_resume_irq(void)
> +{
> + struct pm_irq_chip *chip;
> + u8 block, bits;
> + int pmirq;
> +
> + list_for_each_entry(chip, &pm_irq_chips, link) {
> + for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
> + if (test_bit(pmirq, chip->wake_enable)) {
> + block = pmirq / 8;
> + if (!pm8xxx_read_block_irq(chip,
> + &block, &bits)) {
> + if (bits & (1 << (pmirq & 0x7)))
> + pr_warning("%d triggered\n",
> + pmirq + chip->pdata.irq_base);
> + }
> + }
> + }
> + }
> +}

What's the point of this function?

> +int pm8xxx_resume_irq(const void *data)
> +{
> + const struct pm_irq_chip *chip = data;
> + int pmirq;
> +
> + for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
> + if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
> + if (!((chip->config[i] & PM_IRQF_MASK_ALL)
> + == PM_IRQF_MASK_ALL)) {
> + irq = i + chip->irq_base;
> + pm8xxx_irq_unmask(get_irq_data(irq));
> + }
> + }
> + }
> +
> + if (!chip->count_wakeable)
> + enable_irq(chip->dev->irq);
> +
> + return 0;
> +}
> +#else
> +#define pm8xxx_suspend NULL
> +#define pm8xxx_resume NULL

Where is pm8xxx_suspend/pm8xxx_resume defined for the !PM case and
where are those used at all ?

> +#endif
> +
> +void * __devinit pm8xxx_irq_init(struct device *dev,
> + const struct pm8xxx_irq_platform_data *pdata)
> +{
> + struct pm_irq_chip *chip;
> + int devirq;
> + int rc;
> + unsigned int pmirq;
> +
> + if (!pdata) {
> + pr_err("No platform data\n");
> + return ERR_PTR(-EINVAL);
> + }
> +
> + devirq = pdata->devirq;
> + if (devirq < 0) {
> + pr_err("missing devirq\n");
> + rc = devirq;
> + goto out;
> + }
> +
> + chip = kzalloc(sizeof(struct pm_irq_chip), GFP_KERNEL);
> + if (!chip) {
> + pr_err("Cannot alloc pm_irq_chip struct\n");
> + rc = -ENOMEM;
> + goto out;
> + }
> +
> + chip->dev = dev;
> + chip->devirq = devirq;
> + chip->irq_base = pdata->irq_base;
> + chip->num_irqs = pdata->irq_cdata.nirqs;
> + chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
> + chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
> + spin_lock_init(&chip->pm_irq_lock);
> +
> + chip->irqs_allowed = kzalloc(sizeof(u8) * chip->num_blocks, GFP_KERNEL);
> + if (!chip->irqs_allowed) {
> + pr_err("Cannot alloc irqs_allowed array\n");
> + rc = -ENOMEM;
> + goto free_pm_irq_chip;
> + }
> +
> + chip->irqs_to_handle = kzalloc(sizeof(u16) * chip->num_irqs,
> + GFP_KERNEL);
> + if (!chip->irqs_to_handle) {
> + pr_err("Cannot alloc irqs_to_handle array\n");
> + rc = -ENOMEM;
> + goto free_irqs_allowed;
> + }
> + chip->config = kzalloc(sizeof(u8) * chip->num_irqs, GFP_KERNEL);
> + if (!chip->config) {
> + pr_err("Cannot alloc config array\n");
> + rc = -ENOMEM;
> + goto free_irqs_to_handle;
> + }
> + chip->wake_enable = kzalloc(sizeof(unsigned long)
> + * DIV_ROUND_UP(chip->num_irqs, BITS_PER_LONG),
> + GFP_KERNEL);
> + if (!chip->wake_enable) {
> + pr_err("Cannot alloc wake_enable array\n");
> + rc = -ENOMEM;
> + goto free_config;
> + }
> + list_add(&chip->link, &pm_irq_chips);

What's that list for and how is it protected ?

> + for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
> + set_irq_chip(chip->irq_base + pmirq, &pm8xxx_irq_chip);
> + set_irq_chip_data(chip->irq_base + pmirq, chip);
> + set_irq_handler(chip->irq_base + pmirq, handle_level_irq);
> +#ifdef CONFIG_ARM
> + set_irq_flags(chip->irq_base + pmirq, IRQF_VALID);
> +#else
> + set_irq_noprobe(chip->irq_base + pmirq);
> +#endif
> + }
> +
> + set_irq_type(devirq, pdata->irq_trigger_flag);
> + set_irq_data(devirq, chip);
> + set_irq_chained_handler(devirq, pm8xxx_irq_handler);
> + set_irq_wake(devirq, 1);
> +
> + return chip;
> +
> +free_config:
> + kfree(chip->config);
> +free_irqs_to_handle:
> + kfree(chip->irqs_to_handle);
> +free_irqs_allowed:
> + kfree(chip->irqs_allowed);

No need for 3 separate labels. You kzalloc() chip, so you can call
kfree() on chip->xxx unconditionally.

> +free_pm_irq_chip:
> + kfree(chip);
> +out:
> + return ERR_PTR(rc);
> +}

> +#ifdef CONFIG_MFD_PM8XXX_IRQ
> +/**
> + * pm8xxx_get_irq_stat - get the status of the irq line
> + * @dev: the interrupt device
> + * @irq: the irq number
> + *
> + * The pm8xxx gpio and mpp rely on the interrupt block to read
> + * the values on their pins. This function is to facilitate reading
> + * the status of a gpio or an mpp line. The caller has to convert the
> + * gpio number to irq number.
> + *
> + * RETURNS:
> + * an int indicating the value read on that line
> + */

Please move that comment into the implementation.

> +int pm8xxx_get_irq_stat(void *data, int irq);

Thanks,

tglx

2011-03-08 17:59:03

by Randy Dunlap

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 1/6] mfd: pm8921: Add PMIC 8921 core driver

On Mon, 7 Mar 2011 22:09:45 -0800 [email protected] wrote:

> From: Abhijeet Dharmapurikar <[email protected]>
>
> Add support for the Qualcomm PM8921 PMIC chip. The core driver
> will communicate with the PMIC chip via the MSM SSBI bus.
>
>
> Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
> ---
> drivers/mfd/Kconfig | 18 +++++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/pm8921-core.c | 157 +++++++++++++++++++++++++++++++++++++++
> include/linux/mfd/pm8921.h | 26 +++++++
> include/linux/mfd/pm8xxx/core.h | 66 ++++++++++++++++
> 5 files changed, 268 insertions(+), 0 deletions(-)
> create mode 100644 drivers/mfd/pm8921-core.c
> create mode 100644 include/linux/mfd/pm8921.h
> create mode 100644 include/linux/mfd/pm8xxx/core.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index fd01836..46f0d2f 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -624,6 +624,24 @@ config MFD_WL1273_CORE
> driver connects the radio-wl1273 V4L2 module and the wl1273
> audio codec.
>
> +config MFD_PM8XXX
> + tristate
> +
> +config MFD_PM8921_CORE
> + tristate "Qualcomm PM8921 PMIC chip"
> + depends on MSM_SSBI
> + select MFD_CORE
> + select MFD_PM8XXX
> + help
> + If you say yes to this option, support will be included for the
> + built-in PM8921 PMIC chip

end sentence with period, please.

> +
> + This is required if your board has a PM8921 and uses its features,
> + such as: MPPs, GPIOs, regulators, interrupts, and PWM.
> +
> + Say M here if you want to include support for PM8921 chip as a module.
> + This will build a module called "pm8921-core.ko".

Drop the ".ko". We (usually) don't spell that out since "modprobe pm8921-core"
works.

> +
> endif # MFD_SUPPORT
>
> menu "Multimedia Capabilities Port drivers"

---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***

2011-03-08 23:30:37

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 4/6] mfd: pm8xxx-mpp: Add pm8xxx MPP driver

On Mon, Mar 07, 2011 at 10:09:48PM -0800, [email protected] wrote:

> + mpp_chip->gpio_chip.label = PM8XXX_MPP_DEV_NAME;
> + mpp_chip->gpio_chip.direction_input = pm8xxx_mpp_dir_input;
> + mpp_chip->gpio_chip.direction_output = pm8xxx_mpp_dir_output;
> + mpp_chip->gpio_chip.to_irq = pm8xxx_mpp_to_irq;
> + mpp_chip->gpio_chip.get = pm8xxx_mpp_get;
> + mpp_chip->gpio_chip.set = pm8xxx_mpp_set;
> + mpp_chip->gpio_chip.dbg_show = pm8xxx_mpp_dbg_show;
> + mpp_chip->gpio_chip.ngpio = pdata->core_data.nmpps;
> + mpp_chip->gpio_chip.can_sleep = 1;
> + mpp_chip->gpio_chip.dev = &pdev->dev;
> + mpp_chip->gpio_chip.base = pdata->mpp_base;

It's seems really odd that you're adding gpiolib stuff here when you've
also got a separate gpiolib driver. Possibly this all shouldn't
actually be split up as much as it is - there's also the issue with the
gpiolib driver needing to peer into the interrupt controller. It might
simplify the code if things were merged more.

2011-03-08 23:31:06

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 5/6] MAINTAINERS: Add patterns for pmic 8921 files to MSM subsystem

On Mon, Mar 07, 2011 at 10:09:49PM -0800, [email protected] wrote:

> +F: include/linux/mfd/pm8???.h
> +F: include/linux/mfd/pm8xxx/

Shouldn't the pm8???.h files be in the directory?

2011-03-09 05:21:15

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

Thomas Gleixner wrote:
> On Mon, 7 Mar 2011, [email protected] wrote:
>> +static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
>> + *pdata,
>> + struct pm8921 *pmic,
>> + u32 rev)
>> +{
>> + int ret = 0;
>> + int irq_base = 0;
>> + void *irq_data;
>> +
>> + if (pdata->irq_pdata) {
>
> So if pdata->irq_pdata == NULL you return success. Is that correct ?

Yes. The board configuration may choose not to use pmic interrupts.

> Also please return early on (!pdata->irq_pdata) and avoid that extra
> indent level for the real code path.

I did not do that because there are other subdevices that I will be
adding in the later patches. I cannot return early. well I will change
it for this patch.

>
>> + pdata->irq_pdata->irq_cdata.nirqs = PM8921_NR_IRQS;
>> + pdata->irq_pdata->irq_cdata.rev = rev;
>> + irq_base = pdata->irq_pdata->irq_base;
>> + irq_data = pm8xxx_irq_init(pmic->dev, pdata->irq_pdata);
>> +
>> + if (IS_ERR(irq_data)) {
>> + pr_err("Failed to init interrupts ret=%ld\n",
>> + PTR_ERR(irq_data));
>> + ret = PTR_ERR(irq_data);
>> + goto bail;
>
> return PTR_ERR(irq_data);
>
> And then you have
> }
> pmic->irq_data = irq_data;
> return 0;
>
>> + } else
>> + pmic->irq_data = irq_data;
>> + }
>> +
>> +bail:
>> + return ret;
>> +}
Ok will do it in the next patchset.
>
>
>> +static int
>> +pm8xxx_read_block_irq(const struct pm_irq_chip *chip, u8 bp, u8 *ip)
>> +{
>> + int rc;
>> +
>> + rc = pm8xxx_writeb(chip->dev,
>> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
>> + if (rc) {
>> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
>> + goto bail_out;
>
> These goto's are silly. return rc; is fine here.

Sure, now that I realize SSBI_REG_ADDR_IRQ_BLK_SEL would need
protection. Will add locking
>

>> +static int
>> +pm8xxx_config_irq(const struct pm_irq_chip *chip, u8 bp, u8 cp)
>> +{
>> + int rc;
>> +
>> + rc = pm8xxx_writeb(chip->dev,
>> + SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
>
> And how are the callers of this function serialized against the other
> functions which access SSBI_REG_ADDR_IRQ_BLK_SEL ?

Thanks for pointing this out, will add locks around these.
>
>> + if (rc) {
>> + pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
>> + goto bail_out;
>> + }
>> +
>> + rc = pm8xxx_writeb(chip->dev,
>> + SSBI_REG_ADDR_IRQ_CONFIG, cp);
>> + if (rc)
>> + pr_err("Failed Configuring IRQ rc=%d\n", rc);
>> +bail_out:
>> + return rc;
>> +}
>> +
>> +static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip,
>> + int block, int *handled)
>> +{
>> + int ret = 0;
>> + u8 bits;
>> + int pmirq, irq, k;
>
> Can you please collapse all int variables into one line. Also why are
> the iterators in your various functions randomly named i, j, k and
> whatever? We usually use i for the first iterator and j when we have a
> nested section.
Ok will clean this up.

>
>> + spin_lock(&chip->pm_irq_lock);
>> + ret = pm8xxx_read_block_irq(chip, block, &bits);
>> + if (ret) {
>> + if (pm8xxx_can_print())
>> + pr_err("Failed reading %d block ret=%d",
>> + block, ret);
>> + goto out;
>> + }
>
> You can drop chip->pm_irq_lock here and return if (!bits)
>
>> + if (!bits) {
>> + if (pm8xxx_can_print())
>> + pr_err("block bit set in master but no irqs: %d",
>> + block);
>> + goto out;
>> + }
>> +
>> + /* Check IRQ bits */
>> + for (k = 0; k < 8; k++) {
>> + if (bits & (1 << k)) {
>> + pmirq = block * 8 + k;
>> + irq = pmirq + chip->irq_base;
>> + chip->irqs_to_handle[*handled] = irq;
>> + (*handled)++;
>
> Why all this horrible indirection? Why don't you call
> generic_handle_irq() right away?

Will change it to call generic_handle_irq() right here.
>
>> + }
>> + }
>> +out:
>> + spin_unlock(&chip->pm_irq_lock);
>> + return ret;
>> +}
>> +
>> +static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip,
>> + int master, int *handled)
>> +{
>> + int ret = 0;
>> + u8 blockbits;
>> + int block_number, j;
>> +
>> + ret = pm8xxx_read_master_irq(chip, master, &blockbits);
>> + if (ret) {
>> + pr_err("Failed to read master %d ret=%d\n", master, ret);
>> + return ret;
>> + }
>> + if (!blockbits) {
>> + if (pm8xxx_can_print())
>
> What's the point of this ratelimit? This should not happen at all and
> if it happens often enough that you need a rate limit then you better
> figure out why and fix the real problem instead of papering over it.

There is no issue, we had one bringup where we got a lot of spurious
interrupts and these are remains from the debug code we added in. Will
clean it up.

>
>> + pr_err("master bit set in root but no blocks: %d",
>> + master);
>> + return 0;
>> + }
>> +
>> + for (j = 0; j < 8; j++)
>> + if (blockbits & (1 << j)) {
>> + block_number = master * 8 + j; /* block # */
>> + ret |= pm8xxx_irq_block_handler(chip, block_number,
>> + handled);
>> + }
>> + return ret;
>> +}
>> +
>> +static void pm8xxx_irq_handler(unsigned int irq, struct irq_desc *desc)
>> +{
>> + struct pm_irq_chip *chip = get_irq_data(irq);
>> + int i, ret;
>> + u8 root;
>> + int masters = 0, handled = 0;
>> +
>> + ret = pm8xxx_read_root_irq(chip, &root);
>> + if (ret) {
>> + pr_err("Can't read root status ret=%d\n", ret);
>> + return;
>> + }
>> +
>> + /* on pm8xxx series masters start from bit 1 of the root */
>> + masters = root >> 1;
>> +
>> + /* Read allowed masters for blocks. */
>> + for (i = 0; i < chip->num_masters; i++)
>> + if (masters & (1 << i))
>> + pm8xxx_irq_master_handler(chip, i, &handled);
>> +
>> + for (i = 0; i < handled; i++)
>> + generic_handle_irq(chip->irqs_to_handle[i]);
>> +
>> + desc->chip->ack(irq);
>
> chip->irq_ack()

Yes will do.

>
>> +}
>> +
>> +static void pm8xxx_irq_ack(struct irq_data *d)
>> +{
>> + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
>> + unsigned int pmirq = d->irq - chip->irq_base;
>> + u8 block, config;
>> +
>> + block = pmirq / 8;
>> +
>> + config = PM_IRQF_WRITE | chip->config[pmirq] | PM_IRQF_CLR;
>> + /* Keep the mask */
>> + if (!(chip->irqs_allowed[block] & (1 << (pmirq % 8))))
>> + config |= PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
>
> What's the point of this exercise? ack is called before mask and it

The register design is such that we cannot only clear the interrupt. One
has to write to the trigger bits while clearing it. Now trigger bits
define whether the interrupt is masked or unmasked. If unmasked they
define whether the interrupt rising/falling/level high/level low triggered.
So the code remembers which interrupts are masked and for them it clears
and rewrite the masked status in trigger bits. For unmasked ones it
clears and writes to the trigger bits essentially configuring them same
way as it was before. That is why the if satement to check interrupt was
masked earlier, chip->irqs_allowed[] maintains which interrupt are unmasked.

> ack is called before mask and it
> should never be called when the interrupt is masked.

I didnt quite understand this comment. handle_level_irq calls mask_ack
which masks the interrupt and then acks it. In this case the ack is
called after the mask. Moreover, handle_edge_irq calls only ack and the
interrupt stays unmasked. I dont see ack is always associated with a
mask or any ordering is enforced between them. Please clarify.

>> + config = PM_IRQF_WRITE | chip->config[pmirq] |
>> + PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
>
> Why don't you define PM_IRQF_MASK as PM_IRQF_MASK_FE | PM_IRQF_MASK_RE
> and use this instead of having those line breaks.
Ok will do that.
>
> Also every function which calls pm8xxx_config_irq() ORs
> PM_IRQF_WRITE. Why can't you do that in pm8xxx_config_irq() and only
> OR the real relevant bits in the various callers ?

Ok will do that.

>> +
>> + old_irqs_allowed = chip->irqs_allowed[block];
>
> ???

will remove, some debug code remnants.
>
>> + }
>> +
>> + config = PM_IRQF_WRITE
>> + | chip->config[pmirq] | PM_IRQF_CLR;
>
> Grrr. These random line breaks all over the place are horrible.
>
> Also please make that:
>
> cfg = chip->config[pmirq] | PM_IRQF_WRITE | PM_IRQF_CLR;
>
> So all the bits which you OR to the stored config are together.

Yes I tend to order them the way they show up in the register
definitions. Agree it is not readable, will fix it.

>> +int pm8xxx_get_irq_stat(void *data, int irq)
>> +{
>> + struct pm_irq_chip *chip = data;
>> + int pmirq;
>> + int rc;
>> + u8 block, bits, bit;
>> + unsigned long flags;
>> +
>> + if (chip == NULL || irq < chip->irq_base ||
>> + irq >= chip->irq_base + chip->num_irqs)
>> + return -EINVAL;
>> +
>> + pmirq = irq - chip->irq_base;
>> +
>> + block = pmirq / 8;
>> + bit = pmirq % 8;
>> +
>> + spin_lock_irqsave(&chip->pm_irq_lock, flags);
>> +
>> + rc = pm8xxx_writeb(chip->dev,
>> + SSBI_REG_ADDR_IRQ_BLK_SEL, block);
>> + if (rc) {
>> + pr_err("Failed Selecting block irq=%d pmirq=%d blk=%d rc=%d\n",
>> + irq, pmirq, block, rc);
>> + goto bail_out;
>> + }
>> +
>> + rc = pm8xxx_readb(chip->dev,
>> + SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
>> + if (rc) {
>> + pr_err("Failed Configuring irq=%d pmirq=%d blk=%d rc=%d\n",
>> + irq, pmirq, block, rc);
>> + goto bail_out;
>> + }
>> +
>> + rc = (bits & (1 << bit)) ? 1 : 0;
>> +
>> +bail_out:
>> + spin_unlock_irqrestore(&chip->pm_irq_lock, flags);
>> +
>> + return rc;
>> +}
>> +EXPORT_SYMBOL(pm8xxx_get_irq_stat);
>
> EXPORT_SYMBOL_GPL if at all. Why needs this to be exported?

The core driver calls this to read the status on a gpio/mpp line. The
core driver can be compiled as a module, hence the export. Will use
EXPORT_SYMBOL_GPL instead. I realize there are few more functions as
well that need exporting, will export them in the coming patch.
>
>> +
>> +
>> +void pm8xxx_show_resume_irq(void)
>> +{
>> + struct pm_irq_chip *chip;
>> + u8 block, bits;
>> + int pmirq;
>> +
>> + list_for_each_entry(chip, &pm_irq_chips, link) {
>> + for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
>> + if (test_bit(pmirq, chip->wake_enable)) {
>> + block = pmirq / 8;
>> + if (!pm8xxx_read_block_irq(chip,
>> + &block, &bits)) {
>> + if (bits & (1 << (pmirq & 0x7)))
>> + pr_warning("%d triggered\n",
>> + pmirq + chip->pdata.irq_base);
>> + }
>> + }
>> + }
>> + }
>> +}
>
> What's the point of this function?
This function is used by the power management code right before it
returns from suspend_ops->enter. It helps in debugging what exact
interrupts triggered the resume.

>
>> +int pm8xxx_resume_irq(const void *data)
>> +{
>> + const struct pm_irq_chip *chip = data;
>> + int pmirq;
>> +
>> + for (pmirq = 0; pmirq < chip->num_irqs; pmirq++) {
>> + if (chip->config[i] && !test_bit(i, chip->wake_enable)) {
>> + if (!((chip->config[i] & PM_IRQF_MASK_ALL)
>> + == PM_IRQF_MASK_ALL)) {
>> + irq = i + chip->irq_base;
>> + pm8xxx_irq_unmask(get_irq_data(irq));
>> + }
>> + }
>> + }
>> +
>> + if (!chip->count_wakeable)
>> + enable_irq(chip->dev->irq);
>> +
>> + return 0;
>> +}
>> +#else
>> +#define pm8xxx_suspend NULL
>> +#define pm8xxx_resume NULL
>
> Where is pm8xxx_suspend/pm8xxx_resume defined for the !PM case and
> where are those used at all ?

The core driver calls them (these need to be export_symbol_gpled as
well). I should provide empty implementations rather than NULL
definitions. Will fix them.
>
>> +#endif
>> +
>> +void * __devinit pm8xxx_irq_init(struct device *dev,
>> + const struct pm8xxx_irq_platform_data *pdata)
>> +{
>> + struct pm_irq_chip *chip;
>> + int devirq;
>> + int rc;
>> + unsigned int pmirq;
>> +
>> + if (!pdata) {
>> + pr_err("No platform data\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + devirq = pdata->devirq;
>> + if (devirq < 0) {
>> + pr_err("missing devirq\n");
>> + rc = devirq;
>> + goto out;
>> + }
>> +
>> + chip = kzalloc(sizeof(struct pm_irq_chip), GFP_KERNEL);
>> + if (!chip) {
>> + pr_err("Cannot alloc pm_irq_chip struct\n");
>> + rc = -ENOMEM;
>> + goto out;
>> + }
>> +
>> + chip->dev = dev;
>> + chip->devirq = devirq;
>> + chip->irq_base = pdata->irq_base;
>> + chip->num_irqs = pdata->irq_cdata.nirqs;
>> + chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
>> + chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
>> + spin_lock_init(&chip->pm_irq_lock);
>> +
>> + chip->irqs_allowed = kzalloc(sizeof(u8) * chip->num_blocks, GFP_KERNEL);
>> + if (!chip->irqs_allowed) {
>> + pr_err("Cannot alloc irqs_allowed array\n");
>> + rc = -ENOMEM;
>> + goto free_pm_irq_chip;
>> + }
>> +
>> + chip->irqs_to_handle = kzalloc(sizeof(u16) * chip->num_irqs,
>> + GFP_KERNEL);
>> + if (!chip->irqs_to_handle) {
>> + pr_err("Cannot alloc irqs_to_handle array\n");
>> + rc = -ENOMEM;
>> + goto free_irqs_allowed;
>> + }
>> + chip->config = kzalloc(sizeof(u8) * chip->num_irqs, GFP_KERNEL);
>> + if (!chip->config) {
>> + pr_err("Cannot alloc config array\n");
>> + rc = -ENOMEM;
>> + goto free_irqs_to_handle;
>> + }
>> + chip->wake_enable = kzalloc(sizeof(unsigned long)
>> + * DIV_ROUND_UP(chip->num_irqs, BITS_PER_LONG),
>> + GFP_KERNEL);
>> + if (!chip->wake_enable) {
>> + pr_err("Cannot alloc wake_enable array\n");
>> + rc = -ENOMEM;
>> + goto free_config;
>> + }
>> + list_add(&chip->link, &pm_irq_chips);
>
> What's that list for and how is it protected ?
The list is used in pm8xxx_show_resume_irq function to go over all he
chips and see what interrupts have triggered.

I think I will clean up the printing of resume interrupts and will
submit them as a separate patch along with the power management code.
This list and pm8xxx_show_resume_irq goes.

>> +
>> +free_config:
>> + kfree(chip->config);
>> +free_irqs_to_handle:
>> + kfree(chip->irqs_to_handle);
>> +free_irqs_allowed:
>> + kfree(chip->irqs_allowed);
>
> No need for 3 separate labels. You kzalloc() chip, so you can call
> kfree() on chip->xxx unconditionally.

ok, will do.

>
>> +free_pm_irq_chip:
>> + kfree(chip);
>> +out:
>> + return ERR_PTR(rc);
>> +}
>
>> +#ifdef CONFIG_MFD_PM8XXX_IRQ
>> +/**
>> + * pm8xxx_get_irq_stat - get the status of the irq line
>> + * @dev: the interrupt device
>> + * @irq: the irq number
>> + *
>> + * The pm8xxx gpio and mpp rely on the interrupt block to read
>> + * the values on their pins. This function is to facilitate reading
>> + * the status of a gpio or an mpp line. The caller has to convert the
>> + * gpio number to irq number.
>> + *
>> + * RETURNS:
>> + * an int indicating the value read on that line
>> + */
>
> Please move that comment into the implementation.

Will do.

>
>> +int pm8xxx_get_irq_stat(void *data, int irq);
>
> Thanks,
>
> tglx

--
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-10 03:36:19

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 4/6] mfd: pm8xxx-mpp: Add pm8xxx MPP driver

Mark Brown wrote:
> On Mon, Mar 07, 2011 at 10:09:48PM -0800, [email protected] wrote:
>
>> + mpp_chip->gpio_chip.label = PM8XXX_MPP_DEV_NAME;
>> + mpp_chip->gpio_chip.direction_input = pm8xxx_mpp_dir_input;
>> + mpp_chip->gpio_chip.direction_output = pm8xxx_mpp_dir_output;
>> + mpp_chip->gpio_chip.to_irq = pm8xxx_mpp_to_irq;
>> + mpp_chip->gpio_chip.get = pm8xxx_mpp_get;
>> + mpp_chip->gpio_chip.set = pm8xxx_mpp_set;
>> + mpp_chip->gpio_chip.dbg_show = pm8xxx_mpp_dbg_show;
>> + mpp_chip->gpio_chip.ngpio = pdata->core_data.nmpps;
>> + mpp_chip->gpio_chip.can_sleep = 1;
>> + mpp_chip->gpio_chip.dev = &pdev->dev;
>> + mpp_chip->gpio_chip.base = pdata->mpp_base;
>
> It's seems really odd that you're adding gpiolib stuff here when you've
> also got a separate gpiolib driver. Possibly this all shouldn't
> actually be split up as much as it is - there's also the issue with the
> gpiolib driver needing to peer into the interrupt controller. It might
> simplify the code if things were merged more.

I dont think merging code will help here. gpio lines and mpp lines are
very different piece of hardware,they have a different register map and
different config attributes. They do fall under the generic 'gpiolib'
umbrella, but it seems clean to keep them separate.

I agree with you that gpio code needs to call on interrupt controller (
a complicated hardware design) but I think I have a clean software
implementation to manage it.

--
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-10 03:57:11

by Trilok Soni

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 4/6] mfd: pm8xxx-mpp: Add pm8xxx MPP driver

Hi Abhi,

On 3/10/2011 9:06 AM, Abhijeet Dharmapurikar wrote:
> Mark Brown wrote:
>> On Mon, Mar 07, 2011 at 10:09:48PM -0800, [email protected] wrote:
>>
>>> + mpp_chip->gpio_chip.label = PM8XXX_MPP_DEV_NAME;
>>> + mpp_chip->gpio_chip.direction_input = pm8xxx_mpp_dir_input;
>>> + mpp_chip->gpio_chip.direction_output = pm8xxx_mpp_dir_output;
>>> + mpp_chip->gpio_chip.to_irq = pm8xxx_mpp_to_irq;
>>> + mpp_chip->gpio_chip.get = pm8xxx_mpp_get;
>>> + mpp_chip->gpio_chip.set = pm8xxx_mpp_set;
>>> + mpp_chip->gpio_chip.dbg_show = pm8xxx_mpp_dbg_show;
>>> + mpp_chip->gpio_chip.ngpio = pdata->core_data.nmpps;
>>> + mpp_chip->gpio_chip.can_sleep = 1;
>>> + mpp_chip->gpio_chip.dev = &pdev->dev;
>>> + mpp_chip->gpio_chip.base = pdata->mpp_base;
>>
>> It's seems really odd that you're adding gpiolib stuff here when you've
>> also got a separate gpiolib driver. Possibly this all shouldn't
>> actually be split up as much as it is - there's also the issue with the
>> gpiolib driver needing to peer into the interrupt controller. It might
>> simplify the code if things were merged more.
>
> I dont think merging code will help here. gpio lines and mpp lines are very different piece of hardware,they have a different register map and different config attributes. They do fall under the generic 'gpiolib' umbrella, but it seems clean to keep them separate.
>
> I agree with you that gpio code needs to call on interrupt controller ( a complicated hardware design) but I think I have a clean software implementation to manage it.
>

It would be good to add that MPP do have more functionality than normal GPIO. So, I expect that in future
we might have few exported APIs beyond gpiolib integration.

---Trilok Soni

--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-10 10:32:57

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Tue, 8 Mar 2011, Abhijeet Dharmapurikar wrote:
> Thomas Gleixner wrote:
> > On Mon, 7 Mar 2011, [email protected] wrote:
> > > + if (pdata->irq_pdata) {
> >
> > So if pdata->irq_pdata == NULL you return success. Is that correct ?
>
> Yes. The board configuration may choose not to use pmic interrupts.

Ok.

> > Also please return early on (!pdata->irq_pdata) and avoid that extra
> > indent level for the real code path.
>
> I did not do that because there are other subdevices that I will be adding in
> the later patches. I cannot return early. well I will change it for this
> patch.

Maybe splitting out the various init subsections into different
functions which are called from here might be a good thing.

> > > +static void pm8xxx_irq_ack(struct irq_data *d)
> > > +{
> > > + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
> > > + unsigned int pmirq = d->irq - chip->irq_base;
> > > + u8 block, config;
> > > +
> > > + block = pmirq / 8;
> > > +
> > > + config = PM_IRQF_WRITE | chip->config[pmirq] | PM_IRQF_CLR;
> > > + /* Keep the mask */
> > > + if (!(chip->irqs_allowed[block] & (1 << (pmirq % 8))))
> > > + config |= PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
> >
> > What's the point of this exercise? ack is called before mask and it
>
> The register design is such that we cannot only clear the interrupt. One has
> to write to the trigger bits while clearing it. Now trigger bits define
> whether the interrupt is masked or unmasked. If unmasked they define whether
> the interrupt rising/falling/level high/level low triggered.
> So the code remembers which interrupts are masked and for them it clears and
> rewrite the masked status in trigger bits. For unmasked ones it clears and
> writes to the trigger bits essentially configuring them same way as it was
> before. That is why the if satement to check interrupt was masked earlier,
> chip->irqs_allowed[] maintains which interrupt are unmasked.
>
> > ack is called before mask and it
> > should never be called when the interrupt is masked.
>
> I didnt quite understand this comment. handle_level_irq calls mask_ack which
> masks the interrupt and then acks it. In this case the ack is called after the

Indeed, sorry. So the right way to deal with that is to provide a
mask_ack() callback which does it in the correct order for your
HW. That way you avoid all the local state storage.

Thanks,

tglx

2011-03-10 15:14:27

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 4/6] mfd: pm8xxx-mpp: Add pm8xxx MPP driver

On Wed, Mar 09, 2011 at 07:36:16PM -0800, Abhijeet Dharmapurikar wrote:
> Mark Brown wrote:

>> It's seems really odd that you're adding gpiolib stuff here when you've
>> also got a separate gpiolib driver. Possibly this all shouldn't
>> actually be split up as much as it is - there's also the issue with the
>> gpiolib driver needing to peer into the interrupt controller. It might
>> simplify the code if things were merged more.

> I dont think merging code will help here. gpio lines and mpp lines are
> very different piece of hardware,they have a different register map and
> different config attributes. They do fall under the generic 'gpiolib'
> umbrella, but it seems clean to keep them separate.

Oh, so the MFPs are completely separate pins to the GPIOs controlled by
the GPIO driver? That's unusual - might be worth clarifying that
somehow.

2011-03-11 04:43:24

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

Thomas Gleixner wrote:
> On Tue, 8 Mar 2011, Abhijeet Dharmapurikar wrote:
>> Thomas Gleixner wrote:
>>> On Mon, 7 Mar 2011, [email protected] wrote:
>>>> + if (pdata->irq_pdata) {
>>> So if pdata->irq_pdata == NULL you return success. Is that correct ?
>> Yes. The board configuration may choose not to use pmic interrupts.
>
> Ok.
>
>>> Also please return early on (!pdata->irq_pdata) and avoid that extra
>>> indent level for the real code path.
>> I did not do that because there are other subdevices that I will be adding in
>> the later patches. I cannot return early. well I will change it for this
>> patch.
>
> Maybe splitting out the various init subsections into different
> functions which are called from here might be a good thing.
>
>>>> +static void pm8xxx_irq_ack(struct irq_data *d)
>>>> +{
>>>> + const struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
>>>> + unsigned int pmirq = d->irq - chip->irq_base;
>>>> + u8 block, config;
>>>> +
>>>> + block = pmirq / 8;
>>>> +
>>>> + config = PM_IRQF_WRITE | chip->config[pmirq] | PM_IRQF_CLR;
>>>> + /* Keep the mask */
>>>> + if (!(chip->irqs_allowed[block] & (1 << (pmirq % 8))))
>>>> + config |= PM_IRQF_MASK_FE | PM_IRQF_MASK_RE;
>>> What's the point of this exercise? ack is called before mask and it
>> The register design is such that we cannot only clear the interrupt. One has
>> to write to the trigger bits while clearing it. Now trigger bits define
>> whether the interrupt is masked or unmasked. If unmasked they define whether
>> the interrupt rising/falling/level high/level low triggered.
>> So the code remembers which interrupts are masked and for them it clears and
>> rewrite the masked status in trigger bits. For unmasked ones it clears and
>> writes to the trigger bits essentially configuring them same way as it was
>> before. That is why the if satement to check interrupt was masked earlier,
>> chip->irqs_allowed[] maintains which interrupt are unmasked.
>>
>>> ack is called before mask and it
>>> should never be called when the interrupt is masked.
>> I didnt quite understand this comment. handle_level_irq calls mask_ack which
>> masks the interrupt and then acks it. In this case the ack is called after the
>
> Indeed, sorry. So the right way to deal with that is to provide a
> mask_ack() callback which does it in the correct order for your
> HW. That way you avoid all the local state storage.

Yes however while updating the code I noticed that I would need to keep
account of all the interrupts enabled and all the interrupts marked
wakeup. This aids in switching to the wakeup set in the suspend callback
and the enabled set in the resume callback. I will update the resume
callback to enable the interrupts in irqs_allowed(the local state
storage) in the next patch (my current patch does not do that).

IOW I need to keep the local state storage.

>
> Thanks,
>
> tglx

--
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-11 17:58:27

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Thu, 10 Mar 2011, Abhijeet Dharmapurikar wrote:
> Thomas Gleixner wrote:
> > On Tue, 8 Mar 2011, Abhijeet Dharmapurikar wrote:
> > > > ack is called before mask and it
> > > > should never be called when the interrupt is masked.
> > > I didnt quite understand this comment. handle_level_irq calls mask_ack
> > > which
> > > masks the interrupt and then acks it. In this case the ack is called after
> > > the
> >
> > Indeed, sorry. So the right way to deal with that is to provide a
> > mask_ack() callback which does it in the correct order for your
> > HW. That way you avoid all the local state storage.
>
>
> Yes however while updating the code I noticed that I would need to keep
> account of all the interrupts enabled and all the interrupts marked wakeup.
> This aids in switching to the wakeup set in the suspend callback and the
> enabled set in the resume callback. I will update the resume callback to
> enable the interrupts in irqs_allowed(the local state storage) in the next
> patch (my current patch does not do that).
>
> IOW I need to keep the local state storage.

Wrong. The interrupts are disabled and reenabled by the core code and
not by some extra suspend/resume callbacks in your driver. The core
checks those marked as IRQ_WAKE, the wake callback to the irq chip is
only there if you need to set up some hardware register in order to
make the wake functionality work. So again, you don't need local state
as the core tracks the state for you.

Thanks,

tglx

2011-03-11 19:02:19

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

>> Yes however while updating the code I noticed that I would need to keep
>> account of all the interrupts enabled and all the interrupts marked wakeup.
>> This aids in switching to the wakeup set in the suspend callback and the
>> enabled set in the resume callback. I will update the resume callback to
>> enable the interrupts in irqs_allowed(the local state storage) in the next
>> patch (my current patch does not do that).
>>
>> IOW I need to keep the local state storage.
>
> Wrong. The interrupts are disabled and reenabled by the core code and
> not by some extra suspend/resume callbacks in your driver. The core
> checks those marked as IRQ_WAKE, the wake callback to the irq chip is
> only there if you need to set up some hardware register in order to
> make the wake functionality work. So again, you don't need local state
> as the core tracks the state for you.

Help me understand this, the core code calls disable on all the
interrupts while going to suspend. Notice that I have no disable
callback, which means those interrupts remain unmasked.

I could have a situation, when the system(a mobile phone) goes to
suspend we dont want to wake it up because of unnecessary interrupts. A
good example is, we want to wakeup the phone if the battery goes low,
but dont want to wake it up if an acceleromter interrupt triggers. The
drivers respectively mark the battery low interrupt as wakeup and the
accelerometer interrupt as a non-wake up interrupt. Assume both of them
are edge triggered interrupts.

The genirq code does not mask the interrupt while going to suspend, it
only calls disable(), which I understand should not mask the interrupt
for check_wakeup_irqs() to work.

If I don't mask that accelerometer interrupts in the interrupt
controller's suspend() the phone will wakeup every time the user moves
around, draining the battery unnecessarily.

One might say that the accelerometer should be deactivated in the
suspend callback of the accelerometer driver. Yes this can be done and
we will not see an interrupt while suspended. However not all hardware
can be deactivated like that. There are some devices which simply
interrupt and the only way to keep from waking up is masking their
interrupts.

How do you suggest I mask the accelerometer interrupt?

Abhijeet
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-11 19:44:12

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Fri, 11 Mar 2011, Abhijeet Dharmapurikar wrote:
> > > Yes however while updating the code I noticed that I would need to keep
> > > account of all the interrupts enabled and all the interrupts marked
> > > wakeup.
> > > This aids in switching to the wakeup set in the suspend callback and the
> > > enabled set in the resume callback. I will update the resume callback to
> > > enable the interrupts in irqs_allowed(the local state storage) in the next
> > > patch (my current patch does not do that).
> > >
> > > IOW I need to keep the local state storage.
> >
> > Wrong. The interrupts are disabled and reenabled by the core code and
> > not by some extra suspend/resume callbacks in your driver. The core
> > checks those marked as IRQ_WAKE, the wake callback to the irq chip is
> > only there if you need to set up some hardware register in order to
> > make the wake functionality work. So again, you don't need local state
> > as the core tracks the state for you.
>
> Help me understand this, the core code calls disable on all the interrupts
> while going to suspend. Notice that I have no disable callback, which means
> those interrupts remain unmasked.
>
> The genirq code does not mask the interrupt while going to suspend, it only
> calls disable(), which I understand should not mask the interrupt for
> check_wakeup_irqs() to work.
>
> If I don't mask that accelerometer interrupts in the interrupt controller's
> suspend() the phone will wakeup every time the user moves around, draining the
> battery unnecessarily.

That's why we mark the interrupts which can wake up from suspend with
set_wake() so you can configure your hardware accordingly. That's how
all other stuff works, at least how it's supposed to work.

If there is no way to tell the interrupt controller which interrupts
are wakeup sources and which are not, then working around it with
local state and private suspend/resume functions is the WRONG answer.

Simply because this kind of misdesigned hardware will creep up over
and over and we want to handle these cases in the core. Even for a
sinlge instance like yours solving it in the core is the right thing
to do, because it's a ~3 lines patch to the core code to get this
done.

Sigh, why insist people on working around core code instead of talking
to the responsible maintainers about their problem in the first place?

Thanks,

tglx

2011-03-11 19:57:25

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Fri, Mar 11, 2011 at 08:43:08PM +0100, Thomas Gleixner wrote:

> Sigh, why insist people on working around core code instead of talking
> to the responsible maintainers about their problem in the first place?

I don't know if it's the case here but with a lot of the people I speak
to it's because they're used to working on proprietary OSs where there's
no possibility of fixing the core and they haven't yet realised that
this is a possibility.

2011-03-11 20:06:57

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

Thomas Gleixner wrote:
> On Fri, 11 Mar 2011, Abhijeet Dharmapurikar wrote:
>>>> Yes however while updating the code I noticed that I would need to keep
>>>> account of all the interrupts enabled and all the interrupts marked
>>>> wakeup.
>>>> This aids in switching to the wakeup set in the suspend callback and the
>>>> enabled set in the resume callback. I will update the resume callback to
>>>> enable the interrupts in irqs_allowed(the local state storage) in the next
>>>> patch (my current patch does not do that).
>>>>
>>>> IOW I need to keep the local state storage.
>>> Wrong. The interrupts are disabled and reenabled by the core code and
>>> not by some extra suspend/resume callbacks in your driver. The core
>>> checks those marked as IRQ_WAKE, the wake callback to the irq chip is
>>> only there if you need to set up some hardware register in order to
>>> make the wake functionality work. So again, you don't need local state
>>> as the core tracks the state for you.
>> Help me understand this, the core code calls disable on all the interrupts
>> while going to suspend. Notice that I have no disable callback, which means
>> those interrupts remain unmasked.
>>
>> The genirq code does not mask the interrupt while going to suspend, it only
>> calls disable(), which I understand should not mask the interrupt for
>> check_wakeup_irqs() to work.
>>
>> If I don't mask that accelerometer interrupts in the interrupt controller's
>> suspend() the phone will wakeup every time the user moves around, draining the
>> battery unnecessarily.
>
> That's why we mark the interrupts which can wake up from suspend with
> set_wake() so you can configure your hardware accordingly. That's how
> all other stuff works, at least how it's supposed to work.
>
> If there is no way to tell the interrupt controller which interrupts
> are wakeup sources and which are not, then working around it with
> local state and private suspend/resume functions is the WRONG answer.
>
> Simply because this kind of misdesigned hardware will creep up over
> and over and we want to handle these cases in the core. Even for a
> sinlge instance like yours solving it in the core is the right thing
> to do, because it's a ~3 lines patch to the core code to get this
> done.

~3 lines patch to the code sounds promising. Please tell me how?

--
--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-11 20:12:58

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Fri, 11 Mar 2011, Mark Brown wrote:

> On Fri, Mar 11, 2011 at 08:43:08PM +0100, Thomas Gleixner wrote:
>
> > Sigh, why insist people on working around core code instead of talking
> > to the responsible maintainers about their problem in the first place?
>
> I don't know if it's the case here but with a lot of the people I speak
> to it's because they're used to working on proprietary OSs where there's
> no possibility of fixing the core and they haven't yet realised that
> this is a possibility.

Good point. If I only knew a way to get this message to those folks
once and forever.

There are several good reasons to avoid working around core code:

- It's usually simpler and faster as the core code has all the
necessary information. So that's even an argument which managers
might understand.

- Such workarounds, when not caught, tend to spread themself
magically because driver writers checkout the existing code of
similar devices and copy/paste/modify^Wuglify them over and over.

- In the worst case such workarounds make the core maintainence
harder and in some cases impossible, because they silently imply
semantics on the core w/o the core maintainer knowing about them.

I'm going to give a talk about that at the collab summit :)

Thanks,

tglx

2011-03-11 20:38:56

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

On Fri, 11 Mar 2011, Abhijeet Dharmapurikar wrote:
> Thomas Gleixner wrote:
> > Simply because this kind of misdesigned hardware will creep up over
> > and over and we want to handle these cases in the core. Even for a
> > sinlge instance like yours solving it in the core is the right thing
> > to do, because it's a ~3 lines patch to the core code to get this
> > done.
>
> ~3 lines patch to the code sounds promising. Please tell me how?

So I deduce, that your HW has no way to mark the wakeup
interrupts. Whack your HW designer on my behalf, please! :)

Patch below against:

git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git irq/core

It's 8 lines, but that's still at least an order of magnitude less
than solving this with an workaround. :)

Thanks,

tglx

---------->
Subject: genirq-force-mask-on-suspend.patch
From: Thomas Gleixner <[email protected]>
Date: Fri, 11 Mar 2011 21:22:14 +0100

Signed-off-by: Thomas Gleixner <[email protected]>
---
include/linux/irq.h | 2 ++
kernel/irq/pm.c | 14 ++++++++++----
2 files changed, 12 insertions(+), 4 deletions(-)

Index: linux-2.6-tip/include/linux/irq.h
===================================================================
--- linux-2.6-tip.orig/include/linux/irq.h
+++ linux-2.6-tip/include/linux/irq.h
@@ -330,10 +330,12 @@ struct irq_chip {
*
* IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
* IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
+ * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
*/
enum {
IRQCHIP_SET_TYPE_MASKED = (1 << 0),
IRQCHIP_EOI_IF_HANDLED = (1 << 1),
+ IRQCHIP_MASK_ON_SUSPEND = (2 << 1),
};

/* This include will go away once we isolated irq_desc usage to core code */
Index: linux-2.6-tip/kernel/irq/pm.c
===================================================================
--- linux-2.6-tip.orig/kernel/irq/pm.c
+++ linux-2.6-tip/kernel/irq/pm.c
@@ -68,10 +68,16 @@ int check_wakeup_irqs(void)
struct irq_desc *desc;
int irq;

- for_each_irq_desc(irq, desc)
- if (irqd_is_wakeup_set(&desc->irq_data) &&
- (desc->istate & IRQS_PENDING))
- return -EBUSY;
+ for_each_irq_desc(irq, desc) {
+ if (irqd_is_wakeup_set(&desc->irq_data)) {
+ if (desc->istate & IRQS_PENDING)
+ return -EBUSY;
+ continue;
+ }
+ if (desc->istate & IRQS_SUSPENDED &&
+ irq_desc_get_chip(desc)->flags & IRQCHIP_MASK_ON_SUSPEND)
+ mask_irq(desc);
+ }

return 0;
}

2011-03-12 00:13:19

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 2/6] mfd: pm8xxx: Add irq support

Thomas Gleixner wrote:
> So I deduce, that your HW has no way to mark the wakeup
> interrupts. Whack your HW designer on my behalf, please! :)
>
> Patch below against:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip.git irq/core
>
> It's 8 lines, but that's still at least an order of magnitude less
> than solving this with an workaround. :)
>
> Thanks,
>
> tglx
>
> ---------->
> Subject: genirq-force-mask-on-suspend.patch
> From: Thomas Gleixner <[email protected]>
> Date: Fri, 11 Mar 2011 21:22:14 +0100
>
> Signed-off-by: Thomas Gleixner <[email protected]>
> ---
> include/linux/irq.h | 2 ++
> kernel/irq/pm.c | 14 ++++++++++----
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> Index: linux-2.6-tip/include/linux/irq.h
> ===================================================================
> --- linux-2.6-tip.orig/include/linux/irq.h
> +++ linux-2.6-tip/include/linux/irq.h
> @@ -330,10 +330,12 @@ struct irq_chip {
> *
> * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
> * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
> + * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
> */
> enum {
> IRQCHIP_SET_TYPE_MASKED = (1 << 0),
> IRQCHIP_EOI_IF_HANDLED = (1 << 1),
> + IRQCHIP_MASK_ON_SUSPEND = (2 << 1),
> };
>
> /* This include will go away once we isolated irq_desc usage to core code */
> Index: linux-2.6-tip/kernel/irq/pm.c
> ===================================================================
> --- linux-2.6-tip.orig/kernel/irq/pm.c
> +++ linux-2.6-tip/kernel/irq/pm.c
> @@ -68,10 +68,16 @@ int check_wakeup_irqs(void)
> struct irq_desc *desc;
> int irq;
>
> - for_each_irq_desc(irq, desc)
> - if (irqd_is_wakeup_set(&desc->irq_data) &&
> - (desc->istate & IRQS_PENDING))
> - return -EBUSY;
> + for_each_irq_desc(irq, desc) {
> + if (irqd_is_wakeup_set(&desc->irq_data)) {
> + if (desc->istate & IRQS_PENDING)
> + return -EBUSY;
> + continue;
> + }
> + if (desc->istate & IRQS_SUSPENDED &&
> + irq_desc_get_chip(desc)->flags & IRQCHIP_MASK_ON_SUSPEND)
> + mask_irq(desc);
> + }
>
> return 0;
> }

Awesome. This addresses the suspend/resume concerns. Thanks so much.
Reviewed-by: Abhijeet Dharmapurikar <[email protected]>

To avoid compile time issues, I will add
.flags = IRQCHIP_MASK_ON_SUSPEND
in my driver at a later time (after this change is pulled in).

--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-12 09:36:54

by Grant Likely

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 3/6] gpio: pm8xxx-gpio: Add pm8xxx gpio driver

On Mon, Mar 07, 2011 at 10:09:47PM -0800, [email protected] wrote:
> From: Abhijeet Dharmapurikar <[email protected]>
>
> Add support for GPIO on Qualcomm PM8xxx PMIC chips.
>
>
> Signed-off-by: Abhijeet Dharmapurikar <[email protected]>
> ---

Hi Abhijeet,

comments below, but mostly looks good to me.

g.

> drivers/gpio/Kconfig | 10 +
> drivers/gpio/Makefile | 1 +
> drivers/gpio/pm8xxx-gpio.c | 451 +++++++++++++++++++++++++++++++++++++++
> drivers/mfd/pm8921-core.c | 34 +++
> include/linux/mfd/pm8921.h | 11 +
> include/linux/mfd/pm8xxx/gpio.h | 132 ++++++++++++
> 6 files changed, 639 insertions(+), 0 deletions(-)
> create mode 100644 drivers/gpio/pm8xxx-gpio.c
> create mode 100644 include/linux/mfd/pm8xxx/gpio.h
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 664660e..c5e6f51 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -411,4 +411,14 @@ config GPIO_JANZ_TTL
> This driver provides support for driving the pins in output
> mode only. Input mode is not supported.
>
> +comment "SSBI GPIO expanders:"

SSBI? Also, the comment seems rather out of place when there
currently appears to only be one of such devices.

> +
> +config GPIO_PM8XXX
> + tristate "Qualcomm PM8xxx GPIO support"
> + depends on MFD_PM8XXX
> + default y if MFD_PM8XXX
> + help
> + This option enables support for on-chip GPIO found on Qualcomm PM8xxx
> + PMICs.
> +
> endif
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 3351cf8..10efe6c 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -42,3 +42,4 @@ obj-$(CONFIG_GPIO_JANZ_TTL) += janz-ttl.o
> obj-$(CONFIG_GPIO_SX150X) += sx150x.o
> obj-$(CONFIG_GPIO_VX855) += vx855_gpio.o
> obj-$(CONFIG_GPIO_ML_IOH) += ml_ioh_gpio.o
> +obj-$(CONFIG_GPIO_PM8XXX) += pm8xxx-gpio.o
> diff --git a/drivers/gpio/pm8xxx-gpio.c b/drivers/gpio/pm8xxx-gpio.c
> new file mode 100644
> index 0000000..d9c246b
> --- /dev/null
> +++ b/drivers/gpio/pm8xxx-gpio.c
> @@ -0,0 +1,451 @@
> +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * Qualcomm PMIC8XXX GPIO driver
> + *
> + */
> +
> +#define pr_fmt(fmt) "%s: " fmt, __func__
> +
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/mfd/pm8xxx/core.h>
> +#include <linux/mfd/pm8xxx/gpio.h>
> +#include <linux/debugfs.h>
> +#include <linux/uaccess.h>
> +#include <linux/fs.h>
> +#include <linux/seq_file.h>
> +#include <linux/slab.h>
> +
> +/* GPIO registers */
> +#define SSBI_REG_ADDR_GPIO_BASE 0x150
> +#define SSBI_REG_ADDR_GPIO(n) (SSBI_REG_ADDR_GPIO_BASE + n)
> +
> +/* GPIO */
> +#define PM_GPIO_BANK_MASK 0x70
> +#define PM_GPIO_BANK_SHIFT 4
> +#define PM_GPIO_WRITE 0x80
> +
> +/* Bank 0 */
> +#define PM_GPIO_VIN_MASK 0x0E
> +#define PM_GPIO_VIN_SHIFT 1
> +#define PM_GPIO_MODE_ENABLE 0x01
> +
> +/* Bank 1 */
> +#define PM_GPIO_MODE_MASK 0x0C
> +#define PM_GPIO_MODE_SHIFT 2
> +#define PM_GPIO_OUT_BUFFER 0x02
> +#define PM_GPIO_OUT_INVERT 0x01
> +
> +#define PM_GPIO_MODE_OFF 3
> +#define PM_GPIO_MODE_OUTPUT 2
> +#define PM_GPIO_MODE_INPUT 0
> +#define PM_GPIO_MODE_BOTH 1
> +
> +/* Bank 2 */
> +#define PM_GPIO_PULL_MASK 0x0E
> +#define PM_GPIO_PULL_SHIFT 1
> +
> +/* Bank 3 */
> +#define PM_GPIO_OUT_STRENGTH_MASK 0x0C
> +#define PM_GPIO_OUT_STRENGTH_SHIFT 2
> +
> +/* Bank 4 */
> +#define PM_GPIO_FUNC_MASK 0x0E
> +#define PM_GPIO_FUNC_SHIFT 1
> +
> +/* Bank 5 */
> +#define PM_GPIO_NON_INT_POL_INV 0x08
> +#define PM_GPIO_BANKS 6
> +
> +struct pm_gpio_chip {
> + struct list_head link;
> + struct gpio_chip gpio_chip;
> + struct mutex pm_lock;
> + u8 *bank1;
> + int irq_base;
> +};
> +
> +static LIST_HEAD(pm_gpio_chips);

Looks like you need a mutex for protecting this list from mutual access.

> +
> +static int pm_gpio_get(struct pm_gpio_chip *pm_gpio_chip, unsigned gpio)
> +{
> + int mode;
> +
> + if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
> + return -EINVAL;
> +
> + /* Get gpio value from config bank 1 if output gpio.
> + Get gpio value from IRQ RT status register for all other gpio modes.
> + */
> + mode = (pm_gpio_chip->bank1[gpio] & PM_GPIO_MODE_MASK) >>
> + PM_GPIO_MODE_SHIFT;
> + if (mode == PM_GPIO_MODE_OUTPUT)
> + return pm_gpio_chip->bank1[gpio] & PM_GPIO_OUT_INVERT;
> + else
> + return pm8xxx_read_irq_stat(pm_gpio_chip->gpio_chip.dev->parent,
> + pm_gpio_chip->irq_base + gpio);
> +}
> +
> +static int pm_gpio_set(struct pm_gpio_chip *pm_gpio_chip,
> + unsigned gpio, int value)
> +{
> + int rc;
> + u8 bank1;
> +
> + if (gpio >= pm_gpio_chip->gpio_chip.ngpio || pm_gpio_chip == NULL)
> + return -EINVAL;
> +
> + mutex_lock(&pm_gpio_chip->pm_lock);
> + bank1 = PM_GPIO_WRITE
> + | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_OUT_INVERT);
> +
> + if (value)
> + bank1 |= PM_GPIO_OUT_INVERT;
> +
> + pm_gpio_chip->bank1[gpio] = bank1;
> + rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
> + SSBI_REG_ADDR_GPIO(gpio), bank1);
> + mutex_unlock(&pm_gpio_chip->pm_lock);
> +
> + if (rc)
> + pr_err("FAIL pm8xxx_writeb(): rc=%d. "
> + "(gpio=%d, value=%d)\n",
> + rc, gpio, value);
> +
> + return rc;
> +}
> +
> +static int dir_map[] = {
> + PM_GPIO_MODE_OFF,
> + PM_GPIO_MODE_OUTPUT,
> + PM_GPIO_MODE_INPUT,
> + PM_GPIO_MODE_BOTH,
> +};
> +
> +static int pm_gpio_set_direction(struct pm_gpio_chip *pm_gpio_chip,
> + unsigned gpio, int direction)
> +{
> + int rc;
> + u8 bank1;
> +
> + if (!direction || pm_gpio_chip == NULL)
> + return -EINVAL;
> +
> + mutex_lock(&pm_gpio_chip->pm_lock);
> + bank1 = PM_GPIO_WRITE
> + | (pm_gpio_chip->bank1[gpio] & ~PM_GPIO_MODE_MASK);
> +
> + bank1 |= ((dir_map[direction] << PM_GPIO_MODE_SHIFT)
> + & PM_GPIO_MODE_MASK);
> +
> + pm_gpio_chip->bank1[gpio] = bank1;
> + rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
> + SSBI_REG_ADDR_GPIO(gpio), bank1);
> + mutex_unlock(&pm_gpio_chip->pm_lock);
> +
> + if (rc)
> + pr_err("Failed on pm8xxx_writeb(): rc=%d (GPIO config)\n",
> + rc);
> +
> + return rc;
> +}
> +
> +static int pm_gpio_init_bank1(struct pm_gpio_chip *pm_gpio_chip)
> +{
> + int i, rc;
> + u8 bank;
> +
> + for (i = 0; i < pm_gpio_chip->gpio_chip.ngpio; i++) {
> + bank = 1 << PM_GPIO_BANK_SHIFT;
> + rc = pm8xxx_writeb(pm_gpio_chip->gpio_chip.dev->parent,
> + SSBI_REG_ADDR_GPIO(i),
> + bank);
> + if (rc) {
> + pr_err("error setting bank rc=%d\n", rc);
> + return rc;
> + }
> +
> + rc = pm8xxx_readb(pm_gpio_chip->gpio_chip.dev->parent,
> + SSBI_REG_ADDR_GPIO(i),
> + &pm_gpio_chip->bank1[i]);
> + if (rc) {
> + pr_err("error reading bank 1 rc=%d\n", rc);
> + return rc;
> + }
> + }
> + return 0;
> +}
> +
> +static int pm_gpio_to_irq(struct gpio_chip *gpio_chip, unsigned offset)
> +{
> + struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
> +
> + return pm_gpio_chip->irq_base + offset;
> +}
> +
> +static int pm_gpio_read(struct gpio_chip *gpio_chip, unsigned offset)
> +{
> + struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
> +
> + return pm_gpio_get(pm_gpio_chip, offset);
> +}
> +
> +static void pm_gpio_write(struct gpio_chip *gpio_chip,
> + unsigned offset, int val)
> +{
> + struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
> +
> + pm_gpio_set(pm_gpio_chip, offset, val);
> +}
> +
> +static int pm_gpio_direction_input(struct gpio_chip *gpio_chip,
> + unsigned offset)
> +{
> + struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
> +
> + return pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_IN);
> +}
> +
> +static int pm_gpio_direction_output(struct gpio_chip *gpio_chip,
> + unsigned offset,
> + int val)
> +{
> + int ret;
> + struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
> +
> + ret = pm_gpio_set_direction(pm_gpio_chip, offset, PM_GPIO_DIR_OUT);
> + if (!ret)
> + ret = pm_gpio_set(pm_gpio_chip, offset, val);
> +
> + return ret;
> +}
> +
> +static void pm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gpio_chip)
> +{
> + static const char * const cmode[] = { "in", "in/out", "out", "off" };
> + struct pm_gpio_chip *pm_gpio_chip = dev_get_drvdata(gpio_chip->dev);
> + u8 mode, state, bank;
> + const char *label;
> + int i, j;
> +
> + for (i = 0; i < gpio_chip->ngpio; i++) {
> + label = gpiochip_is_requested(gpio_chip, i);
> + mode = (pm_gpio_chip->bank1[i] & PM_GPIO_MODE_MASK) >>
> + PM_GPIO_MODE_SHIFT;
> + state = pm_gpio_get(pm_gpio_chip, i);
> + seq_printf(s, "gpio-%-3d (%-12.12s) %-10.10s"
> + " %s",
> + gpio_chip->base + i,
> + label ? label : "--",
> + cmode[mode],
> + state ? "hi" : "lo");
> + for (j = 0; j < PM_GPIO_BANKS; j++) {
> + bank = j << PM_GPIO_BANK_SHIFT;
> + pm8xxx_writeb(gpio_chip->dev->parent,
> + SSBI_REG_ADDR_GPIO(i),
> + bank);
> + pm8xxx_readb(gpio_chip->dev->parent,
> + SSBI_REG_ADDR_GPIO(i),
> + &bank);
> + seq_printf(s, " 0x%02x", bank);
> + }
> + seq_printf(s, "\n");
> + }
> +}
> +
> +static int __devinit pm_gpio_probe(struct platform_device *pdev)
> +{
> + int ret;
> + const struct pm8xxx_gpio_platform_data *pdata = pdev->dev.platform_data;
> + struct pm_gpio_chip *pm_gpio_chip;
> +
> + if (!pdata) {
> + pr_err("missing platform data\n");
> + ret = -EINVAL;
> + goto out;
> + }
> +
> + pm_gpio_chip = kzalloc(sizeof(struct pm_gpio_chip), GFP_KERNEL);
> + if (!pm_gpio_chip) {
> + pr_err("Cannot allocate pm_gpio_chip\n");
> + ret = -ENOMEM;
> + goto out;
> + }
> +
> + pm_gpio_chip->bank1 = kzalloc(sizeof(u8) * pdata->gpio_cdata.ngpios,
> + GFP_KERNEL);
> + if (!pm_gpio_chip->bank1) {
> + pr_err("Cannot allocate pm_gpio_chip->bank1\n");
> + ret = -ENOMEM;
> + goto out;
> + }
> +
> + mutex_init(&pm_gpio_chip->pm_lock);
> + pm_gpio_chip->gpio_chip.label = "pm-gpio";
> + pm_gpio_chip->gpio_chip.direction_input = pm_gpio_direction_input;
> + pm_gpio_chip->gpio_chip.direction_output = pm_gpio_direction_output;
> + pm_gpio_chip->gpio_chip.to_irq = pm_gpio_to_irq;
> + pm_gpio_chip->gpio_chip.get = pm_gpio_read;
> + pm_gpio_chip->gpio_chip.set = pm_gpio_write;
> + pm_gpio_chip->gpio_chip.dbg_show = pm_gpio_dbg_show;
> + pm_gpio_chip->gpio_chip.ngpio = pdata->gpio_cdata.ngpios;
> + pm_gpio_chip->gpio_chip.can_sleep = 1;
> + pm_gpio_chip->gpio_chip.dev = &pdev->dev;
> + pm_gpio_chip->gpio_chip.base = pdata->gpio_base;
> + pm_gpio_chip->irq_base = platform_get_irq(pdev, 0);
> + list_add(&pm_gpio_chip->link, &pm_gpio_chips);
> + platform_set_drvdata(pdev, pm_gpio_chip);
> +
> + ret = gpiochip_add(&pm_gpio_chip->gpio_chip);
> + if (ret) {
> + pr_err("gpiochip_add failed ret = %d\n", ret);
> + goto reset_drvdata;
> + }
> +
> + ret = pm_gpio_init_bank1(pm_gpio_chip);
> + if (ret) {
> + pr_err("gpio init bank failed ret = %d\n", ret);
> + goto remove_chip;
> + }
> +
> + return 0;
> +
> +remove_chip:
> + if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
> + pr_err("failed to remove gpio chip\n");
> +reset_drvdata:
> + platform_set_drvdata(pdev, NULL);
> + mutex_destroy(&pm_gpio_chip->pm_lock);
> + kfree(pm_gpio_chip);
> +out:
> + return ret;
> +}
> +
> +static int __devexit pm_gpio_remove(struct platform_device *pdev)
> +{
> + struct pm_gpio_chip *pm_gpio_chip
> + = platform_get_drvdata(pdev);
> +
> + platform_set_drvdata(pdev, NULL);
> + if (gpiochip_remove(&pm_gpio_chip->gpio_chip))
> + pr_err("failed to remove gpio chip\n");
> + mutex_destroy(&pm_gpio_chip->pm_lock);
> + kfree(pm_gpio_chip->bank1);
> + kfree(pm_gpio_chip);
> + return 0;
> +}
> +
> +int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
> +{
> + int rc;
> + u8 bank[8];
> + struct pm_gpio_chip *pm_gpio_chip;
> + struct gpio_chip *gpio_chip;
> + int pm_gpio;
> + int found = 0;
> +
> + if (param == NULL)
> + return -EINVAL;
> + list_for_each_entry(pm_gpio_chip, &pm_gpio_chips, link) {
> + gpio_chip = &pm_gpio_chip->gpio_chip;
> + if (gpio >= gpio_chip->base
> + && gpio < gpio_chip->base + gpio_chip->ngpio) {
> + found = 1;
> + pm_gpio = gpio - gpio_chip->base;
> + break;
> + }
> + }
> + if (!found) {
> + pr_err("called on gpio %d not handled by any pmic\n", gpio);
> + return -EINVAL;
> + }
> +
> + /* Select banks and configure the gpio */
> + bank[0] = PM_GPIO_WRITE |
> + ((param->vin_sel << PM_GPIO_VIN_SHIFT) &
> + PM_GPIO_VIN_MASK) |
> + PM_GPIO_MODE_ENABLE;
> + bank[1] = PM_GPIO_WRITE |
> + ((1 << PM_GPIO_BANK_SHIFT) &
> + PM_GPIO_BANK_MASK) |
> + ((dir_map[param->direction] <<
> + PM_GPIO_MODE_SHIFT) &
> + PM_GPIO_MODE_MASK) |
> + ((param->direction & PM_GPIO_DIR_OUT) ?
> + ((param->output_buffer & 1) ?
> + PM_GPIO_OUT_BUFFER : 0) : 0) |
> + ((param->direction & PM_GPIO_DIR_OUT) ?
> + param->output_value & 0x01 : 0);
> + bank[2] = PM_GPIO_WRITE |
> + ((2 << PM_GPIO_BANK_SHIFT) &
> + PM_GPIO_BANK_MASK) |
> + ((param->pull << PM_GPIO_PULL_SHIFT) &
> + PM_GPIO_PULL_MASK);
> + bank[3] = PM_GPIO_WRITE |
> + ((3 << PM_GPIO_BANK_SHIFT) &
> + PM_GPIO_BANK_MASK) |
> + ((param->out_strength <<
> + PM_GPIO_OUT_STRENGTH_SHIFT) &
> + PM_GPIO_OUT_STRENGTH_MASK);
> + bank[4] = PM_GPIO_WRITE |
> + ((4 << PM_GPIO_BANK_SHIFT) &
> + PM_GPIO_BANK_MASK) |
> + ((param->function << PM_GPIO_FUNC_SHIFT) &
> + PM_GPIO_FUNC_MASK);
> + bank[5] = PM_GPIO_WRITE |
> + ((5 << PM_GPIO_BANK_SHIFT) & PM_GPIO_BANK_MASK) |
> + (param->inv_int_pol ? 0 : PM_GPIO_NON_INT_POL_INV);
> +
> + mutex_lock(&pm_gpio_chip->pm_lock);
> + /* Remember bank1 for later use */
> + pm_gpio_chip->bank1[pm_gpio] = bank[1];
> + rc = pm8xxx_write_buf(pm_gpio_chip->gpio_chip.dev->parent,
> + SSBI_REG_ADDR_GPIO(pm_gpio), bank, 6);
> + mutex_unlock(&pm_gpio_chip->pm_lock);
> +
> + if (rc)
> + pr_err("Failed on pm8xxx_write_buf() rc=%d (GPIO config)\n",
> + rc);
> +
> + return rc;
> +}
> +EXPORT_SYMBOL(pm8xxx_gpio_config);
> +
> +static struct platform_driver pm_gpio_driver = {
> + .probe = pm_gpio_probe,
> + .remove = __devexit_p(pm_gpio_remove),
> + .driver = {
> + .name = PM8XXX_GPIO_DEV_NAME,
> + .owner = THIS_MODULE,
> + },
> +};
> +
> +static int __init pm_gpio_init(void)
> +{
> + int rc = platform_driver_register(&pm_gpio_driver);
> +
> + return rc;
> +}
> +subsys_initcall(pm_gpio_init);
> +
> +static void __exit pm_gpio_exit(void)
> +{
> + platform_driver_unregister(&pm_gpio_driver);
> +}
> +module_exit(pm_gpio_exit);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("PMIC GPIO driver");
> +MODULE_VERSION("1.0");
> +MODULE_ALIAS("platform:" PM8XXX_GPIO_DEV_NAME);
> diff --git a/drivers/mfd/pm8921-core.c b/drivers/mfd/pm8921-core.c
> index d554551..c887ac6 100644
> --- a/drivers/mfd/pm8921-core.c
> +++ b/drivers/mfd/pm8921-core.c
> @@ -79,6 +79,22 @@ static struct pm8xxx_drvdata pm8921_drvdata = {
> .pmic_read_irq_stat = pm8921_read_irq_stat,
> };
>
> +static const struct resource gpio_cell_resources[] __devinitconst = {
> + [0] = {
> + .start = PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, 0),
> + .end = PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, 0)
> + + PM8921_NR_GPIOS - 1,
> + .flags = IORESOURCE_IRQ,
> + },
> +};
> +
> +static struct mfd_cell gpio_cell __devinitdata = {
> + .name = PM8XXX_GPIO_DEV_NAME,
> + .id = -1,
> + .resources = gpio_cell_resources,
> + .num_resources = ARRAY_SIZE(gpio_cell_resources),
> +};
> +
> static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
> *pdata,
> struct pm8921 *pmic,
> @@ -103,7 +119,25 @@ static int __devinit pm8921_add_subdevices(const struct pm8921_platform_data
> pmic->irq_data = irq_data;
> }
>
> + if (pdata->gpio_pdata) {
> + pdata->gpio_pdata->gpio_cdata.ngpios = PM8921_NR_GPIOS;
> + pdata->gpio_pdata->gpio_cdata.rev = rev;
> + gpio_cell.platform_data = pdata->gpio_pdata;
> + gpio_cell.data_size = sizeof(struct pm8xxx_gpio_platform_data);
> + ret = mfd_add_devices(pmic->dev, 0, &gpio_cell, 1,
> + NULL, irq_base);
> + if (ret) {
> + pr_err("Failed to add gpio subdevice ret=%d\n", ret);
> + goto bail;
> + }
> + }
> +
> + return 0;
> bail:
> + if (pmic->irq_data) {
> + pm8xxx_irq_exit(pmic->irq_data);
> + pmic->irq_data = NULL;
> + }
> return ret;
> }
>
> diff --git a/include/linux/mfd/pm8921.h b/include/linux/mfd/pm8921.h
> index d2806ff..74d47c7 100644
> --- a/include/linux/mfd/pm8921.h
> +++ b/include/linux/mfd/pm8921.h
> @@ -19,12 +19,23 @@
>
> #include <linux/device.h>
> #include <linux/mfd/pm8xxx/irq.h>
> +#include <linux/mfd/pm8xxx/gpio.h>
>
> #define PM8921_NR_IRQS 256
>
> +#define PM8921_NR_GPIOS 44
> +
> +#define PM8921_GPIO_BLOCK_START 24
> +#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
> +
> +/* GPIOs [1,N] */
> +#define PM8921_GPIO_IRQ(base, gpio) ((base) + \
> + PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, (gpio)-1))
> +
> struct pm8921_platform_data {
> int irq_base;
> struct pm8xxx_irq_platform_data *irq_pdata;
> + struct pm8xxx_gpio_platform_data *gpio_pdata;
> };
>
> #endif
> diff --git a/include/linux/mfd/pm8xxx/gpio.h b/include/linux/mfd/pm8xxx/gpio.h
> new file mode 100644
> index 0000000..3ab08e0
> --- /dev/null
> +++ b/include/linux/mfd/pm8xxx/gpio.h
> @@ -0,0 +1,132 @@
> +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * Qualcomm PMIC8XXX gpio driver header file
> + *
> + */
> +
> +#ifndef __PM8XXX_GPIO_H
> +#define __PM8XXX_GPIO_H
> +
> +#include <linux/errno.h>
> +
> +#define PM8XXX_GPIO_DEV_NAME "pm8xxx-gpio"
> +
> +struct pm8xxx_gpio_core_data {
> + u32 rev;
> + int ngpios;
> +};
> +
> +struct pm8xxx_gpio_platform_data {
> + struct pm8xxx_gpio_core_data gpio_cdata;
> + int gpio_base;
> +};

There doesn't seem to be any value it splitting pm8xxx_gpio_core_data
into a separate structure from what I see in this patch. How is this
going to be used?

> +
> +/* GPIO parameters */
> +/* direction */
> +#define PM_GPIO_DIR_OUT 0x01
> +#define PM_GPIO_DIR_IN 0x02
> +#define PM_GPIO_DIR_BOTH (PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
> +
> +/* output_buffer */
> +#define PM_GPIO_OUT_BUF_OPEN_DRAIN 1
> +#define PM_GPIO_OUT_BUF_CMOS 0
> +
> +/* pull */
> +#define PM_GPIO_PULL_UP_30 0
> +#define PM_GPIO_PULL_UP_1P5 1
> +#define PM_GPIO_PULL_UP_31P5 2
> +#define PM_GPIO_PULL_UP_1P5_30 3
> +#define PM_GPIO_PULL_DN 4
> +#define PM_GPIO_PULL_NO 5
> +
> +/* vin_sel: Voltage Input Select */
> +#define PM_GPIO_VIN_VPH 0
> +#define PM_GPIO_VIN_BB 1
> +#define PM_GPIO_VIN_S3 2
> +#define PM_GPIO_VIN_L3 3
> +#define PM_GPIO_VIN_L7 4
> +#define PM_GPIO_VIN_L6 5
> +#define PM_GPIO_VIN_L5 6
> +#define PM_GPIO_VIN_L2 7
> +
> +/* out_strength */
> +#define PM_GPIO_STRENGTH_NO 0
> +#define PM_GPIO_STRENGTH_HIGH 1
> +#define PM_GPIO_STRENGTH_MED 2
> +#define PM_GPIO_STRENGTH_LOW 3
> +
> +/* function */
> +#define PM_GPIO_FUNC_NORMAL 0
> +#define PM_GPIO_FUNC_PAIRED 1
> +#define PM_GPIO_FUNC_1 2
> +#define PM_GPIO_FUNC_2 3
> +#define PM_GPIO_DTEST1 4
> +#define PM_GPIO_DTEST2 5
> +#define PM_GPIO_DTEST3 6
> +#define PM_GPIO_DTEST4 7
> +
> +/**
> + * struct pm_gpio - structure to specify gpio configurtion values
> + * @direction: indicates whether the gpio should be input, output, or
> + * both. Should be of the type PM_GPIO_DIR_*
> + * @output_buffer: indicates gpio should be configured as CMOS or open
> + * drain. Should be of the type PM_GPIO_OUT_BUF_*
> + * @output_value: The gpio output value of the gpio line - 0 or 1
> + * @pull: Indicates whether a pull up or pull down should be
> + * applied. If a pullup is required the current strength
> + * needs to be specified. Current values of 30uA, 1.5uA,
> + * 31.5uA, 1.5uA with 30uA boost are supported. This value
> + * should be one of the PM_GPIO_PULL_*
> + * @vin_sel: specifies the voltage level when the output is set to 1.
> + * For an input gpio specifies the voltage level at which
> + * the input is interpreted as a logical 1.
> + * @out_strength: the amount of current supplied for an output gpio,
> + * should be of the type PM_GPIO_STRENGTH_*
> + * @function: choose alternate function for the gpio. Certain gpios
> + * can be paired (shorted) with each other. Some gpio pin
> + * can act as alternate functions. This parameter should
> + * be of type PM_GPIO_FUNC_*
> + * @inv_int_pol: Invert polarity before feeding the line to the interrupt
> + * module in pmic. This feature will almost be never used
> + * since the pm8xxx interrupt block can detect both edges
> + * and both levels.
> + */
> +struct pm_gpio {
> + int direction;
> + int output_buffer;
> + int output_value;
> + int pull;
> + int vin_sel;
> + int out_strength;
> + int function;
> + int inv_int_pol;
> +};
> +
> +#if defined(CONFIG_GPIO_PM8XXX) || defined(CONFIG_GPIO_PM8XXX_MODULE)
> +/**
> + * pm8xxx_gpio_config - configure a gpio controlled by a pm8xxx chip
> + * @gpio: gpio number to configure
> + * @param: configuration values
> + *
> + * RETURNS: an appropriate -ERRNO error value on error, or zero for success.
> + */
> +int pm8xxx_gpio_config(int gpio, struct pm_gpio *param);
> +#else
> +static inline int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
> +{
> + return -ENXIO;
> +}
> +#endif
> +
> +#endif
> --
> 1.7.1
>
> Sent by an employee of the Qualcomm Innovation Center, Inc.
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-12 10:19:31

[permalink] [raw]

Subject: [tip:irq/core] genirq: Add chip flag to force mask on suspend

Commit-ID: d209a699a0b975ad47f399d70ddc3791f1b84496
Gitweb: http://git.kernel.org/tip/d209a699a0b975ad47f399d70ddc3791f1b84496
Author: Thomas Gleixner <[email protected]>
AuthorDate: Fri, 11 Mar 2011 21:22:14 +0100
Committer: Thomas Gleixner <[email protected]>
CommitDate: Sat, 12 Mar 2011 11:12:58 +0100

genirq: Add chip flag to force mask on suspend

On suspend we disable all interrupts in the core code, but this does
not mask the interrupt line in the default implementation as we use a
lazy disable approach. That means we mark the interrupt disabled, but
leave the hardware unmasked. That's an optimization because we avoid
the hardware access for the common case where no interrupt happens
after we marked it disabled. If an interrupt happens, then the
interrupt flow handler masks the line at the hardware level and marks
it pending.

Suspend makes use of this delayed disable as it "disables" all
interrupts when preparing the suspend transition. Right before the
system goes into hardware suspend state it checks whether one of the
interrupts which is marked as a wakeup interrupt came in after
disabling it.

Most interrupt chips have a separate register which selects the
interrupts which can wake up the system from suspend, so we don't have
to mask any on the non wakeup interrupts.

But now we have to deal with brilliant designed hardware which lacks
such a wakeup configuration facility. For such hardware it's necessary
to mask all non wakeup interrupts before going into suspend in order
to avoid the wakeup from random interrupts.

Rather than working around this in the affected interrupt chip
implementations we can solve this elegant in the core code itself.

Add a flag IRQCHIP_MASK_ON_SUSPEND which can be set by the irq chip
implementation to indicate, that the interrupts which are not selected
as wakeup sources must be masked in the suspend path. Mask them in the
loop which checks the wakeup interrupts pending flag.

Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Abhijeet Dharmapurikar <[email protected]>
LKML-Reference: <[email protected]>

---
include/linux/irq.h | 2 ++
kernel/irq/pm.c | 22 ++++++++++++++++++----
2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/include/linux/irq.h b/include/linux/irq.h
index ff62d01..1d3577f 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -330,10 +330,12 @@ struct irq_chip {
*
* IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
* IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
+ * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
*/
enum {
IRQCHIP_SET_TYPE_MASKED = (1 << 0),
IRQCHIP_EOI_IF_HANDLED = (1 << 1),
+ IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
};

/* This include will go away once we isolated irq_desc usage to core code */
diff --git a/kernel/irq/pm.c b/kernel/irq/pm.c
index 1329f0e..f76fc00 100644
--- a/kernel/irq/pm.c
+++ b/kernel/irq/pm.c
@@ -68,10 +68,24 @@ int check_wakeup_irqs(void)
struct irq_desc *desc;
int irq;

- for_each_irq_desc(irq, desc)
- if (irqd_is_wakeup_set(&desc->irq_data) &&
- (desc->istate & IRQS_PENDING))
- return -EBUSY;
+ for_each_irq_desc(irq, desc) {
+ if (irqd_is_wakeup_set(&desc->irq_data)) {
+ if (desc->istate & IRQS_PENDING)
+ return -EBUSY;
+ continue;
+ }
+ /*
+ * Check the non wakeup interrupts whether they need
+ * to be masked before finally going into suspend
+ * state. That's for hardware which has no wakeup
+ * source configuration facility. The chip
+ * implementation indicates that with
+ * IRQCHIP_MASK_ON_SUSPEND.
+ */
+ if (desc->istate & IRQS_SUSPENDED &&
+ irq_desc_get_chip(desc)->flags & IRQCHIP_MASK_ON_SUSPEND)
+ mask_irq(desc);
+ }

return 0;
}

2011-03-16 18:55:24

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 3/6] gpio: pm8xxx-gpio: Add pm8xxx gpio driver

>>
>> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
>> index 664660e..c5e6f51 100644
>> --- a/drivers/gpio/Kconfig
>> +++ b/drivers/gpio/Kconfig
>> @@ -411,4 +411,14 @@ config GPIO_JANZ_TTL
>> This driver provides support for driving the pins in output
>> mode only. Input mode is not supported.
>>
>> +comment "SSBI GPIO expanders:"
>
> SSBI? Also, the comment seems rather out of place when there
> currently appears to only be one of such devices.

SSBI is a bus architecture used to access this device's register
(actually this is a subdevice in the pmic and ssbi is used to access all
the registers in the pmic).The bus driver can be found here
https://patchwork.kernel.org/patch/601771/

It didnt occur to me that the comment is only meant for buses which have
more than one gpio devices. I saw
comment "MODULbus GPIO expanders:"
comment "AC97 GPIO expanders:"
both containing single devices and thought it is a norm to add a comment
if a device running on a new bus is introduced.

Let me know if you still think I should remove
comment "SSBI GPIO expanders:" ?

>> +
>> +struct pm_gpio_chip {
>> + struct list_head link;
>> + struct gpio_chip gpio_chip;
>> + struct mutex pm_lock;
>> + u8 *bank1;
>> + int irq_base;
>> +};
>> +
>> +static LIST_HEAD(pm_gpio_chips);
>
> Looks like you need a mutex for protecting this list from mutual access.

Yes will fix this.

>
>> +

>> +#ifndef __PM8XXX_GPIO_H
>> +#define __PM8XXX_GPIO_H
>> +
>> +#include <linux/errno.h>
>> +
>> +#define PM8XXX_GPIO_DEV_NAME "pm8xxx-gpio"
>> +
>> +struct pm8xxx_gpio_core_data {
>> + u32 rev;
>> + int ngpios;
>> +};
>> +
>> +struct pm8xxx_gpio_platform_data {
>> + struct pm8xxx_gpio_core_data gpio_cdata;
>> + int gpio_base;
>> +};
>
> There doesn't seem to be any value it splitting pm8xxx_gpio_core_data
> into a separate structure from what I see in this patch. How is this
> going to be used?

gpio_base comes from the platform data because the board file knows
where in the global gpio numbers the pm8xxx gpio start. For example if
the MSM code supports 150 gpios(0 through 149), the board file will set
gpio_base to indicate pm8xxx gpios should start from 150.

The pm8xxx_gpio_core_data is meant to be filled in by the pm8921 core.
We have different pmic chips with similar gpio implementations. For
example 8058 pmic, 8901 pmic and 8921 pmic, all have the same gpio
implementation but different number of gpio lines. The pm8xxx-gpio.c is
used for all these pmics. Hence we separated core specific gpio
information (number of gpio lines supported) from board specific gpio
information (where in the global map the gpio number for this device
starts).

--
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm
Innovation Center, Inc. is a member of the Code Aurora Forum.

2011-03-16 19:54:55

by Grant Likely

[permalink] [raw]

Subject: Re: [Qualcomm PM8921 MFD v2 3/6] gpio: pm8xxx-gpio: Add pm8xxx gpio driver

On Wed, Mar 16, 2011 at 11:55:19AM -0700, Abhijeet Dharmapurikar wrote:
>
> >>
> >>diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> >>index 664660e..c5e6f51 100644
> >>--- a/drivers/gpio/Kconfig
> >>+++ b/drivers/gpio/Kconfig
> >>@@ -411,4 +411,14 @@ config GPIO_JANZ_TTL
> >> This driver provides support for driving the pins in output
> >> mode only. Input mode is not supported.
> >>+comment "SSBI GPIO expanders:"
> >
> >SSBI? Also, the comment seems rather out of place when there
> >currently appears to only be one of such devices.
>
> SSBI is a bus architecture used to access this device's register
> (actually this is a subdevice in the pmic and ssbi is used to access
> all the registers in the pmic).The bus driver can be found here
> https://patchwork.kernel.org/patch/601771/
>
> It didnt occur to me that the comment is only meant for buses which
> have more than one gpio devices. I saw
> comment "MODULbus GPIO expanders:"
> comment "AC97 GPIO expanders:"
> both containing single devices and thought it is a norm to add a
> comment if a device running on a new bus is introduced.
>
> Let me know if you still think I should remove
> comment "SSBI GPIO expanders:" ?

Yes, remove the comment. I'll probably also remove the comment for
MODULbus and AC97.

g.

>
> >>+
> >>+struct pm_gpio_chip {
> >>+ struct list_head link;
> >>+ struct gpio_chip gpio_chip;
> >>+ struct mutex pm_lock;
> >>+ u8 *bank1;
> >>+ int irq_base;
> >>+};
> >>+
> >>+static LIST_HEAD(pm_gpio_chips);
> >
> >Looks like you need a mutex for protecting this list from mutual access.
>
> Yes will fix this.
>
> >
> >>+
>
> >>+#ifndef __PM8XXX_GPIO_H
> >>+#define __PM8XXX_GPIO_H
> >>+
> >>+#include <linux/errno.h>
> >>+
> >>+#define PM8XXX_GPIO_DEV_NAME "pm8xxx-gpio"
> >>+
> >>+struct pm8xxx_gpio_core_data {
> >>+ u32 rev;
> >>+ int ngpios;
> >>+};
> >>+
> >>+struct pm8xxx_gpio_platform_data {
> >>+ struct pm8xxx_gpio_core_data gpio_cdata;
> >>+ int gpio_base;
> >>+};
> >
> >There doesn't seem to be any value it splitting pm8xxx_gpio_core_data
> >into a separate structure from what I see in this patch. How is this
> >going to be used?
>
> gpio_base comes from the platform data because the board file knows
> where in the global gpio numbers the pm8xxx gpio start. For example
> if the MSM code supports 150 gpios(0 through 149), the board file
> will set gpio_base to indicate pm8xxx gpios should start from 150.
>
> The pm8xxx_gpio_core_data is meant to be filled in by the pm8921
> core. We have different pmic chips with similar gpio
> implementations. For example 8058 pmic, 8901 pmic and 8921 pmic, all
> have the same gpio implementation but different number of gpio
> lines. The pm8xxx-gpio.c is used for all these pmics. Hence we
> separated core specific gpio information (number of gpio lines
> supported) from board specific gpio information (where in the global
> map the gpio number for this device starts).

I could see the argument if multiple pm8xxx instances pointed to a
single pm8xxx_gpio_core_data structure, but in this case it is simply
encapsulated. Personally I'd just drop the extra structure.

g.

2011-03-16 19:56:40