Introduce digital RTC node in wakeup domain. Even though this has
no specific battery backup supply, this on-chip RTC is used in
cost-optimized board designs as a wakeup source.
Reviewed-by: Dhruva Gole <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
---
Changes since v2:
- Just reviewed-by pickups
V2: https://lore.kernel.org/all/[email protected]/
V1: https://lore.kernel.org/all/[email protected]/
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
index 38dced6b4fef..fec81546fbbd 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
@@ -40,4 +40,14 @@ wkup_i2c0: i2c@2b200000 {
clock-names = "fck";
status = "disabled";
};
+
+ wkup_rtc0: rtc@2b1f0000 {
+ compatible = "ti,am62-rtc";
+ reg = <0x00 0x2b1f0000 0x00 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
+ clock-names = "vbus", "osc32k";
+ power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
+ wakeup-source;
+ };
};
--
2.40.0
Hi,
On 20/03/23 22:21, Nishanth Menon wrote:
> Introduce digital RTC node in wakeup domain. Even though this has
> no specific battery backup supply, this on-chip RTC is used in
> cost-optimized board designs as a wakeup source.
>
> Reviewed-by: Dhruva Gole <[email protected]>
> Reviewed-by: Bryan Brattlof <[email protected]>
> Signed-off-by: Nishanth Menon <[email protected]>
> ---
> Changes since v2:
> - Just reviewed-by pickups
>
> V2: https://lore.kernel.org/all/[email protected]/
> V1: https://lore.kernel.org/all/[email protected]/
>
> arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> index 38dced6b4fef..fec81546fbbd 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
> @@ -40,4 +40,14 @@ wkup_i2c0: i2c@2b200000 {
> clock-names = "fck";
> status = "disabled";
> };
> +
> + wkup_rtc0: rtc@2b1f0000 {
> + compatible = "ti,am62-rtc";
> + reg = <0x00 0x2b1f0000 0x00 0x100>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
> + clock-names = "vbus", "osc32k";
> + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>;
> + wakeup-source;
> + };
> };
I was just wondering why some of the rtctests show failures on this platform:
https://gist.github.com/DhruvaG2000/5c6d8bb99b087308b916985d70f0c440
pass:5 fail:2
the test is compiled from tools/testing/selftests/rtc/rtctest.c for arm64 target
Is this expected?
--
Best regards,
Dhruva Gole
Texas Instruments Incorporated
On 10:07-20230321, Dhruva Gole wrote:
[...]
>
> I was just wondering why some of the rtctests show failures on this platform:
>
> https://gist.github.com/DhruvaG2000/5c6d8bb99b087308b916985d70f0c440
>
> pass:5 fail:2
>
> the test is compiled from tools/testing/selftests/rtc/rtctest.c for arm64 target
>
> Is this expected?
I used the standard defconfig and [1] on beagleplay and
cross verified on 6.3-rc3 as well. It works fine. See logs below.
NOTE: BeaglePlay has a external 32k crystal that drives RTC and other
32k clock sources internal to the SoC. This helps maintain accurate
time. If your platform does'nt have an external 32k crystal OR AM62
does'nt enable 32k using MCU_CTRL_LFXOSC_CTRL[2], then default 32k RC
osc inside the SoC triggers. This internal clock is very variable.
There are a ton of stuff inside the SoC that depends on 32k, so this
wont be just a RTC specific behavior.
ti-next: (6.3-rc1)
ti-next + 6.3-rc3: (dirty is because of a rtctest Makefile mod to build
static)
https://gist.github.com/nmenon/e1b300652ac452ad55fa4cf936fc3e63
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git/log/
[2] https://git.beagleboard.org/beagleplay/u-boot/-/blob/lc-ti-u-boot-2021.01/board/ti/am62x/evm.c#L243
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D