2022-05-30 00:54:44

by Liu Ying

Subject: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()

The PLL parameters in rate table should be directly compared with
those read from PLL registers instead of the cooked ones.

Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
Cc: Abel Vesa <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Peng Fan <[email protected]>
Signed-off-by: Liu Ying <[email protected]>
---
drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 71c102d950ab..762b07dd5a6d 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -131,18 +131,7 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
mfi = FIELD_GET(PLL_MFI_MASK, pll_div);

rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
- rdiv = rdiv + 1;
odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
- switch (odiv) {
- case 0:
- odiv = 2;
- break;
- case 1:
- odiv = 3;
- break;
- default:
- break;
- }

/*
* Sometimes, the recalculated rate has deviation due to
@@ -160,6 +149,19 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
if (rate)
return (unsigned long)rate;

+ rdiv = rdiv + 1;
+
+ switch (odiv) {
+ case 0:
+ odiv = 2;
+ break;
+ case 1:
+ odiv = 3;
+ break;
+ default:
+ break;
+ }
+
/* Fvco = Fref * (MFI + MFN / MFD) */
fvco = fvco * mfi * mfd + fvco * mfn;
do_div(fvco, mfd * rdiv * odiv);
--
2.25.1

2022-05-30 07:49:54

by Peng Fan

Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()

> Subject: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table properly in
> ->recalc_rate()
>
> The PLL parameters in rate table should be directly compared with those read
> from PLL registers instead of the cooked ones.
>
> Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> Cc: Abel Vesa <[email protected]>
> Cc: Michael Turquette <[email protected]>
> Cc: Stephen Boyd <[email protected]>
> Cc: Shawn Guo <[email protected]>
> Cc: Sascha Hauer <[email protected]>
> Cc: Pengutronix Kernel Team <[email protected]>
> Cc: Fabio Estevam <[email protected]>
> Cc: NXP Linux Team <[email protected]>
> Cc: Peng Fan <[email protected]>
> Signed-off-by: Liu Ying <[email protected]>

Reviewed-by: Peng Fan <[email protected]>

> ---
> drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++-----------
> 1 file changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
> index 71c102d950ab..762b07dd5a6d 100644
> --- a/drivers/clk/imx/clk-fracn-gppll.c
> +++ b/drivers/clk/imx/clk-fracn-gppll.c
> @@ -131,18 +131,7 @@ static unsigned long
> clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
> mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
>
> rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
> - rdiv = rdiv + 1;
> odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
> - switch (odiv) {
> - case 0:
> - odiv = 2;
> - break;
> - case 1:
> - odiv = 3;
> - break;
> - default:
> - break;
> - }
>
> /*
> * Sometimes, the recalculated rate has deviation due to @@ -160,6
> +149,19 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw
> *hw, unsigned lon
> if (rate)
> return (unsigned long)rate;
>
> + rdiv = rdiv + 1;
> +
> + switch (odiv) {
> + case 0:
> + odiv = 2;
> + break;
> + case 1:
> + odiv = 3;
> + break;
> + default:
> + break;
> + }
> +
> /* Fvco = Fref * (MFI + MFN / MFD) */
> fvco = fvco * mfi * mfd + fvco * mfn;
> do_div(fvco, mfd * rdiv * odiv);
> --
> 2.25.1

2022-05-30 11:28:06

by Peng Fan

Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()

> Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table properly
> in ->recalc_rate()
>
> > Subject: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table
> > properly in
> > ->recalc_rate()
> >
> > The PLL parameters in rate table should be directly compared with
> > those read from PLL registers instead of the cooked ones.
> >
> > Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> > Cc: Abel Vesa <[email protected]>
> > Cc: Michael Turquette <[email protected]>
> > Cc: Stephen Boyd <[email protected]>
> > Cc: Shawn Guo <[email protected]>
> > Cc: Sascha Hauer <[email protected]>
> > Cc: Pengutronix Kernel Team <[email protected]>
> > Cc: Fabio Estevam <[email protected]>
> > Cc: NXP Linux Team <[email protected]>
> > Cc: Peng Fan <[email protected]>
> > Signed-off-by: Liu Ying <[email protected]>
>
> Reviewed-by: Peng Fan <[email protected]>
>
> > ---
> > drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++-----------
> > 1 file changed, 13 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-fracn-gppll.c
> > b/drivers/clk/imx/clk-fracn-gppll.c
> > index 71c102d950ab..762b07dd5a6d 100644
> > --- a/drivers/clk/imx/clk-fracn-gppll.c
> > +++ b/drivers/clk/imx/clk-fracn-gppll.c
> > @@ -131,18 +131,7 @@ static unsigned long
> > clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
> > mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
> >
> > rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
> > - rdiv = rdiv + 1;
> > odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
> > - switch (odiv) {
> > - case 0:
> > - odiv = 2;
> > - break;
> > - case 1:
> > - odiv = 3;
> > - break;
> > - default:
> > - break;
> > - }
> >
> > /*
> > * Sometimes, the recalculated rate has deviation due to @@ -160,6
> > +149,19 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct
> > +clk_hw
> > *hw, unsigned lon
> > if (rate)
> > return (unsigned long)rate;
> >
> > + rdiv = rdiv + 1;

After check more:
According to doc, needs add a check here:
if (!rdiv)
rdiv = rdiv + 1;

Regards,
Peng.
> > +
> > + switch (odiv) {
> > + case 0:
> > + odiv = 2;
> > + break;
> > + case 1:
> > + odiv = 3;
> > + break;
> > + default:
> > + break;
> > + }
> > +
> > /* Fvco = Fref * (MFI + MFN / MFD) */
> > fvco = fvco * mfi * mfd + fvco * mfn;
> > do_div(fvco, mfd * rdiv * odiv);
> > --
> > 2.25.1

2022-06-01 20:25:56

by Liu Ying

Subject: Re: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate table properly in ->recalc_rate()

Hi Peng,

On Mon, 2022-05-30 at 17:08 +0800, Peng Fan wrote:
> > Subject: RE: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate
> > table properly
> > in ->recalc_rate()
> >
> > > Subject: [PATCH] clk: imx: clk-fracn-gppll: Return rate in rate
> > > table
> > > properly in
> > > ->recalc_rate()
> > >
> > > The PLL parameters in rate table should be directly compared with
> > > those read from PLL registers instead of the cooked ones.
> > >
> > > Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
> > > Cc: Abel Vesa <[email protected]>
> > > Cc: Michael Turquette <[email protected]>
> > > Cc: Stephen Boyd <[email protected]>
> > > Cc: Shawn Guo <[email protected]>
> > > Cc: Sascha Hauer <[email protected]>
> > > Cc: Pengutronix Kernel Team <[email protected]>
> > > Cc: Fabio Estevam <[email protected]>
> > > Cc: NXP Linux Team <[email protected]>
> > > Cc: Peng Fan <[email protected]>
> > > Signed-off-by: Liu Ying <[email protected]>
> >
> > Reviewed-by: Peng Fan <[email protected]>
> >
> > > ---
> > > drivers/clk/imx/clk-fracn-gppll.c | 24 +++++++++++++-----------
> > > 1 file changed, 13 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-fracn-gppll.c
> > > b/drivers/clk/imx/clk-fracn-gppll.c
> > > index 71c102d950ab..762b07dd5a6d 100644
> > > --- a/drivers/clk/imx/clk-fracn-gppll.c
> > > +++ b/drivers/clk/imx/clk-fracn-gppll.c
> > > @@ -131,18 +131,7 @@ static unsigned long
> > > clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon
> > > mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
> > >
> > > rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
> > > - rdiv = rdiv + 1;
> > > odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
> > > - switch (odiv) {
> > > - case 0:
> > > - odiv = 2;
> > > - break;
> > > - case 1:
> > > - odiv = 3;
> > > - break;
> > > - default:
> > > - break;
> > > - }
> > >
> > > /*
> > > * Sometimes, the recalculated rate has deviation due to @@
> > > -160,6
> > > +149,19 @@ static unsigned long
> > > clk_fracn_gppll_recalc_rate(struct
> > > +clk_hw
> > > *hw, unsigned lon
> > > if (rate)
> > > return (unsigned long)rate;
> > >
> > > + rdiv = rdiv + 1;
>
> After check more:
> According to doc, needs add a check here:
> if (!rdiv)
> rdiv = rdiv + 1;

This new check is not something this patch tries to deal with.
Maybe, you may send a separate patch to add the check.

Regards,
Liu Ying

>
> Regards,
> Peng.
> > > +
> > > + switch (odiv) {
> > > + case 0:
> > > + odiv = 2;
> > > + break;
> > > + case 1:
> > > + odiv = 3;
> > > + break;
> > > + default:
> > > + break;
> > > + }
> > > +
> > > /* Fvco = Fref * (MFI + MFN / MFD) */
> > > fvco = fvco * mfi * mfd + fvco * mfn;
> > > do_div(fvco, mfd * rdiv * odiv);
> > > --
> > > 2.25.1
>
>