MSM platforms manage NoC related clocks and scaling from RPM.
However, in IPQ SoCs, RPM is not involved in managing NoC
related clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for the accessing the peripherals present in the
system. Hence add a minimalistic interconnect driver that
establishes a path from the processor/memory to those peripherals
and vice versa.
---
v2:
qcom,ipq9574.h
Fix license identifier
Rename macros
qcom,ipq9574-gcc.yaml
Include interconnect-cells
gcc-ipq9574.c
Update commit log
Remove IS_ENABLED(CONFIG_INTERCONNECT) and auto select it from Kconfig
ipq9574.dtsi
Moved to separate patch
Include interconnect-cells to clock controller node
drivers/clk/qcom/Kconfig:
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK
Varadarajan Narayanan (4):
dt-bindings: clock: Add interconnect-cells
dt-bindings: interconnect: Add Qualcomm IPQ9574 support
clk: qcom: add IPQ9574 interconnect clocks support
arm64: dts: qcom: ipq9574: Add icc provider ability to gcc
.../bindings/clock/qcom,ipq9574-gcc.yaml | 3 +
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +
drivers/clk/qcom/Kconfig | 2 +
drivers/clk/qcom/gcc-ipq9574.c | 65 ++++++++++++++++++-
.../dt-bindings/interconnect/qcom,ipq9574.h | 62 ++++++++++++++++++
5 files changed, 133 insertions(+), 1 deletion(-)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
--
2.34.1
Add interconnect-cells to clock provider so that it can be
used as icc provider
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
index 944a0ea79cd6..824781cbdf34 100644
--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
@@ -33,6 +33,9 @@ properties:
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
+ '#interconnect-cells':
+ const: 1
+
required:
- compatible
- clocks
--
2.34.1
Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
interfaces. This will be used by the gcc-ipq9574 driver
that will for providing interconnect services using the
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v2: Rename master slave macros
Fix license identifier
---
.../dt-bindings/interconnect/qcom,ipq9574.h | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
new file mode 100644
index 000000000000..b7b32aa6bbb1
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+#ifndef INTERCONNECT_QCOM_IPQ9574_H
+#define INTERCONNECT_QCOM_IPQ9574_H
+
+#define IPQ_APPS_ID 9574 /* some unique value */
+#define IPQ_NSS_ID (IPQ_APPS_ID * 2)
+
+#define MASTER_ANOC_PCIE0_1 0
+#define SLAVE_ANOC_PCIE0_1 1
+#define MASTER_SNOC_PCIE0_1 2
+#define SLAVE_SNOC_PCIE0_1 3
+#define MASTER_ANOC_PCIE1_1 4
+#define SLAVE_ANOC_PCIE1_1 5
+#define MASTER_SNOC_PCIE1_1 6
+#define SLAVE_SNOC_PCIE1_1 7
+#define MASTER_ANOC_PCIE2_2 8
+#define SLAVE_ANOC_PCIE2_2 9
+#define MASTER_SNOC_PCIE2_2 10
+#define SLAVE_SNOC_PCIE2_2 11
+#define MASTER_ANOC_PCIE3_2 12
+#define SLAVE_ANOC_PCIE3_2 13
+#define MASTER_SNOC_PCIE3_2 14
+#define SLAVE_SNOC_PCIE3_2 15
+#define MASTER_USB 16
+#define SLAVE_USB 17
+#define MASTER_USB_AXI 18
+#define SLAVE_USB_AXI 19
+#define MASTER_NSSNOC_NSSCC 20
+#define SLAVE_NSSNOC_NSSCC 21
+#define MASTER_NSSNOC_SNOC 22
+#define SLAVE_NSSNOC_SNOC 23
+#define MASTER_NSSNOC_SNOC_1 24
+#define SLAVE_NSSNOC_SNOC_1 25
+#define MASTER_NSSNOC_PCNOC_1 26
+#define SLAVE_NSSNOC_PCNOC_1 27
+#define MASTER_NSSNOC_QOSGEN_REF 28
+#define SLAVE_NSSNOC_QOSGEN_REF 29
+#define MASTER_NSSNOC_TIMEOUT_REF 30
+#define SLAVE_NSSNOC_TIMEOUT_REF 31
+#define MASTER_NSSNOC_XO_DCD 32
+#define SLAVE_NSSNOC_XO_DCD 33
+#define MASTER_NSSNOC_ATB 34
+#define SLAVE_NSSNOC_ATB 35
+#define MASTER_MEM_NOC_NSSNOC 36
+#define SLAVE_MEM_NOC_NSSNOC 37
+#define MASTER_NSSNOC_MEMNOC 38
+#define SLAVE_NSSNOC_MEMNOC 39
+#define MASTER_NSSNOC_MEM_NOC_1 40
+#define SLAVE_NSSNOC_MEM_NOC_1 41
+
+#define MASTER_NSS_CC_NSSNOC_PPE 0
+#define SLAVE_NSS_CC_NSSNOC_PPE 1
+#define MASTER_NSS_CC_NSSNOC_PPE_CFG 2
+#define SLAVE_NSS_CC_NSSNOC_PPE_CFG 3
+#define MASTER_NSS_CC_NSSNOC_NSS_CSR 4
+#define SLAVE_NSS_CC_NSSNOC_NSS_CSR 5
+#define MASTER_NSS_CC_NSSNOC_IMEM_QSB 6
+#define SLAVE_NSS_CC_NSSNOC_IMEM_QSB 7
+#define MASTER_NSS_CC_NSSNOC_IMEM_AHB 8
+#define SLAVE_NSS_CC_NSSNOC_IMEM_AHB 9
+
+#endif /* INTERCONNECT_QCOM_IPQ9574_H */
--
2.34.1
Unlike MSM platforms that manage NoC related clocks and scaling
from RPM, IPQ SoCs dont involve RPM in managing NoC related
clocks and there is no NoC scaling.
However, there is a requirement to enable some NoC interface
clocks for accessing the peripheral controllers present on
these NoCs. Though exposing these as normal clocks would work,
having a minimalistic interconnect driver to handle these clocks
would make it consistent with other Qualcomm platforms resulting
in common code paths. This is similar to msm8996-cbf's usage of
icc-clk framework.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v2: Move DTS to separate patch
Update commit log
Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error
---
drivers/clk/qcom/Kconfig | 2 ++
drivers/clk/qcom/gcc-ipq9574.c | 65 +++++++++++++++++++++++++++++++++-
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 8ab08e7b5b6c..af73a0b396eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,8 @@ config IPQ_GCC_8074
config IPQ_GCC_9574
tristate "IPQ9574 Global Clock Controller"
+ select INTERCONNECT
+ select INTERCONNECT_CLK
help
Support for global clock controller on ipq9574 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 0a3f846695b8..ed25bb34216a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -9,9 +9,12 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/interconnect-clk.h>
+#include <linux/interconnect-provider.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
@@ -4301,6 +4304,33 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
};
+
+static struct icc_clk_data *icc_ipq9574;
+
+static int noc_clks[] = {
+ GCC_ANOC_PCIE0_1LANE_M_CLK,
+ GCC_SNOC_PCIE0_1LANE_S_CLK,
+ GCC_ANOC_PCIE1_1LANE_M_CLK,
+ GCC_SNOC_PCIE1_1LANE_S_CLK,
+ GCC_ANOC_PCIE2_2LANE_M_CLK,
+ GCC_SNOC_PCIE2_2LANE_S_CLK,
+ GCC_ANOC_PCIE3_2LANE_M_CLK,
+ GCC_SNOC_PCIE3_2LANE_S_CLK,
+ GCC_SNOC_USB_CLK,
+ GCC_ANOC_USB_AXI_CLK,
+ GCC_NSSNOC_NSSCC_CLK,
+ GCC_NSSNOC_SNOC_CLK,
+ GCC_NSSNOC_SNOC_1_CLK,
+ GCC_NSSNOC_PCNOC_1_CLK,
+ GCC_NSSNOC_QOSGEN_REF_CLK,
+ GCC_NSSNOC_TIMEOUT_REF_CLK,
+ GCC_NSSNOC_XO_DCD_CLK,
+ GCC_NSSNOC_ATB_CLK,
+ GCC_MEM_NOC_NSSNOC_CLK,
+ GCC_NSSNOC_MEMNOC_CLK,
+ GCC_NSSNOC_MEM_NOC_1_CLK,
+};
+
static const struct of_device_id gcc_ipq9574_match_table[] = {
{ .compatible = "qcom,ipq9574-gcc" },
{ }
@@ -4327,7 +4357,40 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
static int gcc_ipq9574_probe(struct platform_device *pdev)
{
- return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
+ int ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
+ struct icc_provider *provider;
+ struct icc_clk_data *icd;
+ int i;
+
+ if (ret)
+ return dev_err_probe(&pdev->dev, ret, "%s failed\n", __func__);
+
+ icd = devm_kmalloc(&pdev->dev, ARRAY_SIZE(noc_clks) * sizeof(*icd),
+ GFP_KERNEL);
+
+ if (IS_ERR_OR_NULL(icd))
+ return dev_err_probe(&pdev->dev, PTR_ERR(icd),
+ "%s malloc failed\n", __func__);
+
+ icc_ipq9574 = icd;
+
+ for (i = 0; i < ARRAY_SIZE(noc_clks); i++, icd++) {
+ icd->clk = gcc_ipq9574_clks[noc_clks[i]]->hw.clk;
+ if (IS_ERR_OR_NULL(icd->clk)) {
+ dev_err(&pdev->dev, "%s: %d clock not found\n",
+ __func__, noc_clks[i]);
+ return -ENOENT;
+ }
+ icd->name = clk_hw_get_name(&gcc_ipq9574_clks[noc_clks[i]]->hw);
+ }
+
+ provider = icc_clk_register(&pdev->dev, IPQ_APPS_ID,
+ ARRAY_SIZE(noc_clks), icc_ipq9574);
+ if (IS_ERR_OR_NULL(provider))
+ return dev_err_probe(&pdev->dev, PTR_ERR(provider),
+ "%s: icc_clk_register failed\n", __func__);
+
+ return 0;
}
static struct platform_driver gcc_ipq9574_driver = {
--
2.34.1
IPQ SoCs dont involve RPM in managing NoC related clocks and
there is no NoC scaling. Linux itself handles these clocks.
However, these should not be exposed as just clocks and align
with other Qualcomm SoCs that handle these clocks from a
interconnect provider.
Hence include icc provider capability to the gcc node so that
peripherals can use the interconnect facility to enable these
clocks.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
v2: Fix include file order
Move to separate patch
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 7f2e5cbf3bbb..5b3e69379b1f 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq9574-gcc.h>
+#include <dt-bindings/interconnect/qcom,ipq9574.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/qcom,ipq9574-gcc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -306,6 +307,7 @@ gcc: clock-controller@1800000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ #interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
--
2.34.1
On 25.03.2024 11:20 AM, Varadarajan Narayanan wrote:
> Unlike MSM platforms that manage NoC related clocks and scaling
> from RPM, IPQ SoCs dont involve RPM in managing NoC related
> clocks and there is no NoC scaling.
>
> However, there is a requirement to enable some NoC interface
> clocks for accessing the peripheral controllers present on
> these NoCs. Though exposing these as normal clocks would work,
> having a minimalistic interconnect driver to handle these clocks
> would make it consistent with other Qualcomm platforms resulting
> in common code paths. This is similar to msm8996-cbf's usage of
> icc-clk framework.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
[...]
>
> +
> +static struct icc_clk_data *icc_ipq9574;
> +
What does this help achieve?
[...]
> +static int noc_clks[] = {
We could probably use indexed identifiers here to avoid confusion:
[ICC_BINDING_NAME] = CLK_BINDING_NAME
> static int gcc_ipq9574_probe(struct platform_device *pdev)
> {
> - return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> + int ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> + struct icc_provider *provider;
> + struct icc_clk_data *icd;
> + int i;
> +
> + if (ret)
I'd personally prefer if you left ret uninitialized and assigned it
above the if-statement.
> + return dev_err_probe(&pdev->dev, ret, "%s failed\n", __func__);
Please avoid the use of __func__ throughout your change and write
a more useful error message.
> +
> + icd = devm_kmalloc(&pdev->dev, ARRAY_SIZE(noc_clks) * sizeof(*icd),
> + GFP_KERNEL);
devm_kcalloc
> +
> + if (IS_ERR_OR_NULL(icd))
> + return dev_err_probe(&pdev->dev, PTR_ERR(icd),
> + "%s malloc failed\n", __func__);
ditto
> +
> + icc_ipq9574 = icd;
> +
> + for (i = 0; i < ARRAY_SIZE(noc_clks); i++, icd++) {
> + icd->clk = gcc_ipq9574_clks[noc_clks[i]]->hw.clk;
> + if (IS_ERR_OR_NULL(icd->clk)) {
> + dev_err(&pdev->dev, "%s: %d clock not found\n",
> + __func__, noc_clks[i]);
> + return -ENOENT;
return dev_err_probe
> + }
> + icd->name = clk_hw_get_name(&gcc_ipq9574_clks[noc_clks[i]]->hw);
> + }
> +
> + provider = icc_clk_register(&pdev->dev, IPQ_APPS_ID,
> + ARRAY_SIZE(noc_clks), icc_ipq9574);
> + if (IS_ERR_OR_NULL(provider))
> + return dev_err_probe(&pdev->dev, PTR_ERR(provider),
> + "%s: icc_clk_register failed\n", __func__);
ditto
On a second thought, since I'm assuming you're going to expand this to other
IPQ SoCs, it might be useful to factor this out into drivers/clk/qcom/common.c
Konrad
On Mon, Mar 25, 2024 at 08:42:21PM +0100, Konrad Dybcio wrote:
> On 25.03.2024 11:20 AM, Varadarajan Narayanan wrote:
> > Unlike MSM platforms that manage NoC related clocks and scaling
> > from RPM, IPQ SoCs dont involve RPM in managing NoC related
> > clocks and there is no NoC scaling.
> >
> > However, there is a requirement to enable some NoC interface
> > clocks for accessing the peripheral controllers present on
> > these NoCs. Though exposing these as normal clocks would work,
> > having a minimalistic interconnect driver to handle these clocks
> > would make it consistent with other Qualcomm platforms resulting
> > in common code paths. This is similar to msm8996-cbf's usage of
> > icc-clk framework.
> >
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
>
> [...]
>
> >
> > +
> > +static struct icc_clk_data *icc_ipq9574;
> > +
>
> What does this help achieve?
Had it as a place holder in case if the provider pointer is needed
for any debug. Will remove it.
> > +static int noc_clks[] = {
>
> We could probably use indexed identifiers here to avoid confusion:
> [ICC_BINDING_NAME] = CLK_BINDING_NAME
ok.
> > static int gcc_ipq9574_probe(struct platform_device *pdev)
> > {
> > - return qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> > + int ret = qcom_cc_probe(pdev, &gcc_ipq9574_desc);
> > + struct icc_provider *provider;
> > + struct icc_clk_data *icd;
> > + int i;
> > +
> > + if (ret)
>
> I'd personally prefer if you left ret uninitialized and assigned it
> above the if-statement.
ok
> > + return dev_err_probe(&pdev->dev, ret, "%s failed\n", __func__);
>
> Please avoid the use of __func__ throughout your change and write
> a more useful error message.
>
> > +
> > + icd = devm_kmalloc(&pdev->dev, ARRAY_SIZE(noc_clks) * sizeof(*icd),
> > + GFP_KERNEL);
>
> devm_kcalloc
ok
> > +
> > + if (IS_ERR_OR_NULL(icd))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(icd),
> > + "%s malloc failed\n", __func__);
>
> ditto
ok
> > +
> > + icc_ipq9574 = icd;
> > +
> > + for (i = 0; i < ARRAY_SIZE(noc_clks); i++, icd++) {
> > + icd->clk = gcc_ipq9574_clks[noc_clks[i]]->hw.clk;
> > + if (IS_ERR_OR_NULL(icd->clk)) {
> > + dev_err(&pdev->dev, "%s: %d clock not found\n",
> > + __func__, noc_clks[i]);
> > + return -ENOENT;
>
> return dev_err_probe
ok
> > + }
> > + icd->name = clk_hw_get_name(&gcc_ipq9574_clks[noc_clks[i]]->hw);
> > + }
> > +
> > + provider = icc_clk_register(&pdev->dev, IPQ_APPS_ID,
> > + ARRAY_SIZE(noc_clks), icc_ipq9574);
> > + if (IS_ERR_OR_NULL(provider))
> > + return dev_err_probe(&pdev->dev, PTR_ERR(provider),
> > + "%s: icc_clk_register failed\n", __func__);
>
> ditto
ok
> On a second thought, since I'm assuming you're going to expand this to other
> IPQ SoCs, it might be useful to factor this out into drivers/clk/qcom/common.c
Will move it.
Thanks
Varada
On 25/03/2024 11:20, Varadarajan Narayanan wrote:
> Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> interfaces. This will be used by the gcc-ipq9574 driver
> that will for providing interconnect services using the
> icc-clk framework.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> v2: Rename master slave macros
> Fix license identifier
Both patches should be squashed. Header is parts of bindings and your
previous patch adds the interconnects, doesn't it?
> ---
> .../dt-bindings/interconnect/qcom,ipq9574.h | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
>
> diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
> new file mode 100644
> index 000000000000..b7b32aa6bbb1
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +#ifndef INTERCONNECT_QCOM_IPQ9574_H
> +#define INTERCONNECT_QCOM_IPQ9574_H
> +
> +#define IPQ_APPS_ID 9574 /* some unique value */
Why random unique values are bindings? Why this cannot be 0? Please
explain how this is used by DTS and driver.
> +#define IPQ_NSS_ID (IPQ_APPS_ID * 2)
This does not seem right.
Best regards,
Krzysztof
On Tue, Mar 26, 2024 at 07:49:00AM +0100, Krzysztof Kozlowski wrote:
> On 25/03/2024 11:20, Varadarajan Narayanan wrote:
> > Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip
> > interfaces. This will be used by the gcc-ipq9574 driver
> > that will for providing interconnect services using the
> > icc-clk framework.
> >
> > Signed-off-by: Varadarajan Narayanan <[email protected]>
> > ---
> > v2: Rename master slave macros
> > Fix license identifier
>
> Both patches should be squashed. Header is parts of bindings and your
> previous patch adds the interconnects, doesn't it?
>
>
> > ---
> > .../dt-bindings/interconnect/qcom,ipq9574.h | 62 +++++++++++++++++++
> > 1 file changed, 62 insertions(+)
> > create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
> >
> > diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
> > new file mode 100644
> > index 000000000000..b7b32aa6bbb1
> > --- /dev/null
> > +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
> > @@ -0,0 +1,62 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> > +#ifndef INTERCONNECT_QCOM_IPQ9574_H
> > +#define INTERCONNECT_QCOM_IPQ9574_H
> > +
> > +#define IPQ_APPS_ID 9574 /* some unique value */
>
> Why random unique values are bindings? Why this cannot be 0? Please
> explain how this is used by DTS and driver.
This 'id' is not used by the driver or DTS. It is a unique id that
is initialized for the node by the interconnect driver framework.
A random value was chosen such that it does not conflict with an
already existing node id. Chose 9574 based on this comment from
clk-cbf-msm8996.c
/* Random ID that doesn't clash with main qnoc and OSM */
#define CBF_MASTER_NODE 2000
> > +#define IPQ_NSS_ID (IPQ_APPS_ID * 2)
>
> This does not seem right.
Doubled the NSS id so that APPS node ids dont clash.
Thanks
Varada
On 26/03/2024 09:59, Varadarajan Narayanan wrote:
>>> ---
>>> .../dt-bindings/interconnect/qcom,ipq9574.h | 62 +++++++++++++++++++
>>> 1 file changed, 62 insertions(+)
>>> create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h
>>>
>>> diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h
>>> new file mode 100644
>>> index 000000000000..b7b32aa6bbb1
>>> --- /dev/null
>>> +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h
>>> @@ -0,0 +1,62 @@
>>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>>> +#ifndef INTERCONNECT_QCOM_IPQ9574_H
>>> +#define INTERCONNECT_QCOM_IPQ9574_H
>>> +
>>> +#define IPQ_APPS_ID 9574 /* some unique value */
>>
>> Why random unique values are bindings? Why this cannot be 0? Please
>> explain how this is used by DTS and driver.
>
> This 'id' is not used by the driver or DTS. It is a unique id that
Then it is not a binding really.
Don't put driver stuff to bindings.
Best regards,
Krzysztof