Hi,
These patches adds support for USB host on the DRA7-evm board.
The USB host port (USB2) is tested and works fine.
The USB OTG port (USB1) is still not functional in OTG mode as it is missing
ID pin routing and mailbox write. However, you can get just the host mode to
work by explicitely setting this port to "host" mode.
Patches are based on v3.11-rc3 dra7 baseport tree [1], with balbi/next
merged on top and the control-usb multiple instance support [2].
NOTE: It also needs a patch [3] which allows us to operate at lower then
Super Speed mode. This patch is still in transition.
Patches in this series can be obtained from branch
usbhost-dra7-3.11-rc3
in git tree
git://github.com/rogerq/linux.git
cheers,
-roger
[1] - dra7 base tree
https://github.com/lokeshvutla/linux/tree/dra7-3.11-rc3-base
[2] - multiple control-usb instances
https://github.com/rogerq/linux/tree/usb-control-module
[3] - usb: dwc3: core: make USB3 PHY optional
https://github.com/rogerq/linux/commit/290955f6b4d1f2d6d466732c6ec92d009500fb67
Roger Quadros (4):
CLK: ti: dra7: Initialize USB_DPLL
ARM: dts: dra7: Add USB related nodes
dts: dra7-evm: add USB support
ARM: DRA7: hwmod: Add SYSCONFIG for usb_otg_ss
arch/arm/boot/dts/dra7-evm.dts | 22 +++++
arch/arm/boot/dts/dra7.dtsi | 136 +++++++++++++++++++++++++++++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 +++
drivers/clk/omap/clk-7xx.c | 11 +++
4 files changed, 181 insertions(+), 0 deletions(-)
--
1.7.4.1
USB_DPLL must be initialized and locked at boot so that
USB modules can work.
Also program USB_DLL_M2 output to half rate.
Signed-off-by: Roger Quadros <[email protected]>
---
drivers/clk/omap/clk-7xx.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
index ddb39dd..f444513 100644
--- a/drivers/clk/omap/clk-7xx.c
+++ b/drivers/clk/omap/clk-7xx.c
@@ -19,6 +19,7 @@
#define DRA7_DPLL_ABE_DEFFREQ 361267200
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+#define DRA7_DPLL_USB_DEFFREQ 960000000
static struct omap_dt_clk dra7xx_clks[] = {
@@ -63,5 +64,15 @@ int __init dra7xx_clk_init(void)
if (rc)
pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
+ dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
+ if (rc)
+ pr_err("%s: failed to configure USB DPLL!\n", __func__);
+
+ dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
+ rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
+ if (rc)
+ pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+
return rc;
}
--
1.7.4.1
Add the sysconfig class bits for the Super Speed USB
controllers
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index f647998b..e8d9f38 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1732,8 +1732,20 @@ static struct omap_hwmod dra7xx_uart6_hwmod = {
*
*/
+static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
.name = "usb_otg_ss",
+ .sysc = &dra7xx_usb_otg_ss_sysc,
};
/* usb_otg_ss1 */
--
1.7.4.1
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/dra7.dtsi | 136 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 136 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ce9a0f0..3a2e55e 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -484,6 +484,142 @@
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
+
+ omap_control_usb2phy1: omap-control-usb@4a002300 {
+ compatible = "ti,omap-control-usb";
+ reg = <0x4a002300 0x4>;
+ reg-names = "power";
+ ti,type = <2>;
+ };
+
+ omap_control_usb3phy1: omap-control-usb@4a002370 {
+ compatible = "ti,omap-control-usb";
+ reg = <0x4a002370 0x4>;
+ reg-names = "power";
+ ti,type = <3>;
+ };
+
+ omap_control_usb2phy2: omap-control-usb@0x4a002e74 {
+ compatible = "ti,omap-control-usb";
+ reg = <0x4a002e74 0x4>, <0x4a0086c0 0x4>;
+ reg-names = "power", "power_aux";
+ ti,type = <4>;
+ };
+
+ ocp2scp {
+ compatible = "ti,omap-ocp2scp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "ocp2scp1";
+
+ usb2_phy1: usb2phy1@4a084000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a084000 0x400>;
+ ctrl-module = <&omap_control_usb2phy1>;
+ clocks = <&usb_otg_ss1_refclk960m>, <&usb_phy1_always_on_clk32k>;
+ clock-names = "usb_otg_ss_refclk960m", "usb_phy_cm_clk32k";
+ };
+
+ usb2_phy2: usb2phy2@4a085000 {
+ compatible = "ti,omap-usb2";
+ reg = <0x4a085000 0x400>;
+ ctrl-module = <&omap_control_usb2phy2>;
+ clocks = <&usb_otg_ss2_refclk960m>, <&usb_phy2_always_on_clk32k>;
+ clock-names = "usb_otg_ss_refclk960m", "usb_phy_cm_clk32k";
+ };
+
+ usb3_phy1: usb3phy@4a084400 {
+ compatible = "ti,omap-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ ctrl-module = <&omap_control_usb3phy1>;
+ clocks = <&usb_otg_ss1_refclk960m>, <&usb_phy3_always_on_clk32k>;
+ clock-names = "usb_otg_ss_refclk960m", "usb_phy_cm_clk32k";
+ };
+ };
+
+ omap_dwc3_1@48880000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss1";
+ reg = <0x48880000 0x10000>;
+ interrupts = <0 77 4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ dwc3_1: dwc3@48890000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x48890000 0x17000>;
+ interrupts = <0 76 4>;
+ usb-phy = <&usb2_phy1>, <&usb3_phy1>;
+ tx-fifo-resize;
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ omap_dwc3_2@488c0000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss2";
+ reg = <0x488c0000 0x10000>;
+ interrupts = <0 92 4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ dwc3_2: dwc3@488d0000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x488d0000 0x17000>;
+ interrupts = <0 78 4>;
+ usb-phy = <&usb2_phy2>;
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
+ omap_dwc3_3@48900000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss3";
+ reg = <0x48900000 0x10000>;
+ /* interrupts = <0 TBD 4>; */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ dwc3_3: dwc3@48910000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x48910000 0x17000>;
+ /* interrupts = <0 93 4>; */
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ omap_dwc3_4@48940000 {
+ compatible = "ti,dwc3";
+ ti,hwmods = "usb_otg_ss4";
+ reg = <0x48940000 0x10000>;
+ /* interrupts = <0 TBD 4>; */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ dwc3_4: dwc3@48950000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x48950000 0x17000>;
+ /* interrupts = <0 TBD 4>; */
+ tx-fifo-resize;
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+
};
clocks {
--
1.7.4.1
Add USB drv_vbus pinctrl information and USB mode
for the USB controller.
Signed-off-by: Roger Quadros <[email protected]>
---
arch/arm/boot/dts/dra7-evm.dts | 22 ++++++++++++++++++++++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index cb0703c..acd3c09 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -18,3 +18,25 @@
reg = <0x80000000 0x60000000>; /* 1536 MB */
};
};
+
+&dra7_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &usb_pins
+ >;
+
+ usb_pins: pinmux_usb_pins {
+ pinctrl-single,pins = <
+ 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+ 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
+ >;
+ };
+};
+
+&dwc3_1 {
+ dr_mode = "otg";
+};
+
+&dwc3_2 {
+ dr_mode = "host";
+};
--
1.7.4.1
On 08/01/2013 09:58 AM, Roger Quadros wrote:
> USB_DPLL must be initialized and locked at boot so that
> USB modules can work.
>
> Also program USB_DLL_M2 output to half rate.
>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> drivers/clk/omap/clk-7xx.c | 11 +++++++++++
> 1 files changed, 11 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
> index ddb39dd..f444513 100644
> --- a/drivers/clk/omap/clk-7xx.c
> +++ b/drivers/clk/omap/clk-7xx.c
> @@ -19,6 +19,7 @@
>
> #define DRA7_DPLL_ABE_DEFFREQ 361267200
> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
> +#define DRA7_DPLL_USB_DEFFREQ 960000000
>
>
> static struct omap_dt_clk dra7xx_clks[] = {
> @@ -63,5 +64,15 @@ int __init dra7xx_clk_init(void)
> if (rc)
> pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>
> + dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
> + if (rc)
> + pr_err("%s: failed to configure USB DPLL!\n", __func__);
> +
> + dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
> + if (rc)
> + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
> +
> return rc;
> }
>
As I had mentioned on [1] - we are going to see similar needs keep
popping up. there is no need to hack this up for even more peripherals :(
http://marc.info/?l=linux-omap&m=137536803106017&w=2
--
Regards,
Nishanth Menon
Hi Nishant,
On 08/01/2013 06:06 PM, Nishanth Menon wrote:
> On 08/01/2013 09:58 AM, Roger Quadros wrote:
>> USB_DPLL must be initialized and locked at boot so that
>> USB modules can work.
>>
>> Also program USB_DLL_M2 output to half rate.
>>
>> Signed-off-by: Roger Quadros <[email protected]>
>> ---
>> drivers/clk/omap/clk-7xx.c | 11 +++++++++++
>> 1 files changed, 11 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
>> index ddb39dd..f444513 100644
>> --- a/drivers/clk/omap/clk-7xx.c
>> +++ b/drivers/clk/omap/clk-7xx.c
>> @@ -19,6 +19,7 @@
>>
>> #define DRA7_DPLL_ABE_DEFFREQ 361267200
>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>> +#define DRA7_DPLL_USB_DEFFREQ 960000000
>>
>>
>> static struct omap_dt_clk dra7xx_clks[] = {
>> @@ -63,5 +64,15 @@ int __init dra7xx_clk_init(void)
>> if (rc)
>> pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>>
>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
>> + if (rc)
>> + pr_err("%s: failed to configure USB DPLL!\n", __func__);
>> +
>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
>> + if (rc)
>> + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
>> +
>> return rc;
>> }
>>
> As I had mentioned on [1] - we are going to see similar needs keep popping up. there is no need to hack this up for even more peripherals :(
>
> http://marc.info/?l=linux-omap&m=137536803106017&w=2
>
The DPLLs need to be initialized irrespective of whether peripheral drivers are present or not.
We have seen cases where the SoC fails to enter RETention if the DPLLS are not correctly
configured.
But I agree with you that we should be able to initialize it by specifying the initial rate via Clock Data.
This patch can be removed when the appropriate feature is added in OMAP clock core.
cheers,
-roger
On 08/02/2013 10:30 AM, Roger Quadros wrote:
> Hi Nishant,
>
> On 08/01/2013 06:06 PM, Nishanth Menon wrote:
>> On 08/01/2013 09:58 AM, Roger Quadros wrote:
>>> USB_DPLL must be initialized and locked at boot so that
>>> USB modules can work.
>>>
>>> Also program USB_DLL_M2 output to half rate.
>>>
>>> Signed-off-by: Roger Quadros <[email protected]>
>>> ---
>>> drivers/clk/omap/clk-7xx.c | 11 +++++++++++
>>> 1 files changed, 11 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
>>> index ddb39dd..f444513 100644
>>> --- a/drivers/clk/omap/clk-7xx.c
>>> +++ b/drivers/clk/omap/clk-7xx.c
>>> @@ -19,6 +19,7 @@
>>>
>>> #define DRA7_DPLL_ABE_DEFFREQ 361267200
>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>> +#define DRA7_DPLL_USB_DEFFREQ 960000000
>>>
>>>
>>> static struct omap_dt_clk dra7xx_clks[] = {
>>> @@ -63,5 +64,15 @@ int __init dra7xx_clk_init(void)
>>> if (rc)
>>> pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>>>
>>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
>>> + if (rc)
>>> + pr_err("%s: failed to configure USB DPLL!\n", __func__);
>>> +
>>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
>>> + if (rc)
>>> + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
>>> +
>>> return rc;
>>> }
>>>
>> As I had mentioned on [1] - we are going to see similar needs keep popping up. there is no need to hack this up for even more peripherals :(
>>
>> http://marc.info/?l=linux-omap&m=137536803106017&w=2
>>
> The DPLLs need to be initialized irrespective of whether peripheral drivers are present or not.
> We have seen cases where the SoC fails to enter RETention if the DPLLS are not correctly
> configured.
>
> But I agree with you that we should be able to initialize it by specifying the initial rate via Clock Data.
>
> This patch can be removed when the appropriate feature is added in OMAP clock core.
... not OMAP clock core, I would say clock core. This is again a feature
we can work with once we have initial support in place.
-Tero
On 08/02/2013 05:57 AM, Tero Kristo wrote:
> On 08/02/2013 10:30 AM, Roger Quadros wrote:
>> Hi Nishant,
>>
>> On 08/01/2013 06:06 PM, Nishanth Menon wrote:
>>> On 08/01/2013 09:58 AM, Roger Quadros wrote:
>>>> USB_DPLL must be initialized and locked at boot so that
>>>> USB modules can work.
>>>>
>>>> Also program USB_DLL_M2 output to half rate.
>>>>
>>>> Signed-off-by: Roger Quadros <[email protected]>
>>>> ---
>>>> drivers/clk/omap/clk-7xx.c | 11 +++++++++++
>>>> 1 files changed, 11 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/omap/clk-7xx.c b/drivers/clk/omap/clk-7xx.c
>>>> index ddb39dd..f444513 100644
>>>> --- a/drivers/clk/omap/clk-7xx.c
>>>> +++ b/drivers/clk/omap/clk-7xx.c
>>>> @@ -19,6 +19,7 @@
>>>>
>>>> #define DRA7_DPLL_ABE_DEFFREQ 361267200
>>>> #define DRA7_DPLL_GMAC_DEFFREQ 1000000000
>>>> +#define DRA7_DPLL_USB_DEFFREQ 960000000
>>>>
>>>>
>>>> static struct omap_dt_clk dra7xx_clks[] = {
>>>> @@ -63,5 +64,15 @@ int __init dra7xx_clk_init(void)
>>>> if (rc)
>>>> pr_err("%s: failed to configure GMAC DPLL!\n", __func__);
>>>>
>>>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
>>>> + if (rc)
>>>> + pr_err("%s: failed to configure USB DPLL!\n", __func__);
>>>> +
>>>> + dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
>>>> + rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
>>>> + if (rc)
>>>> + pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
>>>> +
>>>> return rc;
>>>> }
>>>>
>>> As I had mentioned on [1] - we are going to see similar needs keep
>>> popping up. there is no need to hack this up for even more
>>> peripherals :(
>>>
>>> http://marc.info/?l=linux-omap&m=137536803106017&w=2
>>>
>> The DPLLs need to be initialized irrespective of whether peripheral
>> drivers are present or not.
>> We have seen cases where the SoC fails to enter RETention if the DPLLS
>> are not correctly
>> configured.
>>
>> But I agree with you that we should be able to initialize it by
>> specifying the initial rate via Clock Data.
>>
>> This patch can be removed when the appropriate feature is added in
>> OMAP clock core.
>
> ... not OMAP clock core, I would say clock core. This is again a feature
> we can work with once we have initial support in place.
OK. /me gives up for now. but please squash this into your set.
--
Regards,
Nishanth Menon
On 8/1/2013 8:28 PM, Roger Quadros wrote:
> Add nodes for the Super Speed USB controllers, omap-control-usb,
> USB2 PHY and USB3 PHY devices.
>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> arch/arm/boot/dts/dra7.dtsi | 136 +++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 136 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index ce9a0f0..3a2e55e 100644
<snip>
> + omap_dwc3_1@48880000 {
How about usb1: omap_dwc3@48880000 {
usb2: omap_dwc3@488c0000 { etc.
> + compatible = "ti,dwc3";
> + ti,hwmods = "usb_otg_ss1";
> + reg = <0x48880000 0x10000>;
> + interrupts = <0 77 4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + utmi-mode = <2>;
> + ranges;
> + dwc3_1: dwc3@48890000 {
> + compatible = "synopsys,dwc3";
> + reg = <0x48890000 0x17000>;
> + interrupts = <0 76 4>;
> + usb-phy = <&usb2_phy1>, <&usb3_phy1>;
> + tx-fifo-resize;
> + maximum-speed = "super-speed";
> + dr_mode = "otg";
> + };
> + };
> +
> + omap_dwc3_2@488c0000 {
> + compatible = "ti,dwc3";
> + ti,hwmods = "usb_otg_ss2";
> + reg = <0x488c0000 0x10000>;
> + interrupts = <0 92 4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + utmi-mode = <2>;
> + ranges;
> + dwc3_2: dwc3@488d0000 {
> + compatible = "synopsys,dwc3";
> + reg = <0x488d0000 0x17000>;
> + interrupts = <0 78 4>;
> + usb-phy = <&usb2_phy2>;
> + tx-fifo-resize;
> + maximum-speed = "high-speed";
> + dr_mode = "otg";
> + };
> + };
> +
> + /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
> + omap_dwc3_3@48900000 {
> + compatible = "ti,dwc3";
> + ti,hwmods = "usb_otg_ss3";
> + reg = <0x48900000 0x10000>;
> + /* interrupts = <0 TBD 4>; */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + utmi-mode = <2>;
> + ranges;
> + dwc3_3: dwc3@48910000 {
> + compatible = "synopsys,dwc3";
> + reg = <0x48910000 0x17000>;
> + /* interrupts = <0 93 4>; */
> + tx-fifo-resize;
> + maximum-speed = "high-speed";
> + dr_mode = "otg";
> + };
> + };
> +
> + omap_dwc3_4@48940000 {
> + compatible = "ti,dwc3";
> + ti,hwmods = "usb_otg_ss4";
> + reg = <0x48940000 0x10000>;
> + /* interrupts = <0 TBD 4>; */
> + #address-cells = <1>;
> + #size-cells = <1>;
> + utmi-mode = <2>;
> + ranges;
> + dwc3_4: dwc3@48950000 {
> + compatible = "synopsys,dwc3";
> + reg = <0x48950000 0x17000>;
> + /* interrupts = <0 TBD 4>; */
> + tx-fifo-resize;
> + maximum-speed = "high-speed";
> + dr_mode = "otg";
> + };
> + };
> +
> };
>
> clocks {
--
-George
On 8/1/2013 8:28 PM, Roger Quadros wrote:
> Add USB drv_vbus pinctrl information and USB mode
> for the USB controller.
>
> Signed-off-by: Roger Quadros <[email protected]>
> ---
> arch/arm/boot/dts/dra7-evm.dts | 22 ++++++++++++++++++++++
> 1 files changed, 22 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
> index cb0703c..acd3c09 100644
> --- a/arch/arm/boot/dts/dra7-evm.dts
> +++ b/arch/arm/boot/dts/dra7-evm.dts
> @@ -18,3 +18,25 @@
> reg = <0x80000000 0x60000000>; /* 1536 MB */
> };
> };
> +
> +&dra7_pmx_core {
> + pinctrl-names = "default";
> + pinctrl-0 = <
> + &usb_pins
> + >;
> +
> + usb_pins: pinmux_usb_pins {
> + pinctrl-single,pins = <
> + 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
> + 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
> + >;
> + };
> +};
> +
> +&dwc3_1 {
> + dr_mode = "otg";
otg???
> +};
> +
> +&dwc3_2 {
> + dr_mode = "host";
> +};
--
-George
On 08/02/2013 06:02 PM, George Cherian wrote:
> On 8/1/2013 8:28 PM, Roger Quadros wrote:
>> Add nodes for the Super Speed USB controllers, omap-control-usb,
>> USB2 PHY and USB3 PHY devices.
>>
>> Signed-off-by: Roger Quadros <[email protected]>
>> ---
>> arch/arm/boot/dts/dra7.dtsi | 136 +++++++++++++++++++++++++++++++++++++++++++
>> 1 files changed, 136 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
>> index ce9a0f0..3a2e55e 100644
>
> <snip>
>
>> + omap_dwc3_1@48880000 {
>
> How about usb1: omap_dwc3@48880000 {
> usb2: omap_dwc3@488c0000 { etc.
>
Yes. will update it in next revision.
cheers,
-roger
On 08/02/2013 06:04 PM, George Cherian wrote:
> On 8/1/2013 8:28 PM, Roger Quadros wrote:
>> Add USB drv_vbus pinctrl information and USB mode
>> for the USB controller.
>>
>> Signed-off-by: Roger Quadros <[email protected]>
>> ---
>> arch/arm/boot/dts/dra7-evm.dts | 22 ++++++++++++++++++++++
>> 1 files changed, 22 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>> index cb0703c..acd3c09 100644
>> --- a/arch/arm/boot/dts/dra7-evm.dts
>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>> @@ -18,3 +18,25 @@
>> reg = <0x80000000 0x60000000>; /* 1536 MB */
>> };
>> };
>> +
>> +&dra7_pmx_core {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <
>> + &usb_pins
>> + >;
>> +
>> + usb_pins: pinmux_usb_pins {
>> + pinctrl-single,pins = <
>> + 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
>> + 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
>> + >;
>> + };
>> +};
>> +
>> +&dwc3_1 {
>> + dr_mode = "otg";
>
> otg???
What's wrong there?
please see
Documentation/devicetree/bindings/usb/generic.txt
we want it to operate in dual role mode and hence "otg"
cheers,
-roger
On 8/5/2013 1:25 PM, Roger Quadros wrote:
> On 08/02/2013 06:04 PM, George Cherian wrote:
>> On 8/1/2013 8:28 PM, Roger Quadros wrote:
>>> Add USB drv_vbus pinctrl information and USB mode
>>> for the USB controller.
>>>
>>> Signed-off-by: Roger Quadros <[email protected]>
>>> ---
>>> arch/arm/boot/dts/dra7-evm.dts | 22 ++++++++++++++++++++++
>>> 1 files changed, 22 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>>> index cb0703c..acd3c09 100644
>>> --- a/arch/arm/boot/dts/dra7-evm.dts
>>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>>> @@ -18,3 +18,25 @@
>>> reg = <0x80000000 0x60000000>; /* 1536 MB */
>>> };
>>> };
>>> +
>>> +&dra7_pmx_core {
>>> + pinctrl-names = "default";
>>> + pinctrl-0 = <
>>> + &usb_pins
>>> + >;
>>> +
>>> + usb_pins: pinmux_usb_pins {
>>> + pinctrl-single,pins = <
>>> + 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
>>> + 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
>>> + >;
>>> + };
>>> +};
>>> +
>>> +&dwc3_1 {
>>> + dr_mode = "otg";
>> otg???
> What's wrong there?
> please see
> Documentation/devicetree/bindings/usb/generic.txt
>
> we want it to operate in dual role mode and hence "otg"
Am sorry for not being clear with my earlier comment.
I meant whether we have otg/ DRD working. Till then shouldnt we put
either peripheral/host?
> cheers,
> -roger
--
-George
On 08/05/2013 12:03 PM, George Cherian wrote:
> On 8/5/2013 1:25 PM, Roger Quadros wrote:
>> On 08/02/2013 06:04 PM, George Cherian wrote:
>>> On 8/1/2013 8:28 PM, Roger Quadros wrote:
>>>> Add USB drv_vbus pinctrl information and USB mode
>>>> for the USB controller.
>>>>
>>>> Signed-off-by: Roger Quadros <[email protected]>
>>>> ---
>>>> arch/arm/boot/dts/dra7-evm.dts | 22 ++++++++++++++++++++++
>>>> 1 files changed, 22 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
>>>> index cb0703c..acd3c09 100644
>>>> --- a/arch/arm/boot/dts/dra7-evm.dts
>>>> +++ b/arch/arm/boot/dts/dra7-evm.dts
>>>> @@ -18,3 +18,25 @@
>>>> reg = <0x80000000 0x60000000>; /* 1536 MB */
>>>> };
>>>> };
>>>> +
>>>> +&dra7_pmx_core {
>>>> + pinctrl-names = "default";
>>>> + pinctrl-0 = <
>>>> + &usb_pins
>>>> + >;
>>>> +
>>>> + usb_pins: pinmux_usb_pins {
>>>> + pinctrl-single,pins = <
>>>> + 0x280 0xc0000 /* usb1_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
>>>> + 0x284 0xc0000 /* usb2_drvvbus, SLOW_SLEW | PULLUPEN | MODE0 */
>>>> + >;
>>>> + };
>>>> +};
>>>> +
>>>> +&dwc3_1 {
>>>> + dr_mode = "otg";
>>> otg???
>> What's wrong there?
>> please see
>> Documentation/devicetree/bindings/usb/generic.txt
>>
>> we want it to operate in dual role mode and hence "otg"
>
> Am sorry for not being clear with my earlier comment.
> I meant whether we have otg/ DRD working. Till then shouldnt we put either peripheral/host?
Setting it to peripheral did not work and I don't think it is meant to be used as host port at all
so no point in setting it has host. Users needing host support can always use usb2 port.
The kit comes supplied with host adapter only for the usb2 (mini) port.
So I think we should just leave usb1 port OTG, and get it to work somehow, at least in peripheral mode
first.
cheers,
-roger