From: David Daney <[email protected]>
The Cavium, OCTEON is a MIPS based SoC. Here we add support for its
on-chip GPIO lines.
Changes from v1: Cleaned up variable names, messages and added some
comments as suggested by Linus Walleij.
The second patch depends on the first, but is in code maintained by
Ralf. It may be best to mrege both of these together, perhaps from
the GPIO tree, with Ralf's Acked-by.
David Daney (2):
MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB
gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
arch/mips/Kconfig | 1 +
arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 ++++
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-octeon.c | 157 ++++++++++++++++++++++++
5 files changed, 188 insertions(+)
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h
create mode 100644 drivers/gpio/gpio-octeon.c
--
1.7.11.7
From: David Daney <[email protected]>
The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
GPIO pins, this driver handles them all. Configuring the pins as
interrupt sources is handled elsewhere (OCTEON's irq handling code).
Signed-off-by: David Daney <[email protected]>
---
Device tree binding defintions already exist for this device in
Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
drivers/gpio/Kconfig | 8 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-octeon.c | 157 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 166 insertions(+)
create mode 100644 drivers/gpio/gpio-octeon.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b2450ba..b21b7a2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -193,6 +193,14 @@ config GPIO_MXS
select GPIO_GENERIC
select GENERIC_IRQ_CHIP
+config GPIO_OCTEON
+ tristate "Cavium OCTEON GPIO"
+ depends on GPIOLIB && CAVIUM_OCTEON_SOC
+ default y
+ help
+ Say yes here to support the on-chip GPIO lines on the OCTEON
+ family of SOCs.
+
config GPIO_PL061
bool "PrimeCell PL061 GPIO support"
depends on ARM && ARM_AMBA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ef3e983..e7fd980 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o
obj-$(CONFIG_GPIO_MVEBU) += gpio-mvebu.o
obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o
obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o
+obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o
obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o
obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
diff --git a/drivers/gpio/gpio-octeon.c b/drivers/gpio/gpio-octeon.c
new file mode 100644
index 0000000..71a4a31
--- /dev/null
+++ b/drivers/gpio/gpio-octeon.c
@@ -0,0 +1,157 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011, 2012 Cavium Inc.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-gpio-defs.h>
+
+#define RX_DAT 0x80
+#define TX_SET 0x88
+#define TX_CLEAR 0x90
+/*
+ * The address offset of the GPIO configuration register for a given
+ * line.
+ */
+static unsigned int bit_cfg_reg(unsigned int offset)
+{
+ /*
+ * The register stride is 8, with a discontinuity after the
+ * first 16.
+ */
+ if (offset < 16)
+ return 8 * offset;
+ else
+ return 8 * (offset - 16) + 0x100;
+}
+
+struct octeon_gpio {
+ struct gpio_chip chip;
+ u64 register_base;
+};
+
+static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+
+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
+ return 0;
+}
+
+static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 mask = 1ull << offset;
+ u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
+ cvmx_write_csr(reg, mask);
+}
+
+static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ union cvmx_gpio_bit_cfgx cfgx;
+
+ octeon_gpio_set(chip, offset, value);
+
+ cfgx.u64 = 0;
+ cfgx.s.tx_oe = 1;
+
+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
+ return 0;
+}
+
+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
+
+ return ((1ull << offset) & read_bits) != 0;
+}
+
+static int octeon_gpio_probe(struct platform_device *pdev)
+{
+ struct octeon_gpio *gpio;
+ struct gpio_chip *chip;
+ struct resource *res_mem;
+ int err = 0;
+
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+ chip = &gpio->chip;
+
+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (res_mem == NULL) {
+ dev_err(&pdev->dev, "found no memory resource\n");
+ err = -ENXIO;
+ goto out;
+ }
+ if (!devm_request_mem_region(&pdev->dev, res_mem->start,
+ resource_size(res_mem),
+ res_mem->name)) {
+ dev_err(&pdev->dev, "request_mem_region failed\n");
+ err = -ENXIO;
+ goto out;
+ }
+ gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
+ resource_size(res_mem));
+
+ pdev->dev.platform_data = chip;
+ chip->label = "octeon-gpio";
+ chip->dev = &pdev->dev;
+ chip->owner = THIS_MODULE;
+ chip->base = 0;
+ chip->can_sleep = 0;
+ chip->ngpio = 20;
+ chip->direction_input = octeon_gpio_dir_in;
+ chip->get = octeon_gpio_get;
+ chip->direction_output = octeon_gpio_dir_out;
+ chip->set = octeon_gpio_set;
+ err = gpiochip_add(chip);
+ if (err)
+ goto out;
+
+ dev_info(&pdev->dev, "OCTEON GPIO driver probed.\n");
+out:
+ return err;
+}
+
+static int octeon_gpio_remove(struct platform_device *pdev)
+{
+ struct gpio_chip *chip = pdev->dev.platform_data;
+ return gpiochip_remove(chip);
+}
+
+static struct of_device_id octeon_gpio_match[] = {
+ {
+ .compatible = "cavium,octeon-3860-gpio",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, octeon_gpio_match);
+
+static struct platform_driver octeon_gpio_driver = {
+ .driver = {
+ .name = "octeon_gpio",
+ .owner = THIS_MODULE,
+ .of_match_table = octeon_gpio_match,
+ },
+ .probe = octeon_gpio_probe,
+ .remove = octeon_gpio_remove,
+};
+
+module_platform_driver(octeon_gpio_driver);
+
+MODULE_DESCRIPTION("Cavium Inc. OCTEON GPIO Driver");
+MODULE_AUTHOR("David Daney");
+MODULE_LICENSE("GPL");
--
1.7.11.7
From: David Daney <[email protected]>
... and create asm/mach-cavium-octeon/gpio.h so that things continue
to build.
This allows us to use the existing I2C connected GPIO expanders.
Signed-off-by: David Daney <[email protected]>
---
arch/mips/Kconfig | 1 +
arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c3abed3..9c2293a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -731,6 +731,7 @@ config CAVIUM_OCTEON_SOC
select USB_ARCH_HAS_OHCI
select USB_ARCH_HAS_EHCI
select HOLES_IN_ZONE
+ select ARCH_REQUIRE_GPIOLIB
help
This option supports all of the Octeon reference boards from Cavium
Networks. It builds a kernel that dynamically determines the Octeon
diff --git a/arch/mips/include/asm/mach-cavium-octeon/gpio.h b/arch/mips/include/asm/mach-cavium-octeon/gpio.h
new file mode 100644
index 0000000..34e9f7a
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/gpio.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_MACH_CAVIUM_OCTEON_GPIO_H
+#define __ASM_MACH_CAVIUM_OCTEON_GPIO_H
+
+#ifdef CONFIG_GPIOLIB
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
+#else
+int gpio_request(unsigned gpio, const char *label);
+void gpio_free(unsigned gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_value(unsigned gpio, int value);
+#endif
+
+#include <asm-generic/gpio.h>
+
+#define gpio_to_irq __gpio_to_irq
+
+#endif /* __ASM_MACH_GENERIC_GPIO_H */
--
1.7.11.7
On 07/29/2013 02:29 PM, David Daney wrote:
> From: David Daney <[email protected]>
>
> The Cavium, OCTEON is a MIPS based SoC. Here we add support for its
> on-chip GPIO lines.
>
> Changes from v1: Cleaned up variable names, messages and added some
> comments as suggested by Linus Walleij.
>
> The second patch depends on the first, but is in code maintained by
> Ralf. It may be best to mrege both of these together, perhaps from
> the GPIO tree, with Ralf's Acked-by.
Really I meant to say that the first patch is in the MIPS tree, and
should be Acked-by Ralf, if that wasn't clear.
David Daney
>
> David Daney (2):
> MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB
> gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
>
> arch/mips/Kconfig | 1 +
> arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 ++++
> drivers/gpio/Kconfig | 8 ++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-octeon.c | 157 ++++++++++++++++++++++++
> 5 files changed, 188 insertions(+)
> create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h
> create mode 100644 drivers/gpio/gpio-octeon.c
>
On Mon, Jul 29, 2013 at 02:29:08PM -0700, David Daney wrote:
> From: David Daney <[email protected]>
>
> The Cavium, OCTEON is a MIPS based SoC. Here we add support for its
> on-chip GPIO lines.
>
> Changes from v1: Cleaned up variable names, messages and added some
> comments as suggested by Linus Walleij.
>
> The second patch depends on the first, but is in code maintained by
> Ralf. It may be best to mrege both of these together, perhaps from
> the GPIO tree, with Ralf's Acked-by.
Acked-by: Ralf Baechle <[email protected]>
Ralf
Ping.
Hi Linus,
I wonder if you have had a chance to look at these...
David Daney
On 07/29/2013 02:29 PM, David Daney wrote:
> From: David Daney <[email protected]>
>
> The Cavium, OCTEON is a MIPS based SoC. Here we add support for its
> on-chip GPIO lines.
>
> Changes from v1: Cleaned up variable names, messages and added some
> comments as suggested by Linus Walleij.
>
> The second patch depends on the first, but is in code maintained by
> Ralf. It may be best to mrege both of these together, perhaps from
> the GPIO tree, with Ralf's Acked-by.
>
> David Daney (2):
> MIPS: OCTEON: Select ARCH_REQUIRE_GPIOLIB
> gpio MIPS/OCTEON: Add a driver for OCTEON's on-chip GPIO pins.
>
> arch/mips/Kconfig | 1 +
> arch/mips/include/asm/mach-cavium-octeon/gpio.h | 21 ++++
> drivers/gpio/Kconfig | 8 ++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-octeon.c | 157 ++++++++++++++++++++++++
> 5 files changed, 188 insertions(+)
> create mode 100644 arch/mips/include/asm/mach-cavium-octeon/gpio.h
> create mode 100644 drivers/gpio/gpio-octeon.c
>
On Mon, Jul 29, 2013 at 11:29 PM, David Daney <[email protected]> wrote:
> From: David Daney <[email protected]>
>
> ... and create asm/mach-cavium-octeon/gpio.h so that things continue
> to build.
>
> This allows us to use the existing I2C connected GPIO expanders.
>
> Signed-off-by: David Daney <[email protected]>
I like the looks of this.
Acked-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 29, 2013 at 11:29 PM, David Daney <[email protected]> wrote:
> From: David Daney <[email protected]>
>
> The SOCs in the OCTEON family have 16 (or in some cases 20) on-chip
> GPIO pins, this driver handles them all. Configuring the pins as
> interrupt sources is handled elsewhere (OCTEON's irq handling code).
>
> Signed-off-by: David Daney <[email protected]>
> ---
>
> Device tree binding defintions already exist for this device in
> Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt
I like this.
Reviewed-by: Linus Walleij <[email protected]>
I guess you will merge both patches through the MIPS arch
tree?
Yours,
Linus Walleij
On 16/08/13 15:16, Linus Walleij wrote:
> I guess you will merge both patches through the MIPS arch
> tree?
Hi Linus,
sure, we can take them via the MIPS tree
John