The current logic that returns (sys_addr >> 8) & 0x7 when
num_dcts_intlv = 4 is incorrect. We should really be doing-
If intlv_addr = 0x4, then interleave on bits [9:8] and if
intlv_addr = 0x5, interleave on bits [10:9].
Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
(Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
Tested on F15 M30h with mce_inj module and patch did not cause
any regressions.
Signed-off-by: Aravind Gopalakrishnan <[email protected]>
---
drivers/edac/amd64_edac.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index b53d0de..ef9fe30 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1240,9 +1240,17 @@ static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
if (num_dcts_intlv == 2) {
select = (sys_addr >> 8) & 0x3;
channel = select ? 0x3 : 0;
- } else if (num_dcts_intlv == 4)
- channel = (sys_addr >> 8) & 0x7;
-
+ } else if (num_dcts_intlv == 4) {
+ u8 intlv_addr = dct_sel_interleave_addr(pvt);
+ switch (intlv_addr) {
+ case 0x4:
+ channel = (sys_addr >> 8) & 0x3;
+ break;
+ case 0x5:
+ channel = (sys_addr >> 9) & 0x3;
+ break;
+ }
+ }
return channel;
}
--
1.7.10.4
On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote:
> The current logic that returns (sys_addr >> 8) & 0x7 when
> num_dcts_intlv = 4 is incorrect. We should really be doing-
> If intlv_addr = 0x4, then interleave on bits [9:8] and if
> intlv_addr = 0x5, interleave on bits [10:9].
>
> Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
> (Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
>
> Tested on F15 M30h with mce_inj module and patch did not cause
> any regressions.
>
> Signed-off-by: Aravind Gopalakrishnan <[email protected]>
> ---
>
Ping..
-Aravind.
On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote:
> On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote:
> >The current logic that returns (sys_addr >> 8) & 0x7 when
> >num_dcts_intlv = 4 is incorrect. We should really be doing-
> >If intlv_addr = 0x4, then interleave on bits [9:8] and if
> >intlv_addr = 0x5, interleave on bits [10:9].
> >
> >Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
> >(Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
> >
> >Tested on F15 M30h with mce_inj module and patch did not cause
> >any regressions.
> >
> >Signed-off-by: Aravind Gopalakrishnan <[email protected]>
> >---
> >
>
> Ping..
I haven't forgotten you - it's just that I'm not taking any patches
during the merge window. Now that it is over, all is back to normal.
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--
On 2/3/2014 1:32 PM, Borislav Petkov wrote:
> On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote:
>> On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote:
>>> The current logic that returns (sys_addr >> 8) & 0x7 when
>>> num_dcts_intlv = 4 is incorrect. We should really be doing-
>>> If intlv_addr = 0x4, then interleave on bits [9:8] and if
>>> intlv_addr = 0x5, interleave on bits [10:9].
>>>
>>> Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
>>> (Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
>>>
>>> Tested on F15 M30h with mce_inj module and patch did not cause
>>> any regressions.
>>>
>>> Signed-off-by: Aravind Gopalakrishnan <[email protected]>
>>> ---
>>>
>> Ping..
> I haven't forgotten you - it's just that I'm not taking any patches
> during the merge window.
yes, I realised :)
Just noticed rc1 on kernel.org; hence the ping..
Thanks in advance
-Aravind.
On Tue, Jan 21, 2014 at 03:03:36PM -0600, Aravind Gopalakrishnan wrote:
> The current logic that returns (sys_addr >> 8) & 0x7 when
> num_dcts_intlv = 4 is incorrect. We should really be doing-
> If intlv_addr = 0x4, then interleave on bits [9:8] and if
> intlv_addr = 0x5, interleave on bits [10:9].
>
> Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)
> (Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
>
> Tested on F15 M30h with mce_inj module and patch did not cause
> any regressions.
>
> Signed-off-by: Aravind Gopalakrishnan <[email protected]>
Applied, thanks.
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
--