Hello,
This series rework the sunxi pinctrl driver to support the PLx pins
available on the A31 SoC.
It also add missing A31 reset controller DT bindings documentation.
I need those PL pins (actually I only need PL0 and PL1) to support
the P2WI bus, which in turn is used to communicate with the AXP221
PMIC.
Let me know if these changes are too intrusive.
Best Regards,
Boris
Boris BREZILLON (15):
ARM: sunxi: dt: list all pinctrl compatible strings
ARM: sunxi: dt: document pinctrl clock related properties
ARM: sunxi: dt: add pinctrl clock-names properties
pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk
clk: sunxi: add A31 APB0 clk gate defintions
clk: sunxi: add A31 APB0 gates compatible string to the documentation
ARM: sunxi: dt: define A31's APB0 clk gates node
reset: sunxi: document sunxi's reset controllers bindings
clk: sunxi: add A31 APB0 reset line defintions
pinctrl: sunxi: add PL pin definitions
pinctrl: sunxi: add support for A31 PL pins
pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC
pinctrl: sunxi: retrieve and enable PL reset line for A31 SoC
pinctrl: sunxi: define A31 PL0/PL1 pins
ARM: sunxi: dt: add support for A31's PL pins
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 13 +-
.../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++
arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
arch/arm/boot/dts/sun5i-a10s.dtsi | 1 +
arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 25 ++-
arch/arm/boot/dts/sun7i-a20.dtsi | 1 +
drivers/clk/sunxi/clk-sunxi.c | 5 +
drivers/pinctrl/pinctrl-sunxi-pins.h | 8 +
drivers/pinctrl/pinctrl-sunxi.c | 205 +++++++++++++++------
drivers/pinctrl/pinctrl-sunxi.h | 39 +++-
12 files changed, 264 insertions(+), 57 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
--
1.8.3.2
Define PL pin macros.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pinctrl/pinctrl-sunxi.h | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index 552b0e9..ef8890d 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -25,6 +25,7 @@
#define PG_BASE 192
#define PH_BASE 224
#define PI_BASE 256
+#define PL_BASE 352
#define SUNXI_PINCTRL_PIN_PA0 PINCTRL_PIN(PA_BASE + 0, "PA0")
#define SUNXI_PINCTRL_PIN_PA1 PINCTRL_PIN(PA_BASE + 1, "PA1")
@@ -323,6 +324,39 @@
#define SUNXI_PINCTRL_PIN_PI30 PINCTRL_PIN(PI_BASE + 30, "PI30")
#define SUNXI_PINCTRL_PIN_PI31 PINCTRL_PIN(PI_BASE + 31, "PI31")
+#define SUNXI_PINCTRL_PIN_PL0 PINCTRL_PIN(PL_BASE + 0, "PL0")
+#define SUNXI_PINCTRL_PIN_PL1 PINCTRL_PIN(PL_BASE + 1, "PL1")
+#define SUNXI_PINCTRL_PIN_PL2 PINCTRL_PIN(PL_BASE + 2, "PL2")
+#define SUNXI_PINCTRL_PIN_PL3 PINCTRL_PIN(PL_BASE + 3, "PL3")
+#define SUNXI_PINCTRL_PIN_PL4 PINCTRL_PIN(PL_BASE + 4, "PL4")
+#define SUNXI_PINCTRL_PIN_PL5 PINCTRL_PIN(PL_BASE + 5, "PL5")
+#define SUNXI_PINCTRL_PIN_PL6 PINCTRL_PIN(PL_BASE + 6, "PL6")
+#define SUNXI_PINCTRL_PIN_PL7 PINCTRL_PIN(PL_BASE + 7, "PL7")
+#define SUNXI_PINCTRL_PIN_PL8 PINCTRL_PIN(PL_BASE + 8, "PL8")
+#define SUNXI_PINCTRL_PIN_PL9 PINCTRL_PIN(PL_BASE + 9, "PL9")
+#define SUNXI_PINCTRL_PIN_PL10 PINCTRL_PIN(PL_BASE + 10, "PL10")
+#define SUNXI_PINCTRL_PIN_PL11 PINCTRL_PIN(PL_BASE + 11, "PL11")
+#define SUNXI_PINCTRL_PIN_PL12 PINCTRL_PIN(PL_BASE + 12, "PL12")
+#define SUNXI_PINCTRL_PIN_PL13 PINCTRL_PIN(PL_BASE + 13, "PL13")
+#define SUNXI_PINCTRL_PIN_PL14 PINCTRL_PIN(PL_BASE + 14, "PL14")
+#define SUNXI_PINCTRL_PIN_PL15 PINCTRL_PIN(PL_BASE + 15, "PL15")
+#define SUNXI_PINCTRL_PIN_PL16 PINCTRL_PIN(PL_BASE + 16, "PL16")
+#define SUNXI_PINCTRL_PIN_PL17 PINCTRL_PIN(PL_BASE + 17, "PL17")
+#define SUNXI_PINCTRL_PIN_PL18 PINCTRL_PIN(PL_BASE + 18, "PL18")
+#define SUNXI_PINCTRL_PIN_PL19 PINCTRL_PIN(PL_BASE + 19, "PL19")
+#define SUNXI_PINCTRL_PIN_PL20 PINCTRL_PIN(PL_BASE + 20, "PL20")
+#define SUNXI_PINCTRL_PIN_PL21 PINCTRL_PIN(PL_BASE + 21, "PL21")
+#define SUNXI_PINCTRL_PIN_PL22 PINCTRL_PIN(PL_BASE + 22, "PL22")
+#define SUNXI_PINCTRL_PIN_PL23 PINCTRL_PIN(PL_BASE + 23, "PL23")
+#define SUNXI_PINCTRL_PIN_PL24 PINCTRL_PIN(PL_BASE + 24, "PL24")
+#define SUNXI_PINCTRL_PIN_PL25 PINCTRL_PIN(PL_BASE + 25, "PL25")
+#define SUNXI_PINCTRL_PIN_PL26 PINCTRL_PIN(PL_BASE + 26, "PL26")
+#define SUNXI_PINCTRL_PIN_PL27 PINCTRL_PIN(PL_BASE + 27, "PL27")
+#define SUNXI_PINCTRL_PIN_PL28 PINCTRL_PIN(PL_BASE + 28, "PL28")
+#define SUNXI_PINCTRL_PIN_PL29 PINCTRL_PIN(PL_BASE + 29, "PL29")
+#define SUNXI_PINCTRL_PIN_PL30 PINCTRL_PIN(PL_BASE + 30, "PL30")
+#define SUNXI_PINCTRL_PIN_PL31 PINCTRL_PIN(PL_BASE + 31, "PL31")
+
#define SUNXI_PIN_NAME_MAX_LEN 5
#define BANK_MEM_SIZE 0x24
--
1.8.3.2
Retrieve and enable the clock gate related to PL pins.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pinctrl/pinctrl-sunxi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 64dffc8..da76ceb 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -898,6 +898,13 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
return -ENOMEM;
pctl->get_membase = sun6i_a31_pinctrl_get_membase;
+ clk = devm_clk_get(&pdev->dev, "pioL_clk");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ ret = clk_prepare_enable(clk);
+ if (ret)
+ return ret;
} else {
pctl->get_membase = sunxi_pinctrl_get_membase;
}
--
1.8.3.2
The A31 SoC define a new memory region dedicated to PL pins.
Add a new get_membase callback to the sunxi_pinctrl struct in order to
retrieve the membase and relative pin number from an absolute pin number,
and make use of this new callback when manipulating the pins.
Currently, only the A31 SoC needs a specific conversion, the other one use
a contiguous memory region for all their pins.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pinctrl/pinctrl-sunxi.c | 186 +++++++++++++++++++++++++++++-----------
drivers/pinctrl/pinctrl-sunxi.h | 5 +-
2 files changed, 139 insertions(+), 52 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index ef16311..64dffc8 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -115,6 +115,35 @@ sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
return NULL;
}
+static void __iomem *
+sun6i_a31_pinctrl_get_membase(struct sunxi_pinctrl *pctl, unsigned pin_num,
+ unsigned *rel_pin_num)
+{
+ void __iomem *membase;
+
+ if (pin_num >= PL_BASE) {
+ pin_num -= PL_BASE;
+ membase = pctl->membase[1];
+ } else {
+ membase = pctl->membase[0];
+ }
+
+ if (rel_pin_num)
+ *rel_pin_num = pin_num;
+
+ return membase;
+}
+
+static void __iomem *
+sunxi_pinctrl_get_membase(struct sunxi_pinctrl *pctl, unsigned pin_num,
+ unsigned *rel_pin_num)
+{
+ if (rel_pin_num)
+ *rel_pin_num = pin_num;
+
+ return pctl->membase[0];
+}
+
static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
@@ -280,8 +309,10 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = &pctl->groups[group];
+ void __iomem *membase;
unsigned long flags;
- u32 val, mask;
+ u32 val, mask, reg;
+ unsigned pin;
u16 strength;
u8 dlevel;
int i;
@@ -289,6 +320,8 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pctl->lock, flags);
for (i = 0; i < num_configs; i++) {
+ membase = pctl->get_membase(pctl, g->pin, &pin);
+
switch (pinconf_to_config_param(configs[i])) {
case PIN_CONFIG_DRIVE_STRENGTH:
strength = pinconf_to_config_argument(configs[i]);
@@ -304,23 +337,26 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
* 3: 40mA
*/
dlevel = strength / 10 - 1;
- val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
- mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
+ reg = sunxi_dlevel_reg(pin);
+ val = readl(membase + reg);
+ mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
writel((val & ~mask)
- | dlevel << sunxi_dlevel_offset(g->pin),
- pctl->membase + sunxi_dlevel_reg(g->pin));
+ | dlevel << sunxi_dlevel_offset(pin),
+ membase + reg);
break;
case PIN_CONFIG_BIAS_PULL_UP:
- val = readl(pctl->membase + sunxi_pull_reg(g->pin));
- mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
- writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
- pctl->membase + sunxi_pull_reg(g->pin));
+ reg = sunxi_pull_reg(pin);
+ val = readl(membase + reg);
+ mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
+ writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
+ membase + reg);
break;
case PIN_CONFIG_BIAS_PULL_DOWN:
- val = readl(pctl->membase + sunxi_pull_reg(g->pin));
- mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
- writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
- pctl->membase + sunxi_pull_reg(g->pin));
+ reg = sunxi_pull_reg(pin);
+ val = readl(membase + reg);
+ mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
+ writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
+ membase + reg);
break;
default:
break;
@@ -372,15 +408,18 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
u8 config)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ void __iomem *membase;
unsigned long flags;
u32 val, mask;
+ membase = pctl->get_membase(pctl, pin, &pin);
+
spin_lock_irqsave(&pctl->lock, flags);
- val = readl(pctl->membase + sunxi_mux_reg(pin));
+ val = readl(membase + sunxi_mux_reg(pin));
mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
writel((val & ~mask) | config << sunxi_mux_offset(pin),
- pctl->membase + sunxi_mux_reg(pin));
+ membase + sunxi_mux_reg(pin));
spin_unlock_irqrestore(&pctl->lock, flags);
}
@@ -462,10 +501,14 @@ static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
+ void __iomem *membase;
+ u32 reg, val;
+ u8 index;
- u32 reg = sunxi_data_reg(offset);
- u8 index = sunxi_data_offset(offset);
- u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
+ membase = pctl->get_membase(pctl, offset, &offset);
+ reg = sunxi_data_reg(offset);
+ index = sunxi_data_offset(offset);
+ val = (readl(membase + reg) >> index) & DATA_PINS_MASK;
return val;
}
@@ -474,21 +517,25 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
unsigned offset, int value)
{
struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
- u32 reg = sunxi_data_reg(offset);
- u8 index = sunxi_data_offset(offset);
+ void __iomem *membase;
unsigned long flags;
- u32 regval;
+ u32 reg, regval;
+ u8 index;
+
+ membase = pctl->get_membase(pctl, offset, &offset);
+ reg = sunxi_data_reg(offset);
+ index = sunxi_data_offset(offset);
spin_lock_irqsave(&pctl->lock, flags);
- regval = readl(pctl->membase + reg);
+ regval = readl(membase + reg);
if (value)
regval |= BIT(index);
else
regval &= ~(BIT(index));
- writel(regval, pctl->membase + reg);
+ writel(regval, membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags);
}
@@ -556,11 +603,15 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
unsigned int type)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_cfg_reg(d->hwirq);
- u8 index = sunxi_irq_cfg_offset(d->hwirq);
+ void __iomem *membase;
unsigned long flags;
- u32 regval;
- u8 mode;
+ u32 reg, regval;
+ u8 index, mode;
+ unsigned pin;
+
+ membase = pctl->get_membase(pctl, d->hwirq, &pin);
+ reg = sunxi_irq_cfg_reg(pin);
+ index = sunxi_irq_cfg_offset(pin);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -584,9 +635,9 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
spin_lock_irqsave(&pctl->lock, flags);
- regval = readl(pctl->membase + reg);
+ regval = readl(membase + reg);
regval &= ~(IRQ_CFG_IRQ_MASK << index);
- writel(regval | (mode << index), pctl->membase + reg);
+ writel(regval | (mode << index), membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags);
@@ -596,21 +647,27 @@ static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
- u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
- u32 status_reg = sunxi_irq_status_reg(d->hwirq);
- u8 status_idx = sunxi_irq_status_offset(d->hwirq);
+ void __iomem *membase;
+ u32 ctrl_reg, status_reg, val;
+ u8 ctrl_idx, status_idx;
unsigned long flags;
- u32 val;
+ unsigned pin;
+
+ membase = pctl->get_membase(pctl, d->hwirq, &pin);
+
+ ctrl_reg = sunxi_irq_ctrl_reg(pin);
+ ctrl_idx = sunxi_irq_ctrl_offset(pin);
+ status_reg = sunxi_irq_status_reg(pin);
+ status_idx = sunxi_irq_status_offset(pin);
spin_lock_irqsave(&pctl->lock, flags);
/* Mask the IRQ */
- val = readl(pctl->membase + ctrl_reg);
- writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
+ val = readl(membase + ctrl_reg);
+ writel(val & ~(1 << ctrl_idx), membase + ctrl_reg);
/* Clear the IRQ */
- writel(1 << status_idx, pctl->membase + status_reg);
+ writel(1 << status_idx, membase + status_reg);
spin_unlock_irqrestore(&pctl->lock, flags);
}
@@ -618,16 +675,22 @@ static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
- u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
- u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
+ void __iomem *membase;
+ u32 reg, val;
+ u8 idx;
unsigned long flags;
- u32 val;
+ unsigned pin;
+
+ membase = pctl->get_membase(pctl, d->hwirq, &pin);
+
+ reg = sunxi_irq_ctrl_reg(pin);
+ idx = sunxi_irq_ctrl_offset(pin);
spin_lock_irqsave(&pctl->lock, flags);
/* Mask the IRQ */
- val = readl(pctl->membase + reg);
- writel(val & ~(1 << idx), pctl->membase + reg);
+ val = readl(membase + reg);
+ writel(val & ~(1 << idx), membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags);
}
@@ -635,11 +698,17 @@ static void sunxi_pinctrl_irq_mask(struct irq_data *d)
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
{
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
+ void __iomem *membase;
struct sunxi_desc_function *func;
- u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
- u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
+ u32 reg, val;
+ u8 idx;
unsigned long flags;
- u32 val;
+ unsigned pin;
+
+ membase = pctl->get_membase(pctl, d->hwirq, &pin);
+
+ reg = sunxi_irq_ctrl_reg(pin);
+ idx = sunxi_irq_ctrl_offset(pin);
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
pctl->irq_array[d->hwirq],
@@ -651,8 +720,8 @@ static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
spin_lock_irqsave(&pctl->lock, flags);
/* Unmask the IRQ */
- val = readl(pctl->membase + reg);
- writel(val | (1 << idx), pctl->membase + reg);
+ val = readl(membase + reg);
+ writel(val | (1 << idx), membase + reg);
spin_unlock_irqrestore(&pctl->lock, flags);
}
@@ -668,10 +737,15 @@ static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
- const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
+ void __iomem *membase;
+ unsigned long reg;
+
+ membase = pctl->get_membase(pctl, desc->irq_data.hwirq, NULL);
+
+ reg = readl(membase + IRQ_STATUS_REG);
/* Clear all interrupts */
- writel(reg, pctl->membase + IRQ_STATUS_REG);
+ writel(reg, membase + IRQ_STATUS_REG);
if (reg) {
int irqoffset;
@@ -814,10 +888,20 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
spin_lock_init(&pctl->lock);
- pctl->membase = of_iomap(node, 0);
- if (!pctl->membase)
+ pctl->membase[0] = of_iomap(node, 0);
+ if (!pctl->membase[0])
return -ENOMEM;
+ if (of_device_is_compatible(node, "allwinner,sun6i-a31-pinctrl")) {
+ pctl->membase[1] = of_iomap(node, 1);
+ if (!pctl->membase[1])
+ return -ENOMEM;
+
+ pctl->get_membase = sun6i_a31_pinctrl_get_membase;
+ } else {
+ pctl->get_membase = sunxi_pinctrl_get_membase;
+ }
+
device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
if (!device)
return -ENODEV;
diff --git a/drivers/pinctrl/pinctrl-sunxi.h b/drivers/pinctrl/pinctrl-sunxi.h
index ef8890d..a008041 100644
--- a/drivers/pinctrl/pinctrl-sunxi.h
+++ b/drivers/pinctrl/pinctrl-sunxi.h
@@ -431,7 +431,7 @@ struct sunxi_pinctrl_group {
};
struct sunxi_pinctrl {
- void __iomem *membase;
+ void __iomem *membase[2];
struct gpio_chip *chip;
struct sunxi_pinctrl_desc *desc;
struct device *dev;
@@ -444,6 +444,9 @@ struct sunxi_pinctrl {
int irq_array[SUNXI_IRQ_NUMBER];
spinlock_t lock;
struct pinctrl_dev *pctl_dev;
+ void __iomem * (*get_membase)(struct sunxi_pinctrl *pctl,
+ unsigned pin_num,
+ unsigned *rel_pin_num);
};
#define SUNXI_PIN(_pin, ...) \
--
1.8.3.2
Retrieve and deassert the reset line related to PL pins.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pinctrl/pinctrl-sunxi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index da76ceb..09eea79 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -26,6 +26,7 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <linux/slab.h>
#include "core.h"
@@ -878,6 +879,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
const struct of_device_id *device;
struct pinctrl_pin_desc *pins;
struct sunxi_pinctrl *pctl;
+ struct reset_control *rstc;
int i, ret, last_pin;
struct clk *clk;
@@ -905,6 +907,14 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
ret = clk_prepare_enable(clk);
if (ret)
return ret;
+
+ rstc = devm_reset_control_get(&pdev->dev, NULL);
+ if (IS_ERR(rstc))
+ return PTR_ERR(rstc);
+
+ ret = reset_control_deassert(rstc);
+ if (ret)
+ return ret;
} else {
pctl->get_membase = sunxi_pinctrl_get_membase;
}
--
1.8.3.2
Define PL0/PL1 pins available on the A31 SoC.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pinctrl/pinctrl-sunxi-pins.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 3d60669..274cefa 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -2818,6 +2818,14 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "p2wi")), /* SCL */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "p2wi")), /* SDA */
};
static const struct sunxi_desc_pin sun7i_a20_pins[] = {
--
1.8.3.2
The A31 SoC control its PL pins using a different memory, and needs both a
new gate clk and a reset line to enable these PL port.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ed9c2c1..90b3a25 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -210,13 +210,17 @@
pio: pinctrl@01c20800 {
compatible = "allwinner,sun6i-a31-pinctrl";
- reg = <0x01c20800 0x400>;
+ reg = <0x01c20800 0x400>,
+ <0x01f02c00 0x400>;
interrupts = <0 11 4>,
<0 15 4>,
<0 16 4>,
<0 17 4>;
- clocks = <&apb1_gates 5>;
- clock-names = "pio_clk";
+ clocks = <&apb1_gates 5>,
+ <&apb0_gates 0>;
+ clock-names = "pio_clk", "pioL_clk";
+ resets = <&apb0_rst 0>;
+
gpio-controller;
interrupt-controller;
#address-cells = <1>;
--
1.8.3.2
Document clocks and clock-names properties for the pinctrl driver.
Signed-off-by: Boris BREZILLON <[email protected]>
---
Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 0e7e9a1..b3e5c30 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -15,6 +15,10 @@ Required properties:
"allwinner,sun7i-a20-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
+- clocks: Should contain a list of gate clk needed by the pin controller
+- clock-names: Should at least contain "pio_clk" which is used by the
+ base pin controller. In case of sun6i-a31 SoC, this property should
+ also contain the "pioL_clk" string.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
--
1.8.3.2
Add APB0 reset line support for the A31 SoC.
This reset lines are controlled by the PRCM (Power/Reset/Clock Management) block
and thus will act on a different iomem range.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 61e8b34..ed9c2c1 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -237,6 +237,12 @@
reg = <0x01c202c0 0xc>;
};
+ apb0_rst: reset@01f014b0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01f014b0 0x4>;
+ };
+
apb1_rst: reset@01c202d0 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
--
1.8.3.2
List all sunxi pinctrl compatible strings in order to be able to grep for
those values.
Signed-off-by: Boris BREZILLON <[email protected]>
---
.../devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index dff0e5f..0e7e9a1 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -6,8 +6,13 @@ the first two functions being GPIO in and out. The configuration on
the pins includes drive strength and pull-up.
Required properties:
-- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:
- sun5i-a13.
+- compatible: Should be one of the followings (depending on you SoC):
+ "allwinner,sun4i-a10-pinctrl"
+ "allwinner,sun5i-a10s-pinctrl"
+ "allwinner,sun5i-a13-pinctrl"
+ "allwinner,sun6i-a31-pinctrl"
+ "allwinner,sun6i-a31-pinctrl"
+ "allwinner,sun7i-a20-pinctrl"
- reg: Should contain the register physical address and length for the
pin controller.
--
1.8.3.2
Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
Management) block.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 3858424..61e8b34 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -141,6 +141,16 @@
"ahb1_drc0", "ahb1_drc1";
};
+ apb0_gates: apb0_gates@01f01428 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun6i-a31-apb0-gates-clk";
+ reg = <0x01f01428 0x4>;
+ clock-output-names = "apb0_pio", "apb0_ir",
+ "apb0_timer01", "apb0_p2wi",
+ "apb0_uart", "apb0_1wire",
+ "apb0_i2c";
+ };
+
apb1: apb1@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-apb0-clk";
--
1.8.3.2
Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the
sunxi clock documentation.
Signed-off-by: Boris BREZILLON <[email protected]>
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index c2cb762..bc30387 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -25,6 +25,7 @@ Required properties:
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
+ "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A10s
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
--
1.8.3.2
Hi,
On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
<[email protected]> wrote:
> Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the
> sunxi clock documentation.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index c2cb762..bc30387 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -25,6 +25,7 @@ Required properties:
> "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
> "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
> "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
> + "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A10s
^^^^
Copy paste error here.
ChenYu
> "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
> "allwinner,sun4i-apb1-clk" - for the APB1 clock
> "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
Add DT bindings documentation for sunxi's reset controllers.
Signed-off-by: Boris BREZILLON <[email protected]>
---
.../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
new file mode 100644
index 0000000..a582804
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
@@ -0,0 +1,21 @@
+Allwinner sunxi Peripheral Reset Controller
+===========================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be one of the following depending on your SoC:
+ "allwinner,sun6i-a31-ahb1-reset"
+ "allwinner,sun6i-a31-clock-reset"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+example:
+
+ahb1_rst: reset@01c202c0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+};
--
1.8.3.2
Add APB0 gates support for the A31 SoC.
This gates are controlled by the PRCM (Power/Reset/Clock Management) block
and thus will act on a different iomem range.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/clk/sunxi/clk-sunxi.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..f9b11c3 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -718,6 +718,10 @@ static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
.mask = {0x61},
};
+static const struct gates_data sun6i_a31_apb0_gates_data __initconst = {
+ .mask = { 0x7f },
+};
+
static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
.mask = { 0x4ff },
};
@@ -1013,6 +1017,7 @@ static const struct of_device_id clk_gates_match[] __initconst = {
{.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
{.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
+ {.compatible = "allwinner,sun6i-a31-apb0-gates-clk", .data = &sun6i_a31_apb0_gates_data,},
{.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
{.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
{.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
--
1.8.3.2
Specify base pio clk name when retrieving it using the CCF.
This way we will avoid conflicts when introducing a second clk for the A31
SoC.
Signed-off-by: Boris BREZILLON <[email protected]>
---
drivers/pinctrl/pinctrl-sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index f9fabe9..ef16311 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -878,7 +878,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
goto gpiochip_error;
}
- clk = devm_clk_get(&pdev->dev, NULL);
+ clk = devm_clk_get(&pdev->dev, "pio_clk");
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
goto gpiochip_error;
--
1.8.3.2
Add clock-names property to pinctrl node definitions.
Signed-off-by: Boris BREZILLON <[email protected]>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
arch/arm/boot/dts/sun5i-a10s.dtsi | 1 +
arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 1 +
arch/arm/boot/dts/sun7i-a20.dtsi | 1 +
5 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 7753be0..4e33447 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -342,6 +342,7 @@
reg = <0x01c20800 0x400>;
interrupts = <28>;
clocks = <&apb0_gates 5>;
+ clock-names = "pio_clk";
gpio-controller;
interrupt-controller;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ee17b1c..b823bc1 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -305,6 +305,7 @@
reg = <0x01c20800 0x400>;
interrupts = <28>;
clocks = <&apb0_gates 5>;
+ clock-names = "pio_clk";
gpio-controller;
interrupt-controller;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 3490ef9..914e3c2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -286,6 +286,7 @@
reg = <0x01c20800 0x400>;
interrupts = <28>;
clocks = <&apb0_gates 5>;
+ clock-names = "pio_clk";
gpio-controller;
interrupt-controller;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 38d43fe..3858424 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -206,6 +206,7 @@
<0 16 4>,
<0 17 4>;
clocks = <&apb1_gates 5>;
+ clock-names = "pio_clk";
gpio-controller;
interrupt-controller;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index cadcf2f..38ab782 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -368,6 +368,7 @@
reg = <0x01c20800 0x400>;
interrupts = <0 28 4>;
clocks = <&apb0_gates 5>;
+ clock-names = "pio_clk";
gpio-controller;
interrupt-controller;
#address-cells = <1>;
--
1.8.3.2
Hi Boris,
El 09/04/14 10:51, Boris BREZILLON escribi?:
> Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
> Management) block.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index 3858424..61e8b34 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -141,6 +141,16 @@
> "ahb1_drc0", "ahb1_drc1";
> };
>
> + apb0_gates: apb0_gates@01f01428 {
Looks like this node is out of place, judging by the address. Try to
keep them in order.
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
> + reg = <0x01f01428 0x4>;
> + clock-output-names = "apb0_pio", "apb0_ir",
> + "apb0_timer01", "apb0_p2wi",
> + "apb0_uart", "apb0_1wire",
> + "apb0_i2c";
> + };
> +
> apb1: apb1@01c20054 {
> #clock-cells = <0>;
> compatible = "allwinner,sun4i-apb0-clk";
>
Cheers,
Emilio
On 09/04/2014 16:06, Emilio L?pez wrote:
> Hi Boris,
>
> El 09/04/14 10:51, Boris BREZILLON escribi?:
>> Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
>> Management) block.
>>
>> Signed-off-by: Boris BREZILLON <[email protected]>
>> ---
>> arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
>> b/arch/arm/boot/dts/sun6i-a31.dtsi
>> index 3858424..61e8b34 100644
>> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
>> @@ -141,6 +141,16 @@
>> "ahb1_drc0", "ahb1_drc1";
>> };
>>
>> + apb0_gates: apb0_gates@01f01428 {
>
> Looks like this node is out of place, judging by the address. Try to
> keep them in order.
Sure, I'll fix it for the next version.
>
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
>> + reg = <0x01f01428 0x4>;
>> + clock-output-names = "apb0_pio", "apb0_ir",
>> + "apb0_timer01", "apb0_p2wi",
>> + "apb0_uart", "apb0_1wire",
>> + "apb0_i2c";
>> + };
>> +
>> apb1: apb1@01c20054 {
>> #clock-cells = <0>;
>> compatible = "allwinner,sun4i-apb0-clk";
>>
>
> Cheers,
>
> Emilio
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hi,
On Wed, Apr 09, 2014 at 03:51:04PM +0200, Boris BREZILLON wrote:
> List all sunxi pinctrl compatible strings in order to be able to grep for
> those values.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> .../devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index dff0e5f..0e7e9a1 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -6,8 +6,13 @@ the first two functions being GPIO in and out. The configuration on
> the pins includes drive strength and pull-up.
>
> Required properties:
> -- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:
> - sun5i-a13.
> +- compatible: Should be one of the followings (depending on you SoC):
> + "allwinner,sun4i-a10-pinctrl"
> + "allwinner,sun5i-a10s-pinctrl"
> + "allwinner,sun5i-a13-pinctrl"
> + "allwinner,sun6i-a31-pinctrl"
> + "allwinner,sun6i-a31-pinctrl"
Copy and paste error ? :)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On 09/04/2014 15:59, Chen-Yu Tsai wrote:
> Hi,
>
> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
> <[email protected]> wrote:
>> Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the
>> sunxi clock documentation.
>>
>> Signed-off-by: Boris BREZILLON <[email protected]>
>> ---
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
>> index c2cb762..bc30387 100644
>> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
>> @@ -25,6 +25,7 @@ Required properties:
>> "allwinner,sun4i-apb0-gates-clk" - for the APB0 gates on A10
>> "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
>> "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
>> + "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A10s
> ^^^^
> Copy paste error here.
Oops, it'll be fixed in the next version.
>
>
> ChenYu
>
>> "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
>> "allwinner,sun4i-apb1-clk" - for the APB1 clock
>> "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 03:51:08PM +0200, Boris BREZILLON wrote:
> Add APB0 gates support for the A31 SoC.
> This gates are controlled by the PRCM (Power/Reset/Clock Management) block
> and thus will act on a different iomem range.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 03:51:05PM +0200, Boris BREZILLON wrote:
> Document clocks and clock-names properties for the pinctrl driver.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 0e7e9a1..b3e5c30 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -15,6 +15,10 @@ Required properties:
> "allwinner,sun7i-a20-pinctrl"
> - reg: Should contain the register physical address and length for the
> pin controller.
> +- clocks: Should contain a list of gate clk needed by the pin controller
> +- clock-names: Should at least contain "pio_clk" which is used by the
> + base pin controller. In case of sun6i-a31 SoC, this property should
> + also contain the "pioL_clk" string.
You should probably mention that these two should be in the same
order.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
Hi Boris,
On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
<[email protected]> wrote:
> Hello,
>
> This series rework the sunxi pinctrl driver to support the PLx pins
> available on the A31 SoC.
Thanks for working on this. I mentioned to Maxime on IRC yesterday that
we have complete pinctrl drivers for both A31 and A23, based on our current
pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
> It also add missing A31 reset controller DT bindings documentation.
>
> I need those PL pins (actually I only need PL0 and PL1) to support
> the P2WI bus, which in turn is used to communicate with the AXP221
> PMIC.
If you could, please add all the PL and PM pins.
As I said, you can find complete definitions in the A23 SDK.
> Let me know if these changes are too intrusive.
I wonder if we should do a separate driver for the new PIO controller.
Clearly it's a separate IP block, with it's own clock and reset controls.
Allwinner sources list this block as "R_PIO". I suggest using this name.
Clearly "pioL" does not cover all the functionality.
I have started to document the PRCM block: http://linux-sunxi.org/PRCM
Last, please send the patches to the linux-sunxi mailing list as well.
At the very least, Hans will see them and add them to sunxi-devel branch.
Cheers,
ChenYu
> Best Regards,
>
> Boris
>
> Boris BREZILLON (15):
> ARM: sunxi: dt: list all pinctrl compatible strings
> ARM: sunxi: dt: document pinctrl clock related properties
> ARM: sunxi: dt: add pinctrl clock-names properties
> pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk
> clk: sunxi: add A31 APB0 clk gate defintions
> clk: sunxi: add A31 APB0 gates compatible string to the documentation
> ARM: sunxi: dt: define A31's APB0 clk gates node
> reset: sunxi: document sunxi's reset controllers bindings
> clk: sunxi: add A31 APB0 reset line defintions
> pinctrl: sunxi: add PL pin definitions
> pinctrl: sunxi: add support for A31 PL pins
> pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC
> pinctrl: sunxi: retrieve and enable PL reset line for A31 SoC
> pinctrl: sunxi: define A31 PL0/PL1 pins
> ARM: sunxi: dt: add support for A31's PL pins
>
> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 13 +-
> .../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++
> arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
> arch/arm/boot/dts/sun5i-a10s.dtsi | 1 +
> arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
> arch/arm/boot/dts/sun6i-a31.dtsi | 25 ++-
> arch/arm/boot/dts/sun7i-a20.dtsi | 1 +
> drivers/clk/sunxi/clk-sunxi.c | 5 +
> drivers/pinctrl/pinctrl-sunxi-pins.h | 8 +
> drivers/pinctrl/pinctrl-sunxi.c | 205 +++++++++++++++------
> drivers/pinctrl/pinctrl-sunxi.h | 39 +++-
> 12 files changed, 264 insertions(+), 57 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
>
> --
> 1.8.3.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Wed, Apr 09, 2014 at 03:51:09PM +0200, Boris BREZILLON wrote:
> Add the new "allwinner,sun6i-a31-apb0-gates-clk" compatible string to the
> sunxi clock documentation.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
I'd probably merge this with the previous patch.
There's not really any new bindings introduced here, so I guess you
don't really have to make it two commits.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 03:51:10PM +0200, Boris BREZILLON wrote:
> Define the APB0 clk gates controlled by the PRCM (Power/Reset/Clock
> Management) block.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index 3858424..61e8b34 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -141,6 +141,16 @@
> "ahb1_drc0", "ahb1_drc1";
> };
>
> + apb0_gates: apb0_gates@01f01428 {
The node name should reflect the class of the device, so it should be
clk@<address>.
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-apb0-gates-clk";
> + reg = <0x01f01428 0x4>;
> + clock-output-names = "apb0_pio", "apb0_ir",
> + "apb0_timer01", "apb0_p2wi",
> + "apb0_uart", "apb0_1wire",
> + "apb0_i2c";
> + };
> +
Hmmm, I'm not really fond of this.
There's already a PRCM node in the DT, which is used for the SMP
bringup.
I really don't want any duplicate memory regions in the DT, so you'll
have to fix the SMP code.
That being said, I can understand that you did this to be consistent
with the scheme we have for the clock controller where we chose to
make every clock a single driver.
That worked well for the CCU precisely because we only had clocks. It
doesn't for the PRCM because it's not been very well documented, and
it does clocks, resets, that fits pretty well in the existing
frameworks we have, but the SMP related functions are actually not
fitting that well.
It's mostly a power clamp and a power gating bits, that could maybe
fit in the regulator framework.
I don't really have a solution for this. Maybe someone else will.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 10:53:13PM +0800, Chen-Yu Tsai wrote:
> Hi Boris,
>
> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
> <[email protected]> wrote:
> > Hello,
> >
> > This series rework the sunxi pinctrl driver to support the PLx pins
> > available on the A31 SoC.
>
> Thanks for working on this. I mentioned to Maxime on IRC yesterday that
> we have complete pinctrl drivers for both A31 and A23, based on our current
> pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
>
> > It also add missing A31 reset controller DT bindings documentation.
> >
> > I need those PL pins (actually I only need PL0 and PL1) to support
> > the P2WI bus, which in turn is used to communicate with the AXP221
> > PMIC.
>
> If you could, please add all the PL and PM pins.
> As I said, you can find complete definitions in the A23 SDK.
We have no idea what these PM pins are for the A31. And this code only
is of interest for the A31 for the moment. Let's not take into account
the A23 for now as far as the pin definitions are concerned.
> > Let me know if these changes are too intrusive.
>
> I wonder if we should do a separate driver for the new PIO controller.
> Clearly it's a separate IP block, with it's own clock and reset controls.
It's been merged together in the A23, hence why we did it like that.
> Allwinner sources list this block as "R_PIO". I suggest using this name.
> Clearly "pioL" does not cover all the functionality.
I'd agree with that.
> I have started to document the PRCM block: http://linux-sunxi.org/PRCM
It's quite different on the A31 and on the A23 actually :(
You don't have any of the audio thing for example, but you have the
CPUs power clamp controls, that have been moved to the
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 03:51:15PM +0200, Boris BREZILLON wrote:
> Retrieve and enable the clock gate related to PL pins.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> drivers/pinctrl/pinctrl-sunxi.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
> index 64dffc8..da76ceb 100644
> --- a/drivers/pinctrl/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/pinctrl-sunxi.c
> @@ -898,6 +898,13 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> pctl->get_membase = sun6i_a31_pinctrl_get_membase;
> + clk = devm_clk_get(&pdev->dev, "pioL_clk");
> + if (IS_ERR(clk))
> + return PTR_ERR(clk);
> +
> + ret = clk_prepare_enable(clk);
> + if (ret)
> + return ret;
Since the pioL_clk isn't declared in the DT yet, the pinctrl driver
won't ever probe here.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 03:51:16PM +0200, Boris BREZILLON wrote:
> Retrieve and deassert the reset line related to PL pins.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> drivers/pinctrl/pinctrl-sunxi.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
> index da76ceb..09eea79 100644
> --- a/drivers/pinctrl/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/pinctrl-sunxi.c
> @@ -26,6 +26,7 @@
> #include <linux/pinctrl/pinconf-generic.h>
> #include <linux/pinctrl/pinmux.h>
> #include <linux/platform_device.h>
> +#include <linux/reset.h>
> #include <linux/slab.h>
>
> #include "core.h"
> @@ -878,6 +879,7 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
> const struct of_device_id *device;
> struct pinctrl_pin_desc *pins;
> struct sunxi_pinctrl *pctl;
> + struct reset_control *rstc;
> int i, ret, last_pin;
> struct clk *clk;
>
> @@ -905,6 +907,14 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
> ret = clk_prepare_enable(clk);
> if (ret)
> return ret;
> +
> + rstc = devm_reset_control_get(&pdev->dev, NULL);
> + if (IS_ERR(rstc))
> + return PTR_ERR(rstc);
> +
> + ret = reset_control_deassert(rstc);
> + if (ret)
> + return ret;
Same thing than in patch 12 :)
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 03:51:17PM +0200, Boris BREZILLON wrote:
> Define PL0/PL1 pins available on the A31 SoC.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
> ---
> drivers/pinctrl/pinctrl-sunxi-pins.h | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
> index 3d60669..274cefa 100644
> --- a/drivers/pinctrl/pinctrl-sunxi-pins.h
> +++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
> @@ -2818,6 +2818,14 @@ static const struct sunxi_desc_pin sun6i_a31_pins[] = {
> SUNXI_FUNCTION(0x0, "gpio_in"),
> SUNXI_FUNCTION(0x1, "gpio_out"),
> SUNXI_FUNCTION(0x2, "nand1")), /* CE3 */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN_PL0,
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x3, "p2wi")), /* SCL */
> + SUNXI_PIN(SUNXI_PINCTRL_PIN_PL1,
> + SUNXI_FUNCTION(0x0, "gpio_in"),
> + SUNXI_FUNCTION(0x1, "gpio_out"),
> + SUNXI_FUNCTION(0x3, "p2wi")), /* SDA */
If possible, I'd prefer to have this list as exhaustive as
possible.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Wed, Apr 09, 2014 at 05:17:47PM +0200, Maxime Ripard wrote:
> > I have started to document the PRCM block: http://linux-sunxi.org/PRCM
>
> It's quite different on the A31 and on the A23 actually :(
>
> You don't have any of the audio thing for example, but you have the
> CPUs power clamp controls, that have been moved to the
-that have been moved to the
+that have been removed in the A23
Sorry :)
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On 09/04/2014 16:53, Chen-Yu Tsai wrote:
> Hi Boris,
>
> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
> <[email protected]> wrote:
>> Hello,
>>
>> This series rework the sunxi pinctrl driver to support the PLx pins
>> available on the A31 SoC.
> Thanks for working on this. I mentioned to Maxime on IRC yesterday that
> we have complete pinctrl drivers for both A31 and A23, based on our current
> pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
Thanks for pointing this out, I'll take a look.
>
>> It also add missing A31 reset controller DT bindings documentation.
>>
>> I need those PL pins (actually I only need PL0 and PL1) to support
>> the P2WI bus, which in turn is used to communicate with the AXP221
>> PMIC.
> If you could, please add all the PL and PM pins.
Sure, I'll add pin macros for L and M ports.
> As I said, you can find complete definitions in the A23 SDK.
>
>> Let me know if these changes are too intrusive.
> I wonder if we should do a separate driver for the new PIO controller.
> Clearly it's a separate IP block, with it's own clock and reset controls.
This is what I had in mind in the first place, but then I encountered
several issues when doing so:
1) the gpio chip is not dynamically allocated but is declared as a
static variable instead
2) we have to tweak the pinctrl base field, otherwise the pin numbers
overlap
3) other things I haven't noticed yet :-)
I'll try to rework the driver to be able to declare 2 separated pin
controllers.
> Allwinner sources list this block as "R_PIO". I suggest using this name.
> Clearly "pioL" does not cover all the functionality.
Fair enough. I'll modify it.
>
> I have started to document the PRCM block: http://linux-sunxi.org/PRCM
>
> Last, please send the patches to the linux-sunxi mailing list as well.
> At the very least, Hans will see them and add them to sunxi-devel branch.
Sure, this is an oversight, I'm using get_maintainer and just forgot to
add Hans and the linux-sunxi ML. But I'll take care to add you, hans and
the sunxi ML in Cc next time.
Thanks for your review.
Best Regards,
Boris
>
>
> Cheers,
> ChenYu
>
>> Best Regards,
>>
>> Boris
>>
>> Boris BREZILLON (15):
>> ARM: sunxi: dt: list all pinctrl compatible strings
>> ARM: sunxi: dt: document pinctrl clock related properties
>> ARM: sunxi: dt: add pinctrl clock-names properties
>> pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk
>> clk: sunxi: add A31 APB0 clk gate defintions
>> clk: sunxi: add A31 APB0 gates compatible string to the documentation
>> ARM: sunxi: dt: define A31's APB0 clk gates node
>> reset: sunxi: document sunxi's reset controllers bindings
>> clk: sunxi: add A31 APB0 reset line defintions
>> pinctrl: sunxi: add PL pin definitions
>> pinctrl: sunxi: add support for A31 PL pins
>> pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC
>> pinctrl: sunxi: retrieve and enable PL reset line for A31 SoC
>> pinctrl: sunxi: define A31 PL0/PL1 pins
>> ARM: sunxi: dt: add support for A31's PL pins
>>
>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 13 +-
>> .../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++
>> arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
>> arch/arm/boot/dts/sun5i-a10s.dtsi | 1 +
>> arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
>> arch/arm/boot/dts/sun6i-a31.dtsi | 25 ++-
>> arch/arm/boot/dts/sun7i-a20.dtsi | 1 +
>> drivers/clk/sunxi/clk-sunxi.c | 5 +
>> drivers/pinctrl/pinctrl-sunxi-pins.h | 8 +
>> drivers/pinctrl/pinctrl-sunxi.c | 205 +++++++++++++++------
>> drivers/pinctrl/pinctrl-sunxi.h | 39 +++-
>> 12 files changed, 264 insertions(+), 57 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
>>
>> --
>> 1.8.3.2
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> [email protected]
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hi,
On Wed, Apr 9, 2014 at 11:17 PM, Maxime Ripard
<[email protected]> wrote:
> On Wed, Apr 09, 2014 at 10:53:13PM +0800, Chen-Yu Tsai wrote:
>> Hi Boris,
>>
>> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
>> <[email protected]> wrote:
>> > Hello,
>> >
>> > This series rework the sunxi pinctrl driver to support the PLx pins
>> > available on the A31 SoC.
>>
>> Thanks for working on this. I mentioned to Maxime on IRC yesterday that
>> we have complete pinctrl drivers for both A31 and A23, based on our current
>> pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
>>
>> > It also add missing A31 reset controller DT bindings documentation.
>> >
>> > I need those PL pins (actually I only need PL0 and PL1) to support
>> > the P2WI bus, which in turn is used to communicate with the AXP221
>> > PMIC.
>>
>> If you could, please add all the PL and PM pins.
>> As I said, you can find complete definitions in the A23 SDK.
>
> We have no idea what these PM pins are for the A31. And this code only
> is of interest for the A31 for the moment. Let's not take into account
> the A23 for now as far as the pin definitions are concerned.
Yes I was referring to the A31. In the A23 SDK, sun8iw1 refers to A31.
As for the PM pins, the A31 EVB fex file uses one PM pin for LCD backlight
control. And don't take my word for it. A31 standard design schematics from
Omilex clearly show PL/PM pins with the possible functions on the top left of
page 7. See:
https://github.com/OLIMEX/OLINUXINO/blob/master/HARDWARE/A31-PDFs/A31_PAD_STD_V1_90_130225.pdf
>> > Let me know if these changes are too intrusive.
>>
>> I wonder if we should do a separate driver for the new PIO controller.
>> Clearly it's a separate IP block, with it's own clock and reset controls.
>
> It's been merged together in the A23, hence why we did it like that.
I'm not sure I understand. The clock gate and reset control are still separate,
are they not?
>> Allwinner sources list this block as "R_PIO". I suggest using this name.
>> Clearly "pioL" does not cover all the functionality.
>
> I'd agree with that.
>
>
>> I have started to document the PRCM block: http://linux-sunxi.org/PRCM
>
> It's quite different on the A31 and on the A23 actually :(
>
> You don't have any of the audio thing for example, but you have the
> CPUs power clamp controls, that have been removed in the A23.
Thank you for bringing this up. I went through the code and updated
these bits on the wiki. The CPU power clamps are interleaved throughout
the PRCM registers :(
Cheers,
ChenYu
On Thu, Apr 10, 2014 at 12:14 AM, Boris BREZILLON
<[email protected]> wrote:
>
> On 09/04/2014 16:53, Chen-Yu Tsai wrote:
>> Hi Boris,
>>
>> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
>> <[email protected]> wrote:
>>> Hello,
>>>
>>> This series rework the sunxi pinctrl driver to support the PLx pins
>>> available on the A31 SoC.
>> Thanks for working on this. I mentioned to Maxime on IRC yesterday that
>> we have complete pinctrl drivers for both A31 and A23, based on our current
>> pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
>
> Thanks for pointing this out, I'll take a look.
>
>>
>>> It also add missing A31 reset controller DT bindings documentation.
>>>
>>> I need those PL pins (actually I only need PL0 and PL1) to support
>>> the P2WI bus, which in turn is used to communicate with the AXP221
>>> PMIC.
>> If you could, please add all the PL and PM pins.
>
> Sure, I'll add pin macros for L and M ports.
>
>> As I said, you can find complete definitions in the A23 SDK.
>>
>>> Let me know if these changes are too intrusive.
>> I wonder if we should do a separate driver for the new PIO controller.
>> Clearly it's a separate IP block, with it's own clock and reset controls.
>
> This is what I had in mind in the first place, but then I encountered
> several issues when doing so:
>
> 1) the gpio chip is not dynamically allocated but is declared as a
> static variable instead
Hmm. Not sure if this is worth the change.
> 2) we have to tweak the pinctrl base field, otherwise the pin numbers
> overlap
Documentation says pin numbers are global, however the pinctrl core code
only looks up a pin by number in a pinctrl device only.
Also I see mfd pinctrl drivers (ab8500, as3722) have pin numbers starting
from 0. So definitely some confusion there.
> 3) other things I haven't noticed yet :-)
Reworking EINT to use one interrupt per bank will yield some more surprises.
There's also new gpiolib irqchip helpers, but that will require reworking
each pin bank into separate gpio chips. May be more work than just adding
different irq domains for different banks.
See: https://lkml.org/lkml/2014/3/25/175
> I'll try to rework the driver to be able to declare 2 separated pin
> controllers.
Thanks again.
ChenYu
>> Allwinner sources list this block as "R_PIO". I suggest using this name.
>> Clearly "pioL" does not cover all the functionality.
>
> Fair enough. I'll modify it.
>
>>
>> I have started to document the PRCM block: http://linux-sunxi.org/PRCM
>>
>> Last, please send the patches to the linux-sunxi mailing list as well.
>> At the very least, Hans will see them and add them to sunxi-devel branch.
>
> Sure, this is an oversight, I'm using get_maintainer and just forgot to
> add Hans and the linux-sunxi ML. But I'll take care to add you, hans and
> the sunxi ML in Cc next time.
>
> Thanks for your review.
>
> Best Regards,
>
> Boris
>
>>
>>
>> Cheers,
>> ChenYu
>>
>>> Best Regards,
>>>
>>> Boris
>>>
>>> Boris BREZILLON (15):
>>> ARM: sunxi: dt: list all pinctrl compatible strings
>>> ARM: sunxi: dt: document pinctrl clock related properties
>>> ARM: sunxi: dt: add pinctrl clock-names properties
>>> pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk
>>> clk: sunxi: add A31 APB0 clk gate defintions
>>> clk: sunxi: add A31 APB0 gates compatible string to the documentation
>>> ARM: sunxi: dt: define A31's APB0 clk gates node
>>> reset: sunxi: document sunxi's reset controllers bindings
>>> clk: sunxi: add A31 APB0 reset line defintions
>>> pinctrl: sunxi: add PL pin definitions
>>> pinctrl: sunxi: add support for A31 PL pins
>>> pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC
>>> pinctrl: sunxi: retrieve and enable PL reset line for A31 SoC
>>> pinctrl: sunxi: define A31 PL0/PL1 pins
>>> ARM: sunxi: dt: add support for A31's PL pins
>>>
>>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 13 +-
>>> .../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++
>>> arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
>>> arch/arm/boot/dts/sun5i-a10s.dtsi | 1 +
>>> arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
>>> arch/arm/boot/dts/sun6i-a31.dtsi | 25 ++-
>>> arch/arm/boot/dts/sun7i-a20.dtsi | 1 +
>>> drivers/clk/sunxi/clk-sunxi.c | 5 +
>>> drivers/pinctrl/pinctrl-sunxi-pins.h | 8 +
>>> drivers/pinctrl/pinctrl-sunxi.c | 205 +++++++++++++++------
>>> drivers/pinctrl/pinctrl-sunxi.h | 39 +++-
>>> 12 files changed, 264 insertions(+), 57 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
>>>
>>> --
>>> 1.8.3.2
>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> [email protected]
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> Boris Brezillon, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
On 09/04/2014 19:14, Chen-Yu Tsai wrote:
> On Thu, Apr 10, 2014 at 12:14 AM, Boris BREZILLON
> <[email protected]> wrote:
>> On 09/04/2014 16:53, Chen-Yu Tsai wrote:
>>> Hi Boris,
>>>
>>> On Wed, Apr 9, 2014 at 9:51 PM, Boris BREZILLON
>>> <[email protected]> wrote:
>>>> Hello,
>>>>
>>>> This series rework the sunxi pinctrl driver to support the PLx pins
>>>> available on the A31 SoC.
>>> Thanks for working on this. I mentioned to Maxime on IRC yesterday that
>>> we have complete pinctrl drivers for both A31 and A23, based on our current
>>> pinctrl-sunxi driver, in the A23 SDK. These have the complete pin mapping.
>> Thanks for pointing this out, I'll take a look.
>>
>>>> It also add missing A31 reset controller DT bindings documentation.
>>>>
>>>> I need those PL pins (actually I only need PL0 and PL1) to support
>>>> the P2WI bus, which in turn is used to communicate with the AXP221
>>>> PMIC.
>>> If you could, please add all the PL and PM pins.
>> Sure, I'll add pin macros for L and M ports.
>>
>>> As I said, you can find complete definitions in the A23 SDK.
>>>
>>>> Let me know if these changes are too intrusive.
>>> I wonder if we should do a separate driver for the new PIO controller.
>>> Clearly it's a separate IP block, with it's own clock and reset controls.
>> This is what I had in mind in the first place, but then I encountered
>> several issues when doing so:
>>
>> 1) the gpio chip is not dynamically allocated but is declared as a
>> static variable instead
> Hmm. Not sure if this is worth the change.
We have to dynamically allocate the gpio chip struct, otherwise you
would add several times the same struct in the gpio_chips list (when you
call gpiochip_add), which will mess up the list.
Actually, I just realized a gpio chip struct was allocated (line 854)
but then the pointer to this chip was overridden with the address to the
static definitions (line 861):
http://lxr.free-electrons.com/source/drivers/pinctrl/pinctrl-sunxi.c#L854
>
>> 2) we have to tweak the pinctrl base field, otherwise the pin numbers
>> overlap
> Documentation says pin numbers are global, however the pinctrl core code
> only looks up a pin by number in a pinctrl device only.
>
> Also I see mfd pinctrl drivers (ab8500, as3722) have pin numbers starting
> from 0. So definitely some confusion there.
I was talking about the base field of the gpio_chip struct.
This field is used to give a unique gpio id from the GPIO point of view:
unique_gpio_id = gpio_id_within_the_gpio_chip + chip->base.
You can get an automatically assigned gpio base if you set it to -1
before calling gpiochip_add, but AFAIK (correct me if I'm wrong) this is
used for hotplugable GPIO chips.
For ARCH gpios you
>
>> 3) other things I haven't noticed yet :-)
> Reworking EINT to use one interrupt per bank will yield some more surprises.
>
> There's also new gpiolib irqchip helpers, but that will require reworking
> each pin bank into separate gpio chips. May be more work than just adding
> different irq domains for different banks.
>
> See: https://lkml.org/lkml/2014/3/25/175
Okay, I'll take a look.
>
>> I'll try to rework the driver to be able to declare 2 separated pin
>> controllers.
> Thanks again.
>
> ChenYu
>
>>> Allwinner sources list this block as "R_PIO". I suggest using this name.
>>> Clearly "pioL" does not cover all the functionality.
>> Fair enough. I'll modify it.
>>
>>> I have started to document the PRCM block: http://linux-sunxi.org/PRCM
>>>
>>> Last, please send the patches to the linux-sunxi mailing list as well.
>>> At the very least, Hans will see them and add them to sunxi-devel branch.
>> Sure, this is an oversight, I'm using get_maintainer and just forgot to
>> add Hans and the linux-sunxi ML. But I'll take care to add you, hans and
>> the sunxi ML in Cc next time.
>>
>> Thanks for your review.
>>
>> Best Regards,
>>
>> Boris
>>
>>>
>>> Cheers,
>>> ChenYu
>>>
>>>> Best Regards,
>>>>
>>>> Boris
>>>>
>>>> Boris BREZILLON (15):
>>>> ARM: sunxi: dt: list all pinctrl compatible strings
>>>> ARM: sunxi: dt: document pinctrl clock related properties
>>>> ARM: sunxi: dt: add pinctrl clock-names properties
>>>> pinctrl: sunxi: specify clk name when retrieving pinctrl pio clk
>>>> clk: sunxi: add A31 APB0 clk gate defintions
>>>> clk: sunxi: add A31 APB0 gates compatible string to the documentation
>>>> ARM: sunxi: dt: define A31's APB0 clk gates node
>>>> reset: sunxi: document sunxi's reset controllers bindings
>>>> clk: sunxi: add A31 APB0 reset line defintions
>>>> pinctrl: sunxi: add PL pin definitions
>>>> pinctrl: sunxi: add support for A31 PL pins
>>>> pinctrl: sunxi: retrieve and enable PL clk gate for A31 SoC
>>>> pinctrl: sunxi: retrieve and enable PL reset line for A31 SoC
>>>> pinctrl: sunxi: define A31 PL0/PL1 pins
>>>> ARM: sunxi: dt: add support for A31's PL pins
>>>>
>>>> Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>>>> .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 13 +-
>>>> .../bindings/reset/allwinner,sunxi-clock-reset.txt | 21 +++
>>>> arch/arm/boot/dts/sun4i-a10.dtsi | 1 +
>>>> arch/arm/boot/dts/sun5i-a10s.dtsi | 1 +
>>>> arch/arm/boot/dts/sun5i-a13.dtsi | 1 +
>>>> arch/arm/boot/dts/sun6i-a31.dtsi | 25 ++-
>>>> arch/arm/boot/dts/sun7i-a20.dtsi | 1 +
>>>> drivers/clk/sunxi/clk-sunxi.c | 5 +
>>>> drivers/pinctrl/pinctrl-sunxi-pins.h | 8 +
>>>> drivers/pinctrl/pinctrl-sunxi.c | 205 +++++++++++++++------
>>>> drivers/pinctrl/pinctrl-sunxi.h | 39 +++-
>>>> 12 files changed, 264 insertions(+), 57 deletions(-)
>>>> create mode 100644 Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt
>>>>
>>>> --
>>>> 1.8.3.2
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> [email protected]
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> --
>> Boris Brezillon, Free Electrons
>> Embedded Linux and Kernel engineering
>> http://free-electrons.com
>>
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
On Thu, Apr 10, 2014 at 12:27:32AM +0800, Chen-Yu Tsai wrote:
> >> > Let me know if these changes are too intrusive.
> >>
> >> I wonder if we should do a separate driver for the new PIO controller.
> >> Clearly it's a separate IP block, with it's own clock and reset controls.
> >
> > It's been merged together in the A23, hence why we did it like that.
>
> I'm not sure I understand. The clock gate and reset control are still separate,
> are they not?
On the A31 the "regular" port controler handles PA to PH banks, while
the R_PIO handles the PL and PM banks.
On the A23, the regular port controler handles PA to PL banks, and the
R_PIO and PM bank doesn't exist.
So we're not quite in the same situation. The A31 is troublesome,
while the A23 (except for the external interrupts), is pretty much
what we've seen so far with the A10/A20/...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Thu, Apr 10, 2014 at 01:14:26AM +0800, Chen-Yu Tsai wrote:
> > 3) other things I haven't noticed yet :-)
>
> Reworking EINT to use one interrupt per bank will yield some more surprises.
>
> There's also new gpiolib irqchip helpers, but that will require reworking
> each pin bank into separate gpio chips. May be more work than just adding
> different irq domains for different banks.
>
> See: https://lkml.org/lkml/2014/3/25/175
I'm not sure it's worth it actually. Using these helpers will probably
simplify the A31/A23 case, where you have one interrupt controller per
bank, but it will be much more complicated to handle the A10/A20 case
where you have a single interrupt controller for all the banks.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
On Thu, Apr 10, 2014 at 4:10 PM, Maxime Ripard
<[email protected]> wrote:
> On Thu, Apr 10, 2014 at 12:27:32AM +0800, Chen-Yu Tsai wrote:
>> >> > Let me know if these changes are too intrusive.
>> >>
>> >> I wonder if we should do a separate driver for the new PIO controller.
>> >> Clearly it's a separate IP block, with it's own clock and reset controls.
>> >
>> > It's been merged together in the A23, hence why we did it like that.
>>
>> I'm not sure I understand. The clock gate and reset control are still separate,
>> are they not?
>
> On the A31 the "regular" port controler handles PA to PH banks, while
> the R_PIO handles the PL and PM banks.
>
> On the A23, the regular port controler handles PA to PL banks, and the
> R_PIO and PM bank doesn't exist.
On closer inspection of the user manual and the SDK code,
there is no reset control for R_PIO in the A23, but there is
still a APB0 gate. Also the register space is still at 0x01f02c00,
the address space for R_PIO.
I know the user manual lists the PL pins under the PIO controller,
however the section doesn't list registers for them. It would seem
they are still separate blocks. Also the kernel code never bothers
to enable the R_PIO clock, possibly because it was enabled by U-boot.
> So we're not quite in the same situation. The A31 is troublesome,
> while the A23 (except for the external interrupts), is pretty much
> what we've seen so far with the A10/A20/...
On Wed, Apr 9, 2014 at 3:51 PM, Boris BREZILLON
<[email protected]> wrote:
> Specify base pio clk name when retrieving it using the CCF.
> This way we will avoid conflicts when introducing a second clk for the A31
> SoC.
>
> Signed-off-by: Boris BREZILLON <[email protected]>
Are you merging all these through ARM SoC?
In that case
Acked-by: Linus Walleij <[email protected]>
If it's OK to merge stand-alone tell me and I'll apply it to
the pinctrl tree.
Yours,
Linus Walleij
On Thu, Apr 10, 2014 at 8:14 PM, Linus Walleij <[email protected]> wrote:
> On Wed, Apr 9, 2014 at 3:51 PM, Boris BREZILLON
> <[email protected]> wrote:
>
>> Specify base pio clk name when retrieving it using the CCF.
>> This way we will avoid conflicts when introducing a second clk for the A31
>> SoC.
>>
>> Signed-off-by: Boris BREZILLON <[email protected]>
>
> Are you merging all these through ARM SoC?
>
> In that case
> Acked-by: Linus Walleij <[email protected]>
>
> If it's OK to merge stand-alone tell me and I'll apply it to
> the pinctrl tree.
Hm there seems to be quite a few patches to pinctrl here...
May I apply this and the others to the pinctrl tree simply?
As DTS files should be maintained separately I don't think
it's important to keep driver and DTS file changes together.
Yours,
Linus Walleij
Hello Linus,
On 10/04/2014 20:16, Linus Walleij wrote:
> On Thu, Apr 10, 2014 at 8:14 PM, Linus Walleij <[email protected]> wrote:
>> On Wed, Apr 9, 2014 at 3:51 PM, Boris BREZILLON
>> <[email protected]> wrote:
>>
>>> Specify base pio clk name when retrieving it using the CCF.
>>> This way we will avoid conflicts when introducing a second clk for the A31
>>> SoC.
>>>
>>> Signed-off-by: Boris BREZILLON <[email protected]>
>> Are you merging all these through ARM SoC?
>>
>> In that case
>> Acked-by: Linus Walleij <[email protected]>
>>
>> If it's OK to merge stand-alone tell me and I'll apply it to
>> the pinctrl tree.
> Hm there seems to be quite a few patches to pinctrl here...
>
> May I apply this and the others to the pinctrl tree simply?
Actually I made a v2 (and then a v3 https://lkml.org/lkml/2014/4/10/320
:-)) of this series, in which I removed all DT related stuff.
So, if you agree with these changes, I guess you can take them through
you tree.
Best Regards,
Boris
>
> As DTS files should be maintained separately I don't think
> it's important to keep driver and DTS file changes together.
>
> Yours,
> Linus Walleij
--
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com